CN107785366B - 集成有结型场效应晶体管的器件及其制造方法 - Google Patents

集成有结型场效应晶体管的器件及其制造方法 Download PDF

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CN107785366B
CN107785366B CN201610793832.2A CN201610793832A CN107785366B CN 107785366 B CN107785366 B CN 107785366B CN 201610793832 A CN201610793832 A CN 201610793832A CN 107785366 B CN107785366 B CN 107785366B
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jfet
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CN107785366A (zh
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顾炎
程诗康
张森
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CSMC Technologies Fab2 Co Ltd
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Abstract

本发明涉及一种集成有结型场效应晶体管的器件及其制造方法，所述器件的JFET区包括：JFET源极，为第一导电类型；第一阱，为第二导电类型，设于第一导电类型区内且形成于JFET源极两侧；JFET源极的金属电极，形成于JFET源极上，与JFET源极接触；JFET金属栅极，设于JFET源极两侧的第一阱上；钳位区，位于JFET金属栅极的下方、第一阱内，为第二导电类型且离子浓度大于第一阱的离子浓度。本发明通过第二导电类型的钳位区提高了第一阱的离子浓度，增强了沟道区的耗尽能力，使得JFET夹断电压稳定性会有一定程度的提高。同时钳位区的存在会增强该处电场强度，改变雪崩电流的路径，提升了器件的稳定性。

Description

集成有结型场效应晶体管的器件及其制造方法
技术领域
本发明涉及半导体制造技术，特别是涉及一种集成有结型场效应晶体管的器件，还涉及一种集成有结型场效应晶体管的器件的制造方法。
背景技术
在高压工艺平台上集成高压结型场效应晶体管(Junction Field-EffectTransistor，JFET)为如今智能功率集成电路领域的一种先进开发与构想，它可以大大提升纵向功率器件的开态性能，以及显著的减小芯片面积，符合当今智能功率器件制造的主流趋势。
传统结构的高压集成JFET有较简单的工艺可以实现，但其夹断电压的不稳定限制了其在智能功率集成领域的大规模应用。
发明内容
基于此，有必要针对传统的JFET夹断电压不稳定的问题，提供一种集成有结型场效应晶体管的器件。
一种集成有结型场效应晶体管的器件，所述器件包括JFET区和功率器件区，设于所述器件背面的第一导电类型的漏极，和设于所述漏极朝向所述器件正面的面上的第一导电类型区，所述JFET区和功率器件区共享所述漏极和第一导电类型区；所述JFET区还包括：JFET源极，为第一导电类型；第一阱，为第二导电类型，设于所述第一导电类型区内且形成于所述JFET源极两侧；JFET源极的金属电极，形成于所述JFET源极上与所述JFET源极接触；JFET金属栅极，设于所述JFET源极两侧的所述第一阱上；钳位区，位于所述JFET金属栅极的下方、所述第一阱内，为第二导电类型且离子浓度大于所述第一阱的离子浓度；所述第一导电类型和第二导电类型为相反的导电类型。
在其中一个实施例中，所述JFET区和功率器件区交界处形成有一所述第一阱，作为JFET区和功率器件区的隔离。
在其中一个实施例中，所述JFET区形成有：沟槽，所述沟槽的内壁覆盖有氧化硅，所述JFET金属栅极填充于覆盖有所述氧化硅的沟槽内；欧姆接触区，形成于第一阱内与所述沟槽的底部接触处，为第二导电类型，与所述JFET金属栅极相接触。
在其中一个实施例中，所述器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
在其中一个实施例中，所述功率器件区包括栅极、第二阱、设于所述第二阱内的第一导电类型的VDMOS源极，所述第二阱的底部也设置有第二导电类型的钳位区。
在其中一个实施例中，各所述第二阱内形成有沟槽，所述垂直双扩散金属氧化物半导体场效应晶体管还包括VDMOS源极的金属接触，各第二阱内与所述沟槽的底部接触处形成有第二导电类型的欧姆接触区，所述VDMOS源极的金属接触填充于所述功率器件区的沟槽内、贯穿所述VDMOS源极并延伸至所述欧姆接触区，所述欧姆接触区的离子浓度大于所述第二阱的离子浓度。
在其中一个实施例中，在所述功率器件区的第二阱内，所述VDMOS源极和所述欧姆接触区之间还形成有第二导电类型的非钳位感性开关区，所述非钳位感性开关区的离子浓度大于所述第二阱的离子浓度。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
还有必要提供一种集成有结型场效应晶体管的器件的制造方法。
一种集成有结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，所述方法包括：提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；所述第一导电类型和第二导电类型为相反的导电类型；向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；先后生长场氧层和栅氧层，在所述第一导电类型区表面形成多晶硅层，向所述功率器件区的所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱；向所述功率器件区的第二阱中注入第一导电类型的离子，形成功率器件源极；向所述JFET区的两相邻第二阱之间注入第一导电类型的离子，形成JFET源极；光刻并刻蚀接触孔，向所述接触孔内注入第二导电类型的离子，在所述第一阱内以及所述第二阱底部形成钳位区，所述钳位区的离子浓度大于所述第一阱的离子浓度；淀积金属层并填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
在其中一个实施例中，所述在所述第一导电类型区内形成第一阱的步骤，包括在所述JFET区和功率器件区交界处形成第一阱作为JFET区和功率器件区的隔离。
在其中一个实施例中，所述向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱的步骤中，是以所述场氧层和多晶硅层为掩膜进行注入。
在其中一个实施例中，所述形成功率器件源极的步骤和所述形成JFET源极的步骤之间，还包括步骤：形成注入阻挡层，所述场氧层和多晶硅层的表面也叠加上所述注入阻挡层；向所述功率器件区的所述第二阱中注入第二导电类型的离子，以在所述第二阱内所述功率器件源极的下方形成非钳位感性开关区，注入能量大于所述向所述功率器件区的第二阱中注入第一导电类型的离子的步骤的注入能量，叠加有所述注入阻挡层的场氧层和多晶硅层将注入的第二导电类型的离子阻挡。
在其中一个实施例中，所述光刻并刻蚀接触孔的步骤之前，还包括步骤：在各所述第一阱和各所述第二阱内刻蚀沟槽；向所述沟槽注入第二导电类型的离子，在每一第二阱内与所述沟槽的底部接触处，以及在每一第一阱内与所述沟槽的底部接触处形成第二导电类型的欧姆接触区；所述JFET金属栅极由填入所述第一阱内的沟槽的金属层形成，所述功率器件源极的金属接触由填入所述第二阱内的沟槽的金属层形成。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层，所述功率器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
上述集成有结型场效应晶体管的器件及其制造方法，通过第二导电类型的钳位区提高了第一阱的离子浓度，增强了沟道区的耗尽能力，使得JFET夹断电压稳定性会有一定程度的提高。同时钳位区的存在会增强该处电场强度，改变雪崩电流的路径，提升了器件的稳定性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一种传统的高压集成JFET的剖面结构示意图；
图2是一实施例中集成有结型场效应晶体管的器件的剖面结构示意图；
图3是仿真得到的图2所示器件在不同漏极电压Vd下的夹断电压比较曲线；
图4是一实施例中集成有结型场效应晶体管的器件的制造方法的流程图；
图5a～5e是图3所述的制造方法在制造过程中的器件剖面结构示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
一种传统的集成高压结型场效应晶体管(Junction Field-Effect Transistor，JFET)的垂直双扩散金属氧化物半导体场效应晶体管(Vertical Double-diffusedMOSFET，VDMOS)的结构如图1所示。包括栅极101、源极102、高压P阱103、体接触104、N型外延层105以及N+接触106。
当VDMOS处于开启阶段时，电流从底部漏端流过JFET，从source2流出。当source2上加逐渐变大的电压Vg2，同时栅gate上也加同样的电压Vg1，当Vg2>夹断电压Voff时，JFET的耗尽层阻断了电流，即发生了夹断。此时Vg1>Vth，VDMOS开启，完成了一个开启过程。JFET在此吸收了DMOS在米勒平台时的突变电流，让启动更为平缓，电流可以成近似线性变换，所以JFET在启动过程中对器件稳定性提升有着很显著作用。功率器件在其工艺平台上集成寄生JFET则更具有优势。
集成寄生JFET，其最主要特性是整体击穿电压的稳定性和夹断电压的稳定性，最为理想的是，集成后器件的击穿电压保持不变，击穿点最好保持在功率VDMOS的击穿点。传统的集成结构VDMOS与JFET交接处仅用了衬底进行隔离，仅可以拉长衬底外延的横向距离来保证耗尽时的余量，这样会增加整个管芯的面积。同时，由于外延层规范有所偏差，工艺上略有变动就会出现击穿点转移，击穿点会从体内的cell区转移至JFET区或是交接处，大大降低了击穿的稳定性，还会发生击穿电压蠕变的现象。传统结构一般用自对准P型注入的衬底作为P型夹断衬底，由于VDMOS的元胞(cell)的P型衬底其纵向结深很浅，一般只有3～5微米，因此JFET的纵向沟道很短，人为无法去调整纵向沟道长度，所以夹断电压很不稳定。通过仿真可得知当漏端电压从50V到100V变化时，夹断电压Voff会从11V变大至20V，而在实际应用中需要Voff稳定，因此该传统结构难以满足实际需求。
图2是一实施例中集成有结型场效应晶体管的器件的剖面结构示意图，在本实施例中，定义N型为第一导电类型，P型为第二导电类型，功率器件为VDMOS。如图2中所述，将器件按结构分为JFET区和VDMOS区，JFET区和VDMOS区共享设于器件背面(即图2中朝下的面)的N型的漏极201，和设于漏极201正面(即图2中朝上的面)的N型区214。在本实施例中，漏极201为N+漏极，N型区214为N-外延层，作为VDMOS的漂移区(在其他实施例中也可以直接使用N型衬底)。
在本实施例中，JFET区包括JFET源极208、JFET源极的金属电极212、JFET金属栅极213、第一阱202以及钳位区210。
P-的第一阱202设于N型区214内且形成于N+的JFET源极208的两侧，在图2所示实施例中，JFET源极208伸入两侧的第一阱202内。JFET源极的金属电极212形成于JFET源极208上，与JFET源极208接触。JFET金属栅极213设于JFET源极208两侧的第一阱202上。P型的钳位区210位于JFET金属栅极213的下方、第一阱202之内，且离子浓度大于第一阱202的离子浓度。
上述集成有结型场效应晶体管的器件，通过钳位区210提高了第一阱202的离子浓度，增强了沟道区的耗尽能力，使得JFET夹断电压稳定性会有一定程度的提高。同时钳位区210的存在会增强该处电场强度，改变雪崩电流的路径，提升了器件的稳定性。
钳位区210采用高能的P型离子注入，以获得足够的注入深度。在其中一个实施例中注入能量为480kev左右。钳位区210能够固化击穿点。
在图2所示实施例中，JFET区和VDMOS区交界处形成有一个第一阱202，作为JFET区和VDMOS区的隔离。利用P-的第一阱202辅助耗尽隔离，通过较深的P-阱隔离，可以完全阻断电流的流通路径，防止JFET和VDMOS间的漏电，且在器件反偏耐压时可以辅助下方的N-外延层(即N型区214)参与耗尽，提升局部区域的击穿电压来固化击穿点作用。同时，该第一阱202作为结终端扩展技术中终端的耗尽结构，能够有效缩短高压VDMOS的芯片面积。另外由于该结终端扩展的结工艺存在，P-阱结深大大超过了传统技术中VDMOS的P型衬底的结深，从而有了较长的纵向电流沟道。相较于传统结构，器件的夹断电压稳定性会提高较多，同时夹断电压也会显著降低。在其中一个实施例中，第一阱202的阱深为8.5微米～13.5微米。
在图2所示实施例中，VDMOS区包括栅极(栅极包括栅氧层203和多晶硅栅204)、第二阱205、设于第二阱205内的N+的VDMOS源极206，且VDMOS区同样包括P型的钳位区210，其设于第二阱205的底部。
在图2所示实施例中，VDMOS区的第二阱205和JFET区的第一阱202内形成有沟槽，VDMOS区设有VDMOS源极的金属接触211，各第二阱205内与沟槽的底部接触处以及各第一阱202内与沟槽的底部接触处形成有P型的欧姆接触区209，VDMOS源极的金属接触211填充于VDMOS区的沟槽内、向下贯穿VDMOS源极206并延伸至欧姆接触区209。JFET金属栅极213填充于JFET区的沟槽内并向下延伸至欧姆接触区209。欧姆接触区209的离子浓度大于第二阱205的离子浓度。
在图2所示实施例中，在VDMOS区的第二阱205内、VDMOS源极206和欧姆接触区209之间，还形成有P型的非钳位感性开关(Unclamped Inductive Switching,UIS)区207。非钳位感性开关区207的离子浓度大于第二阱205的离子浓度。
图3是仿真得到的图2所示器件在不同漏极电压Vd下的夹断电压比较曲线其中横坐标为源极电压，纵坐标为漏极电流。通过SILVACO软件对不同漏极电压Vd下进行仿真，可以看出当漏极电压Vd分别为50V、100V、200V和600V时的夹断电压变化。从50V到200V的区间内夹断电压变化维持在线性0.5V左右的变化。当漏极电压Vd升高为600V时，夹断电压增加了5V，这是由于热模型添加，高电压情况下器件内载流子有较高温度，动量加大，运动速率加快，单位时间内通过截面的电荷数增加，电流变大，所以在夹断时电流会表现增加，这是正常现象。图5的仿真中针对的是击穿电压为650V器件，上述结型场效应晶体管基本做到了在正常使用范围内夹断电压可控。上述结型场效应晶体管同样适用于外延层加厚之后的超高压器件，以及低压的沟槽栅器件。
上述集成有结型场效应晶体管的器件的主要优势在于提高了原始集成JFET沟道夹断的稳定性。以其较深的纵向沟道的特点，降低了漏极电压Vd对源极表面电势的影响，提高了夹断电压的稳定性，所以结深的增加是本发明结构的其中一个关键所在。第一阱202同时作为VDMOS的结终端扩展环，最深的深度由它的终端技术所限制，但此时已大大超过了耗尽型JFET的P阱所需要的深度，所以二者可以兼容。
图4是一实施例中集成有结型场效应晶体管的器件的制造方法的流程图，以下以功率器件是VDMOS，第一导电类型是N型，第二导电类型是P型为例，介绍集成有结型场效应晶体管的器件的制造方法：
S510，提供第一导电类型的衬底，衬底上形成有第一导电类型区。
在本实施例中，是在N+衬底上外延形成N型区214，衬底后续将会作为器件的漏极201。
S520，注入第二导电类型的离子并推阱，在第一导电类型区内形成第一阱。
在本实施例中，是向N型区214中注入P型离子并推阱，在N型区214内形成第一阱202。图5a是步骤S520完成后器件的剖面结构示意图。
S530，生长场氧层和栅氧层，形成多晶硅层，注入第二导电类型的离子并推阱形成多个第二阱。
生长厚的场氧层然后生长栅氧层，并在N型区214表面形成多晶硅层604，再以场氧层和多晶硅层604为掩膜向N型区214注入P型离子，推阱形成多个第二阱205。第二阱205的离子浓度大于第一阱202的离子浓度。图5b是步骤S530完成后器件的剖面结构示意图。
S540，向功率器件区的第二阱中注入第一导电类型的离子，形成功率器件源极。
向VDMOS区的第二阱205注入N型离子，形成VDMOS源极206。
参见图5c，在本实施例中，注入N型离子形成VDMOS源极206的步骤之后，还包括向功率器件区的第二阱205中注入P型离子的步骤，以在第二阱205内的VDMOS源极206的下方形成非钳位感性开关区207。为了防止向第二阱205中注入的P型离子对沟道区造成不利影响，本实施例中在注入P型离子形成非钳位感性开关区207的步骤之前，还包括形成注入阻挡层的步骤。在本实施例中形成注入阻挡层是通过再形成一层氧化层，由于注入P型离子形成非钳位感性开关区207的注入窗口处的氧化层较薄，因此高能注入的P型离子可以穿过氧化层形成非钳位感性开关区207。而其他位置处的氧化层形成于场氧层、多晶硅层604等结构上，因此整个注入阻挡层的厚度较厚，P型离子难以穿过注入阻挡层进入N型区214内。
S550，向JFET区的两相邻第二阱之间注入第一导电类型的离子，形成JFET源极。
在本实施例中，是通过光刻和刻蚀去除JFET源极208上方的介质和多晶硅层604，然后注入N型杂质，在N型区214的表面形成JFET源极208。多余的多晶硅层604被去除后形成图5d所示的多晶硅栅204。图5d是步骤S550完成后器件的剖面结构示意图。
S560，光刻并刻蚀接触孔，向接触孔内注入第二导电类型的离子形成钳位区。
参见图5e，在本实施例中，步骤S560之前还包括在各第二阱205和第一阱202内刻蚀出沟槽602的步骤。本步骤需要分两次向第二阱205注入P型离子，其中第一次注入在栅极两侧的第二阱205内与沟槽602的底部接触处、以及在源极208两侧的第一阱202内与沟槽602的底部接触处形成P型的欧姆接触区209，第二次注入在栅极两侧的第二阱205的底部、以及源极208两侧的第一阱202内形成P型的钳位区210。
S570，淀积金属层并填入接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
淀积的金属层填入JFET区的第二阱205内的沟槽602，形成JFET金属栅极213，填入功率器件区的第二阱205内的沟槽602，形成VDMOS源极的金属接触211。淀积金属层后在器件表面形成钝化层，完成后器件的剖面如图2所示。
在其中一个实施例中，注入形成P型的钳位区210为高能P型注入，注入能量为480kev左右。
在VDMOS部分引入深槽(沟槽602)加P+注入(形成非钳位感性开关区207)的结构，其目的是提升VDMOS器件的UIS特性。在传统的高压VDMOS工艺中，通过UIS注入来加强器件UIS能力，但受限于注入深度和浓度分散，效果不甚理想。深槽刻蚀VDMOS的cell区，去除了多余的N型杂质，并集中注入了P型离子，增加了UIS过程中电子泄放路径，大大加强了器件的UIS能力。
上述集成有结型场效应晶体管的器件的制造方法，器件中的第二阱205可以是VDMOS中cell区的P型衬底，但P型衬底的浓度受限于VDMOS中cell设计参数，因而在需精确调整的情况下是还需加入专门调节第二阱205的光刻，此光刻与DMOS工艺兼容，所以在整个工艺中的光刻总层数是不变的。
综合上述优势，上述集成有结型场效应晶体管的器件在传统技术的基础上提升了夹断电压的稳定性，固化了击穿点，加强了UIS能力，工艺上完全匹配，并且实现了夹断电压大小的可调性。
在其中一个实施例中，步骤S520包括在JFET区和功率器件区交界处形成一个第一阱202作为JFET区和功率器件区的隔离。
在其中一个实施例中，步骤S520的第一阱202的注入浓度为1.5E13 cm-2～2.2E13cm-2，形成的第一阱202的阱深为8.5微米～13.5微米。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (14)

1.一种集成有结型场效应晶体管的器件，所述器件包括JFET区和功率器件区，设于所述器件背面的第一导电类型的漏极，和设于所述漏极朝向所述器件正面的面上的第一导电类型区，所述JFET区和功率器件区共享所述漏极和第一导电类型区；其特征在于，所述JFET区还包括：
JFET源极，为第一导电类型；
第一阱，为第二导电类型，设于所述第一导电类型区内且形成于所述JFET源极两侧；
JFET源极的金属电极，形成于所述JFET源极上并与所述JFET源极接触；
JFET金属栅极，设于所述JFET源极两侧的所述第一阱上；
钳位区，位于所述JFET金属栅极的下方、所述第一阱内，为第二导电类型且其离子浓度大于所述第一阱的离子浓度；所述第一导电类型和第二导电类型为相反的导电类型。
2.根据权利要求1所述的集成有结型场效应晶体管的器件，其特征在于，所述JFET区和功率器件区交界处形成有一所述第一阱，作为JFET区和功率器件区的隔离。
3.根据权利要求1所述的集成有结型场效应晶体管的器件，其特征在于，所述JFET区形成有：
沟槽，所述沟槽的内壁覆盖有氧化硅，所述JFET金属栅极填充于覆盖有所述氧化硅的沟槽内；
欧姆接触区，形成于第一阱内的与所述沟槽的底部接触处，为第二导电类型，且与所述JFET金属栅极相接触。
4.根据权利要求1所述的集成有结型场效应晶体管的器件，其特征在于，所述器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
5.根据权利要求4所述的集成有结型场效应晶体管的器件，其特征在于，所述功率器件区包括栅极、第二阱、设于所述第二阱内的第一导电类型的VDMOS源极，所述第二阱的底部也设置有第二导电类型的钳位区。
6.根据权利要求5所述的集成有结型场效应晶体管的器件，其特征在于，各所述第二阱内形成有沟槽，各第二阱内与所述沟槽的底部接触处形成有第二导电类型的欧姆接触区，所述器件还包括VDMOS源极的金属接触，所述VDMOS源极的金属接触填充于所述功率器件区的沟槽内、贯穿所述VDMOS源极并延伸至所述欧姆接触区，所述欧姆接触区的离子浓度大于所述第二阱的离子浓度。
7.根据权利要求6所述的集成有结型场效应晶体管的器件，其特征在于，在所述功率器件区的第二阱内，所述VDMOS源极和所述欧姆接触区之间还形成有第二导电类型的非钳位感性开关区，所述非钳位感性开关区的离子浓度大于所述第二阱的离子浓度。
8.根据权利要求1-7中任意一项所述的集成有结型场效应晶体管的器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
9.一种集成有结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，其特征在于，所述方法包括：
提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；所述第一导电类型和第二导电类型为相反的导电类型；
向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；
先后生长场氧层和栅氧层，在所述第一导电类型区表面形成多晶硅层，向所述功率器件区的所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱；
向所述功率器件区的第二阱中注入第一导电类型的离子，形成功率器件源极；
向所述JFET区的两相邻第二阱之间注入第一导电类型的离子，形成JFET源极；
光刻并刻蚀接触孔，向所述接触孔内注入第二导电类型的离子，在所述第一阱内以及所述第二阱底部形成钳位区，所述钳位区的离子浓度大于所述第一阱的离子浓度；
淀积金属层并填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
10.根据权利要求9所述的方法，其特征在于，所述在所述第一导电类型区内形成第一阱的步骤，包括在所述JFET区和功率器件区交界处形成第一阱作为JFET区和功率器件区的隔离。
11.根据权利要求9所述的方法，其特征在于，所述向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱的步骤中，是以所述场氧层和多晶硅层为掩膜进行注入。
12.根据权利要求11所述的方法，其特征在于，所述形成功率器件源极的步骤和所述形成JFET源极的步骤之间，还包括步骤：
形成注入阻挡层，所述场氧层和多晶硅层的表面也叠加上所述注入阻挡层；
向所述功率器件区的所述第二阱中注入第二导电类型的离子，以在所述第二阱内所述功率器件源极的下方形成非钳位感性开关区，注入能量大于所述向所述功率器件区的第二阱中注入第一导电类型的离子的步骤的注入能量，叠加有所述注入阻挡层的场氧层和多晶硅层将注入的第二导电类型的离子阻挡。
13.根据权利要求9所述的方法，其特征在于，所述光刻并刻蚀接触孔的步骤之前，还包括步骤：
在各所述第一阱和各所述第二阱内刻蚀沟槽；
向所述沟槽注入第二导电类型的离子，在每一第二阱内与所述沟槽的底部接触处，以及在每一第一阱内与所述沟槽的底部接触处形成第二导电类型的欧姆接触区；所述JFET金属栅极由填入所述第一阱内的沟槽的金属层形成，所述功率器件源极的金属接触由填入所述第二阱内的沟槽的金属层形成。
14.根据权利要求9-13中任意一项所述的方法，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层，所述功率器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
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