CN102037562A - 隔离的晶体管和二极管、用于半导体管芯的隔离和终端结构 - Google Patents

隔离的晶体管和二极管、用于半导体管芯的隔离和终端结构 Download PDF

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CN102037562A
CN102037562A CN2009801150268A CN200980115026A CN102037562A CN 102037562 A CN102037562 A CN 102037562A CN 2009801150268 A CN2009801150268 A CN 2009801150268A CN 200980115026 A CN200980115026 A CN 200980115026A CN 102037562 A CN102037562 A CN 102037562A
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isolation
substrate
region
groove
conduction type
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CN102037562B (zh
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唐纳德·R·迪斯尼
理查德·K·威廉斯
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Advanced Analog Technology Inc
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Advanced Analog Technology Inc
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Abstract

各种集成电路器件，尤其是晶体管，形成在包括底隔离区域和从所述衬底的表面延伸到该底隔离区域的沟槽的隔离结构内部。该沟槽可由电介质材料填充或可以具有在中心部分的导电材料以及装衬该沟槽的壁的电介质材料。通过延伸该底隔离区域超出沟槽、采用保护环以及形成漂移区的用于终端所述隔离结构的各种技术被描述。

Description

隔离的晶体管和二极管、用于半导体管芯的隔离和终端结构
相关申请的交叉引用
本申请是于2008年2月14日提交的申请No.12/069,941的部分继续申请。
本申请是于2007年8月8日提交的申请No.11/890,993的部分继续申请。申请No.11/890,993是于2006年5月31日提交的申请No.11/444,102的继续申请，且是下述申请的部分继续申请：(a)于2004年8月14日提交的申请No.10/918,316，其是于2002年8月14日提交的、现在为美国专利No.6,900,091的申请No.10/218,668的分案申请；(b)于2005年8月15日提交的申请No.11/204,215，其是2002年8月14日提交的、现在为美国专利No.6,943,426的申请No.10/218,678的分案申请。上述每个申请和专利通过引用全部结合于此。
背景技术
在制造半导体集成电路(IC)芯片的过程中，经常需要使不同的器件与半导体衬底电隔离并使不同的器件彼此电隔离。提供器件之间的横向隔离的一种方法是公知的硅局部氧化(LOCOS，Local Oxidation OfSilicon)工艺，其中芯片的表面用相对硬的材料，诸如硅氮化物作为掩模，较厚的氧化层在掩模的开口中热生长。另一种方法是在硅中刻蚀沟槽，然后用诸如硅氧化物的电介质材料填充该沟槽，这也被称为沟槽隔离。尽管LOCOS和沟槽隔离两者能够防止之间不期望的表面导通，但它们并不便于完全的电隔离。
需要完全的电隔离以集成某些类型的晶体管，包括双极结型晶体管和各种金属氧化物半导体(MOS)晶体管(包括功率DMOS晶体管)。还需要完全的隔离以允许在操作期间CMOS控制电路浮置到高于衬底电势很多的电势。完全的隔离在模拟、功率和混合信号集成电路的制造中也尤其重要。
尽管常规的CMOS晶片制造提供了高密度的晶体管集成，但它不便于所制造的器件的完全电隔离。具体地，包含在制作于P型衬底中的常规CMOS晶体管对中的NMOS晶体管具有短路到衬底的P阱“体”或“背栅”，因此不能浮置在接地电势之上。该限制实质上妨碍了NMOS用作高压侧开关(high-side switch)、模拟传输晶体管(pass transistor)或用作双向开关。这也使得电流检测更加困难，并经常妨碍集成的源极-体短路的使用，需要该短路以使得NMOS更加雪崩强化(avalanche rugged)。此外，由于常规CMOS中的P型衬底通常被偏置到最负的芯片上电势(定义为“接地电势”)，所以每个NMOS必然经受不期望的衬底噪声。
集成器件的完全电隔离典型地采用三重扩散、外延结隔离或电介质隔离来实现。最普遍形式的完全电隔离是结隔离。尽管不像电介质隔离(其中氧化物围绕每个器件或电路)那样理想，但是结隔离已经在历史上提供了制造成本与隔离性能之间的最好折衷。
对于常规的结隔离，使CMOS电隔离需要一复杂结构，该复杂结构包括在P型衬底上生长N型外延层，该N型外延层被电连接到P型衬底的深P型隔离的环形环围绕，以形成完全被隔离的N型外延岛，该完全被隔离的N型外延岛在其下方和所有侧面上具有P型材料。外延层的生长较慢并且耗时，代表了半导体晶片制造过程中最昂贵的单个步骤。隔离扩散也比较昂贵，使用高温扩散来进行并且持续时间延长(达到18小时)。为了能够抑制寄生器件，在外延生长之前重掺杂的N型埋层(NBL)也必须被遮蔽并被选择性地引入。
为了在外延生长和隔离扩散期间使向上扩散最小化，选择慢扩散剂诸如砷(As)或锑(Sb)来形成N型埋层(NBL)。然而，在外延生长之前，该NBL层必须扩散得足够深以减小其表面浓度，否则外延生长的浓度控制将被不利地影响。因为NBL包括慢扩散剂，所以该外延之前的扩散工艺将耗费十小时以上。只有在隔离完成之后，才能开始常规CMOS制造，从而与常规CMOS工艺相比为结隔离工艺的制造增加了相当可观的时间和复杂性。
结隔离制造方法依赖于高温工艺，以形成深扩散结并生长外延层。这些高温工艺昂贵且难以进行，且它们无法与大直径晶片制造兼容，在器件电性能上表现出了相当大的可变性并妨碍了高的晶体管集成密度。结隔离的另一缺点是，存在被隔离结构浪费掉而不能用于制造有源晶体管或电路的面积。作为进一步的复杂，通过结隔离，设计规则(和浪费面积的量)取决于被隔离器件的最大电压。显然，常规外延结隔离尽管其具有电学优点，但是在面积上过于浪费而不能为混合信号和功率集成电路保留可行的技术选择。
用于使集成电路器件隔离的备选方法在美国专利No.6,855,985中公开，其通过引用结合于此。其中公开的用于集成充分被隔离的CMOS、双极晶体管和DMOS(BCD)晶体管的模块工艺可以不需要高温扩散或外延而实现。该模块BCD工艺使用通过具有特定轮廓形状的氧化物的高能(MeV)离子注入，以制造自形成的隔离结构，从而实质上不需要高温处理。该低热预算工艺将受益于“原位注入(as-implanted)”的掺杂剂轮廓，由于没有使用高温工艺，所以该掺杂分布经历很少的掺杂剂再扩散或者不经历掺杂剂再扩散。
通过LOCOS场氧化物注入的掺杂剂形成共形的(conformal)隔离结构，其继而被用于围绕多电压的CMOS、双极晶体管和其它器件并使它们与公共的P型衬底隔离。该相同的工艺能用于集成的双极晶体管以及各种双结DMOS功率器件，它们都被不同剂量和能量的共形的链式离子注入(chainedion implantation)调整。
尽管该“无外延的(epi-less)”低热预算的技术与非隔离工艺及外延结隔离工艺相比具有许多优点，但是在某些情况下，其对LOCOS的依赖会限制其按比例缩小到更小的尺寸并获得更高的晶体管密度的能力。在LOCOS基模块BCD工艺中共形离子注入的原理是：通过注入通过较厚的氧化物层，掺杂剂原子将在靠近硅表面的位置；通过注入通过较薄的氧化物层，注入的原子将位于硅中较深的位置而远离表面。
正如所描述的，具有被LOCOS轮廓化的注入并使用基于0.35微米的技术而易于实现的完全隔离BCD工艺可能在按比例缩小到较小的尺寸并获得更紧密的线宽时遇到问题。为了提高CMOS晶体管的集成密度，优选地可以将场氧化物层的鸟嘴锥减小为更垂直的结构，使得器件能够被更密集地放置，以实现更高的封装密度。然而，狭窄的LOCOS鸟嘴会使得隔离侧壁的宽度变窄并且会牺牲隔离质量。
在这些问题显著的情形下，将期望具有使集成电路器件(尤其是高压器件)完全隔离的新策略，其使用低热预算的无外延集成电路工艺，但消除了上述窄侧壁问题以允许更密集的隔离结构。
发明内容
根据发明的实施例大体上形成在不包括外延层的第一导电类型的半导体衬底中。隔离的横向DMOS晶体管(LDMOS)的实施例包括第二导电类型的底隔离区域和从衬底的表面延伸到该底隔离区域的电介质填充的沟槽，该沟槽与该底隔离区域形成衬底的隔离袋。该LDMOS包括在隔离袋中的第一导电类型的阱，该阱作为LDMOS的体部，该阱包括浅部和深部，该浅部位于衬底的表面附近，该深部位于浅部下方，该浅部具有第一掺杂浓度，而该深部具有第二掺杂浓度，该第二掺杂浓度高于该第一掺杂浓度。
在隔离的LDMOS的第二实施例中，沟槽包括在中心部分的导电材料且该沟槽的壁被装衬电介质材料。隔离袋包括邻近漏极区域的第二导电类型的漂移区和隔离袋中邻近衬底表面的浅沟槽隔离(STI)结构，且STI结构被漂移区从侧部及底部围绕。隔离袋可包括位于源极区域和/或漏极区域之下的埋设的第一导电类型的骤回控制区域。
在根据本发明的隔离的准垂直DMOS(QVDMOS)中，沟槽包括在中心部分的导电材料且沟槽的壁装衬有电介质材料。隔离袋包括在衬底表面的第二导电类型的源极区域。电流从源极区域水平通过在栅极之下的沟道区，然后垂直流到底隔离区域，该底隔离区域包括在QVDMOS的漏极中。
在根据本发明的隔离的结场效应晶体管(JFET)中，沟槽包括在中心部分的导电材料且该沟槽的壁装衬有电介质材料。隔离袋在衬底的表面包括第一导电类型的源极区域和漏极区域以及第二导电类型的顶栅极区域。第一导电类型的沟道区位于顶栅极区域的底部与底隔离区域之间。
在隔离的结场效应晶体管(JFET)的第二个实施例中，隔离袋包括第二导电类型的源极区域和漏极区域、衬底表面的第一导电类型的顶栅极区域以及埋设在衬底中的第一导电类型的底栅极区域。第二导电类型的沟道区位于顶栅极区域的底部和底栅极区域的上边界之间。
在根据本发明的耗尽型MOSFET中，沟槽包括在中心部分的导电材料且该沟槽的壁装衬有电介质材料。该隔离袋包括第二导电类型的源极区域和漏极区域且栅极下方的沟道区的掺杂浓度实质上等于衬底的背景掺杂浓度。为了降低碰撞电离以及抑制骤回，第一导电类型的埋设区域可以至少部分形成在栅极下方。
在根据本发明的隔离的二极管中，隔离袋包括第一导电类型的阳极区域。底隔离区域用作二极管的阴极并通过沟槽中的导电材料被接触。
本发明也包括在隔离袋之外、用于作为沟槽的边界的区域的终端结构。第一导电类型的保护环可以在隔离袋之外形成在衬底的表面处，且底隔离区域可以横向延伸超出沟槽的外边缘。第一导电类型的埋设区域可以形成在保护环下方。第二导电类型的漂移区可以形成为邻近衬底的表面以及隔离袋之外的沟槽。包括电介质材料的一个或更多额外的沟槽可以形成在漂移区内或者在沟槽和保护环之间的衬底中。
附图说明
图1示出完全隔离的N沟道横向DMOS(LDMOS)的截面图；
图2示出隔离的N沟道LDMOS的备选实施例的截面图；
图3示出隔离的N沟道准垂直DMOS的截面图；
图4示出隔离的P沟道JFET的截面图；
图5示出隔离的N沟道JFET的截面图；
图6示出N沟道耗尽型MOSFET的截面图。
图7示出隔离的二极管的截面图；
图8示出隔离的齐纳二极管的截面图；
图9A-9D示出用于控制表面电场且用于减少充电及依赖于时间的表面相关现象的终端结构的截面图。
具体实施方式
图1示意性地示出根据本发明制造的完全被隔离的N沟道横向DMOS(LDMOS)400的截面图，该N沟道横向DMOS不需要外延沉积或高温扩散而被制造。LDMOS 400制造在隔离的P型区464中。P型区464及在P型区464内制造的横向DMOS 400通过高能注入的N型底隔离区域(floorisolation region)462及填充有电介质的沟槽463A和463B与P型衬底461隔离。
N沟道LDMOS 400包括：N+漏极区域468B，由注入的N型轻掺杂漏极区域(LDD)469与栅极474隔开，且由LDD 476区域与沟槽463B隔开；栅极474，优选包含多晶硅和/或硅化物；栅极氧化物层472；N+源极区域468A；以及P+体接触区467，接触包括LDMOS 400的体区域的P型阱465。P型阱465可以至少包括上部465A及下部465B或任意数量的包括不同能量和剂量的注入的区域。P型阱465的较深部465B优选可以包括高于P型阱465的上部465A的掺杂浓度。
侧壁间隔物473及轻掺杂源极延伸471是CMOS制造中的人为产物(artifact)，对于LDMOS 400的正常运行其不是有益地被需要。由于其相对高的掺杂浓度，所以源极延伸471对LDMOS 400的影响可以忽略。
底隔离区域462经由N型阱466及N+接触区468D电接触衬底461的表面。阱466所在的区域以沟槽463A和463C为界。显然，沟槽463B和463C可以是呈闭合图形形状的单个沟槽的一部分，且沟槽463A可将衬底461的由沟槽463B和463C围绕的部分分为包括源极区域468A、漏极区域468B和P型阱465的第一部分以及包括阱466的第二部分。
DN底隔离区域462可被电偏置到DMOS漏极区域468B、P型阱464、衬底461的电势，或其他固定或可变的电势。底隔离区域462和漏极区域468B之间的最大电压差被限制为底隔离区域462与漏极区域468B之间的N-I-N穿通击穿(punch-through breakdown)电压，而底隔离区域462和P型阱465之间的最大电压差由底隔离区域462和P型阱465之间的P-I-N透过击穿(reach-through breakdown)电压设定。在一个实施例中，底隔离区域462和漏极区域468B被电短接，消除了N-I-N穿通击穿的可能性，且将LDMOS400的BVDSS限制为P型阱465和DN底隔离区域462之间的P-I-N雪崩击穿电压。在另一实施例中，底隔离区域462和衬底461被电短接，使得P型阱465可被偏置到接地电势以下，即比衬底461更负的电势。另一备选是“浮置”底隔离区域462，其中底隔离区域462的电势可以改变直到到N+漏极区域468B的N-I-N穿通现象发生，这样底隔离区域462的电势将跟随漏极区域468B的电势。
尽管隔离的N沟道LDMOS 400是不对称的，但它也可以被对称地构建，在中心处具有N+漏极区域468B。备选地，LDMOS 400可以以P型阱465为中心而构建。
尽管LDMOS 400的外边缘可以与沟槽463B和463C一致，但在备选实施例中，被偏置为漏极区域468B的电势的N型终端区域478可围绕沟槽463C，且增加了LDMOS 400相对于衬底461的击穿电压。如果沟槽463B和463C都呈闭合图形的形状，则终端区域478可相邻于沟槽463B和463C的整个外周边而设置。LDMOS 400也可被P+衬底接触区474和/或深注入P型区475围绕。
图2示出隔离的N沟道横向DMOS 300的示意图，该DMOS 300制造在P型区341B中，该P型区341B通过深注入N型底隔离区域360和填充沟槽361与P型衬底341A隔离。在优选实施例中，填充沟槽361围绕着LDMOS 300以提供横向隔离，而底隔离区域360提供垂直隔离。沟槽361包括由绝缘侧壁364横向围绕且隔离的导电中心部分363。导电中心部分363提供底隔离区域360和衬底341A的表面之间的电接触，以便于互连。
LDMOS 300包括中心N+漏极区域348B及N型漂移区342，该N型漂移区342被设置在栅极电介质层362顶部的栅极355限制。在优选实施例中，专用注入被用于形成漂移区342，从而调整其掺杂分布，用于优化LDMOS300的性能。在另一实施例中，此专用漂移区342可以被与其他CMOS器件共享的N型阱替代，这在降低生产成本的同时而兼顾了LDMOS 300的性能。
栅极355交叠漂移区342的一部分，并被N+源极区域348A和P+体接触区347围绕。P型阱343，优选包含具有非高斯或非单调掺杂浓度轮廓的硼链式注入区域，局部位于栅极355之下并形成LDMOS 300的体区域。P型阱343可包括非单调掺杂分布，其包括至少上部343A和下部343B或者任意数量的包括不同能量和剂量的注入的区域。P型阱343的下部343B优选包括比P型阱343的上部343A高的掺杂浓度。在图2所示的实施例中，P型阱343的末端与漂移区342横向间隔开。结果，LDMOS 300的沟道具有两种掺杂浓度，P型阱343的较重浓度设定了LDMOS 300的阈值电压并防止了穿通击穿，区域341B的较低浓度决定了LDMOS 300的雪崩击穿电压和碰撞电离。在另一实施例中，P型阱343毗邻漂移区342，其中LDMOS300的沟道具有单一掺杂浓度，其等于P型阱343的掺杂浓度。
漂移区342部分位于浅沟槽隔离(STI)结构346，即，由硅氧化物填充的浅沟槽之下。在漂移区342上方包括STI 346的一个好处在于：位于STI 346下方的漂移区342的净积分电荷因为沟槽形成期间掺杂剂被去除而减少。漂移区342的净积分电荷，以atoms/cm2为单位，是从在STI 346底部的硅氧化物界面到漂移区342底部的漂移区342的掺杂剂浓度的积分，也就是
Q Dtrench = ∫ x trench x j ( drift ) N Ddrift ( x ) dx ≡ α · Q D
变量α代表在STI 346形成之后保留在漂移区342中的注入标准电荷的百分比，即，在刻蚀保持STI 346的沟槽时未被移除的掺杂剂。电荷的减少导致栅极355下方的表面电场的减弱，且与栅极355的场板效应结合，减少了碰撞电离且降低了热载流子损害的风险。
在制造可靠且耐用的高压和功率LDMOS器件时，控制击穿的位置和碰撞电离的数量是重要的考虑。在LDMOS 300中包括体区域343有助于防止穿通击穿并通过限制出现在LDMOS 300中的寄生横向NPN双极晶体管的增益而降低LDMOS 300对双极注入和骤回(snapback)的敏感度，该寄生横向NPN双极晶体管包括由源极区域348A代表的发射极、由体区域343和区域341B代表的基极以及由漏极区域348B和漂移区342代表的集电极。然而，LDMOS 300的体部不能防止由漂移区342中的局部碰撞电离导致的背景掺杂浓度的调制而引发的骤回。
根据本发明，采用两种方法来控制骤回。第一种方法，再次参考图2，注入的深P型区365设置在源极区域348A之下，被用来抑制栅极下方的电场并使高电场的位置向远离高电流密度的区域移动。这种方法在此被称作“表面下屏蔽(subsurface shielding)”，而深P型区365可被称作表面下屏蔽区域。第二种方法是将LDMOS 300的最大漏电压钳位为在骤回发生以下的电压，使得骤回现象不发生。这种方法这里被称作“漏极钳位(drainclamping)”，并可以通过在漏极区域348B下方引入DP区域366来实现。DP区域366将漏极区域348B下方的垂直电场集中以迫使体，即，非表面，雪崩击穿远离对热载流子敏感的栅极电介质层362。DP区域366也可被称作漏极钳位区域。
横向DMOS晶体管的备选者是准垂直DMOS晶体管。在横向DMOS中，电流通过其的轻掺杂漂移区横向流动，即，平行于晶片表面流动。在准垂直DMOS中，电流既横向流动也垂直(即，基本垂直于晶片表面)流动。电流从器件的DMOS表面沟道区流下进入在其中横向流动的重掺杂表面下层，且然后垂直流回到漏极接触，因此得名“准垂直”。
图3示出了N沟道准垂直DMOS(QVDMOS)晶体管500的截面示意图。该器件包括：栅极510，优选形成为一系列的条纹或闭合的几何形状；N+源极区域506；P型体区域504；以及P+体接触区域505。P体区域形成在N型阱502内部，该N型阱502包括QVDMOS 500的漂移区并交叠在N型底隔离区域501上，该底隔离区域501埋设在P型衬底511中并被包括在QVDMOS 500的漏极中。
填充沟槽507横向围绕QVMDOS 500，提供与制造在衬底500中的其他器件的隔离。填充沟槽507的中心部分是从衬底500的表面向下延伸到底隔离区域501的导电材料508。导电材料508被绝缘材料509横向围绕，该绝缘材料509装衬沟槽507的侧壁，使得导电材料508与N-阱502以及衬底511电隔离。当QVDMOS 500处在导通状态时，电子流从N+源极区域506、横向通过形成在P体区域504的表面处的沟道、垂直向下通过N-阱502、横向通过底隔离区域501并且垂直向上通过填充沟槽507中的导电材料508。从而，可以容易地实现从衬底511的表面到源极区域506和漏极(底隔离区域501)的接触。
在P体区域504将不与栅极510自对准的情况下，P体区域504可在栅极510形成之前被注入。备选地，P体区域504可以在栅极510形成之后通过大倾斜角注入被注入，结果P体区域504与栅极510的边缘自对准。大倾斜角注入容许形成P体区域504与栅极510的相当大的交叠，而不需要高温扩散。
在QVMDOS的另一实施列(未图示)中，侧壁间隔物和N型轻掺杂源极区域缘会作为采用同一栅极层的CMOS制造的人为产物而形成在栅极505的每个边缘。如图3所示，如果采用专用栅极层形成栅极505，则器件内将不出现侧壁间隔物。否则，在N+源极区域与栅极510自对准的情况下，N+源极区域与侧壁间隔物自对准而N-源极延伸将与栅极自对准。
如上所述的表面下屏蔽和漏极钳位技术可以与根据本发明制成的漏极和漏极延伸结构的任何变型结合。
JFET和耗尽型MOSFET
不像传统的为“常关”器件的增强型MOSFET，JFET和耗尽型MOSFET即使在它们的栅极被偏置到其源电势时仍然传导漏电流，即，他们在VGS＝0时仍然传导电流。此类器件在形成用于起动电路的电流源时是方便的，因为该晶体管是常“开”的，而其他的晶体管还没有处于操作状态。
在耗尽型N沟道场效应晶体管中，阀值电压必须小于0伏特，使得即使在0伏特或者更大的栅极偏压条件VGS≥0时，该器件仍处于传导状态。虽然JFET的阀值电压被称作其“夹断”电压或Vpn，但N沟道JFET在0伏特栅极驱动时也为“on”。N沟道耗尽型器件和JFET只有通过偏置其栅极至负电势时才能被截止。相反的，正的栅极偏压增加N沟道器件的漏极偏压。然而，N沟道JFET的最大栅极驱动被限制为栅极-到-源极P-N二极管的正向偏置电压。P沟道JFET也在0伏特栅极驱动时工作，但需要通过正的栅极驱动，即，栅极被偏置到高于源极的电势来关闭。
图4示意性地示出隔离的P沟道JFET 100的截面。P沟道JFET 100包括P+漏极区域107、P型沟道区111、包括N+区域106和可选的N型区域108的N型顶栅、包括N型底隔离区域102的底栅以及P+源极区域105。N型栅极的长度LG优选为1微米到20微米，且由顶栅-N+区域106或N型区域108中较长的长度定义。
JFET 100通过底隔离区域102与P型衬底101垂直地隔离，而由填充沟槽104与P型衬底101横向隔离。底隔离区域102用作JFET 100的底栅。与衬底101的表面的电接触由填充沟槽104的中心的导电材料112提供。绝缘材料113横向围绕导电材料112，以将导电材料112与衬底101和P沟道区111绝缘。底栅(底隔离区域102)被电偏置到电势“BG”，且该底栅偏压BG可与顶栅(N+区域和N型区域108)电势“TG”成比例地改变，或者BG可被设定为一固定电势。
JFET 100的夹断电压由沟道区111的掺杂浓度和沟道区111在NB区域108与底隔离区域102之间的垂直尺寸决定。在一个实施例中，区域111的掺杂浓度与衬底101的掺杂浓度基本相同。在另一实施例中，通过注入追加的掺杂剂提高了区域111的掺杂浓度，以调整JFET 100的夹断电压。
浅沟槽110可设置在N型区108周围，以将N型区108与源极105和漏极107隔离。在优选实施例中，沟槽110比沟槽104浅且窄，因为沟槽110不应接触底隔离区域102。优选，沟槽107完全由电介质材料填充。
图5示意性地示出隔离的N沟道JFET 200的截面。JFET 200包括N+漏极区域203、N型沟道区204、P型顶栅、底栅以及P+源极区域209，其中P型顶栅包括P+区205和可选的P型区206，底栅包括隔离的P型袋207和可选的深注入P型区208。底栅通过P型阱210和P+底栅接触区211电偏置到电势“BG”。底栅偏压BG可与顶栅的电势“TG”成比例地改变，或者BG可以被设定为一固定电势。JFET 200的夹断电压由N沟道区204的掺杂浓度和厚度决定。
JFET200通过N型底隔离区域202与P型衬底201垂直地隔离，而通过填充沟槽214与P型衬底201横向地隔离。与衬底表面的电接触由填充沟槽214中心部分的导电材料212提供。绝缘材料213横向围绕导电材料212，以将其与衬底201和P型区210、208及207绝缘。
浅沟槽210可设置在P型区206周围，以将顶栅206与源极区域209及漏极区域203隔离。此外，浅沟槽215可以用来将P+底栅接触区211与沟道区204、源极区域209和漏极区域203横向隔离。在优选实施例中，沟槽210和215比沟槽214浅且窄，因为沟槽210和215不应接触底隔离区域202。优选用电介质材料完全填充沟槽210及215。
在另一实施例中，可去除底隔离区域202，使得N沟道JFET 200的底栅包括P型衬底201和/或可选的深P型区208。
图6示意性地示出N沟道耗尽型MOSFET 600的截面。MOSFET 600被构造为与图1所示的隔离的N沟道横向DMOS晶体管400类似，除了隔离袋区664中不存在与P型阱465相当的阱之外。在隔离袋区664中没有P型阱，MOSFET 600的阀值电压由栅极氧化物层672的厚度以及隔离P型袋664的掺杂浓度设定，该隔离P型袋664的掺杂浓度基本等于衬底661的背景掺杂浓度。这个阀值电压可以在大约-0.3V到+0.3V之间变动。即使在阀值电压稍微为正时，MOSFET 600仍然能在VGS＝0时传导足够的电流，以用在起动电路中。
耗尽型N沟道MOSFET的骤回效应类似于增强型MOSFET的骤回效应。防止图2所示的LDMOS 300中的骤回的结构可以以任何组合应用于耗尽型器件。
图6的耗尽型MOSFET 600包括N+漏极区域668B，具有栅极674与漏极区域668B之间的N型LDD漂移区669。栅极674位于栅极电介质层672之上。LDD区678从漏极区域668B延伸到填充沟槽663。轻掺杂源(LDS)区域671，作为CMOS工艺的人为产物，存在于侧壁间隔物673A之下。N+源极区域668A与侧壁间隔物673A自对准。
深P型区675设置在至少部分栅极674之下，并可横向延伸超出栅极674，以部分交叠LDD漂移区669，以降低碰撞电离并抑制骤回(snapback)。深P型区675通过P+体接触区667电连接到衬底661的表面。
栅极674之下的沟道区676中的P-型袋664的浓度基本与P型衬底661的浓度相同。在优选实施例中，DP区675的上部足够深，以避免掺杂沟道区676，从而使MOSFET 600的阀值电压最小化。在其他实施例中，深P型区675的掺杂和深度可被调节，以容许其掺杂分布补充沟道区676中的掺杂，从而使阀值电压增加到期望值。
图6的耗尽型MOSFET和P型衬底661之间在垂直上被N型底隔离区域602隔离，在横向上被横向围绕隔离袋664的填充沟槽663间隔。从衬底661的表面到底隔离区域662的电接触由在填充沟槽663的中心部分的导电材料680提供。绝缘材料681横向围绕导电材料680，以使导电材料与衬底661及隔离袋664绝缘。
耗尽型MOSFET的其他实施例可以与图2的LDMOS 300类似地实现，但没有P体区域343，从而阀值电压较低且由隔离袋341B的掺杂设定，且可能由深P型区365的上部的掺杂确定。
隔离的二极管
在很多功率应用中，例如，期望隔离的高压整流二极管，以在切换变流器时在先开后合间隔期间再循环电感电流。
图7示出隔离的二极管700的一个实施例，该隔离的二极管700包括：N型埋区702，用作二极管700的阴极；以及一个或更多P+接触区707，围绕在隔离的P-型区706内部，用作二极管700的阳极。填充沟槽705横向围绕二极管700，其提供横向隔离，而N型埋区702提供二极管700与P型衬底701的垂直隔离。从衬底701的表面到N型埋区702的电接触由填充沟槽705的中心部分的导电材料712提供。绝缘材料713横向围绕导电材料712，以使导电材料与衬底701及P型区706绝缘。电介质层715形成在衬底701的表面上且被图案化，以形成用于阳极接触716和阴极接触717的开口。
额外的填充沟槽708可以被包括，以将二极管分成较小的P型区且提供与埋区702的较低阻抗的接触。在优选实施例中，隔离的P型区706可以具有与P型衬底701基本相同的掺杂浓度。这在阴极-阳极结处提供了最低可能的掺杂，而容许最高的击穿电压BV。备选地，可以引入额外的P型阱注入以增加区域706中的掺杂浓度，这提供了阳极区域中降低的阻抗并提供了将BV调节至较低值的能力。
在一个实施例中，额外的P型阱706具有非单调掺杂分布，其至少包括上部706A和下部706B，且优选利用不同能量和剂量的硼链式注入形成。在一个实施例中，下部706B相对于上部706A具有更高的掺杂浓度。
在功率集成电路中，经常需要形成齐纳钳压电路，即，旨在在反向偏压中正常工作的P-N二极管，且经常处于雪崩击穿模式，以钳制电路电压到最大值。为了提供适当的保护，齐纳二极管的击穿电压必须被很好地控制在6V到20V之间，而这需要采用具有相对较高的掺杂浓度的P-N结，以产生如此低的BV。表面结，诸如通过交叠浅N+区和P+区形成的结，不能制成可靠的齐纳二极管钳位，因为他们的截面区域太小，且雪崩击穿发生在硅氧化物界面附近。因此，优选利用埋入的P-N结形成齐纳二极管钳位以实现表面下雪崩击穿。
图8示出隔离的齐纳二极管800，其包括了重掺杂的埋入N型阴极区802和重掺杂P型阳极区803。P型阳极区803优选由高剂量、高能量注入形成。从衬底801的表面到阳极区803的接触由P+接触区805和可选的P阱804提供。如果P阱804未被引入，则此区域中的掺杂将与衬底801的掺杂基本相同。从衬底的表面到阴极区802的电接触由填充沟槽806的中心部分的导电材料812提供。绝缘材料813横向围绕导电材料812，以使导电材料与衬底801及P型区803和804绝缘。电介质层815形成在衬底801的表面上且被图案化，以形成用于阳极接触816和阴极接触817的开口。
额外的填充沟槽807可以被包括，以将二极管800分成较小的阳极区803且提供与阴极区802的更低阻抗的接触。
在典型运行中，阴极区802被偏置到等于或高于接地衬底801的电势的电势。阳极区803可相对于阴极反向偏置，达到通过在阳极-阴极结的每侧掺杂而设定的击穿电压。此BV可通过优选用于形成埋入的阳极区和阴极区的高能注入的深度和剂量来调节。举例来说，埋入的阳极区可通过剂量范围为从1E13cm-2到1E14cm-2、能量为从2000到3000keV的磷注入来形成，而阴极区可通过剂量范围为从1E13cm-2到1E14cm-2、能量范围为从400到2000keV的硼注入来形成。
类型I的隔离器件的高压终端
功率集成电路中另一个期望特征是容许隔离器件“浮置”到衬底电势以上的高压的能力。浮置的器件或隔离袋的最高电压不取决于隔离袋内部是什么，而是取决于袋被终端的方式，即，什么特征作为沟槽隔离侧壁的外部的边界。
贯穿该公开所描述的一个方法是用填充沟槽来终端隔离区以及将底隔离区域的横向延伸限制到沟槽的外边缘。如前所述，这些沟槽可完全由电介质材料填充，或者这些沟槽可包括在中心的导电材料以及横向围绕导电材料的电介质材料。虽然该方法能够支持高电压，但它不控制表面电场且可以经历充电和其他的依赖于时间的表面相关现象。
另一方法是用都包括高压“终端”的一个或更多的注入结、场释放区(field relief region)和沟道截断(channel stop)围绕侧壁隔离沟槽的外部或作为侧壁隔离沟槽的外部的边界，如图9A-9D所示的一系列截面图所示。在每个图中，P型袋通过填充沟槽与围绕的衬底横向隔离，并通过注入的底隔离区域被垂直地隔离。尽管填充沟槽示出为在其中心包括导电材料，但在其他实施例中也可以采用完全电介质化的填充沟槽。
图9A-9D的截面所示的隔离P型袋可包含CMOS、DMOS晶体管、JFET和耗尽型MOSFET、NPN和PNP双级晶体管、齐纳和整流二极管，或者甚至是诸如电阻和电容的无源部件的任何组合，所有这些都是根据本发明构建和制成的。每幅图包括“CL”中心线标记，表示旋转轴，从而P型袋在四周由具有环形或闭合几何形状的隔离沟槽围绕。
在每个例子中，DN底隔离区域示出为延伸超出沟槽距离LDN，该距离的大小会在0和数十微米之间在长度上参量地改变。当LDN为0时，DN底隔离区域的横向边缘和沟槽的外边缘重合。DN底隔离区域被假定通过接触交叠的N型阱(比如，如图1所示)或者通过填充沟槽中的导电材料来电偏置。终端的外边缘由P+保护环识别，以防止表面反转且用作沟道截断。尺寸参照沟槽的外边缘以及P+保护环的内边缘。P+保护环可包括位于其下方的可选的深P型DP层，以横向容纳少数载流子，且也可包括作为保护环结构一部分的介入P型阱。
图9A示出包括N型底隔离区域902和填充沟槽904的边缘终端结构，它们一起隔离P型袋903以及任何其所包含的器件与P型衬底901。底隔离区域902延伸超出沟槽904距离LDN。当底隔离区域902被偏置到比衬底901更正的电势时，耗尽区分布进入衬底901在底隔离区域902的延伸部分之上的部分，该耗尽区降低了硅表面的电场。底隔离区域902的边缘与P+保护环905及底层埋设的P型区906的边缘之间的横向距离由尺寸LSUB标出，且其范围为从1微米到数十微米之间。
图9B示出包括底隔离区域912和填充沟槽914的边缘终端结构，它们一起隔离P型袋913以及任何其所包含的器件与P型衬底911。底隔离区域912延伸超出沟槽914长度LDN。长度为LD3的深注入N型漂移区917接触N+区918。漂移区917可被偏置到与底隔离区域912相同的电势，或可以偏置到固定的电势。漂移区917的外边缘与P+保护环915及底层的深P型区916间隔距离LSUB。
漂移区917的作用是通过展示二维耗尽扩散效应来抑制表面电场。假设漂移区917具有充分低的积分电荷QD，典型地在从1×1012cm-2到5×1012cm-2的范围内，增加施加到由漂移区917和P型衬底911形成的P-N结的电压导致耗尽扩散进入漂移区917并最终完全耗尽漂移区917。在这种情况下，漂移区917和本征材料在P-I-N二极管中的行为相似，而表面电场根据众所周知的二维电感生的P-I-N结的REFURF原理而实质上下降。此外，漂移区917在底隔离区域912上方的垂直交叠增强了在区域917和912之间的介入区域内的p型衬底911的耗尽，进一步减弱了终端内的表面电场。
图9C示出包括底隔离区域922和填充沟槽924的边缘终端结构，它们一起隔离P型袋923以及任何其所包含的器件与P型衬底921。底隔离区域922延伸超出沟槽924距离LDN，且与沟槽927隔开距离LSUB。在此实施例中，底隔离区域922和沟槽927之间的间隙，即，尺寸为LSUB的间隙，控制在沟槽924和927之间，即，标识为928的区域的表面区域中的P型衬底921的电势。当底隔离区域922和沟槽927之间的间隙变成完全耗尽时，P型区域928的电势变为浮置。P+保护环925围绕该器件且可以包括底层的深P型区926。
图9D示出包括底隔离区域932和填充沟槽934的边缘终端结构，它们一起隔离P型袋933以及任何其所包含的器件与P型衬底931。底隔离区域932延伸超出沟槽934。深注入N型漂移区937接触N+区938。漂移区937可被偏置到与底隔离区域932相同的电势，或者可以偏置到固定的电势。在漂移区937内，形成一个或更多填充沟槽939。每个沟槽939降低了漂移区937中的局部掺杂浓度，这容许漂移区937的相邻部分更容易被耗尽，从而进一步减弱了局部电场。在优选实施例中，沟槽939较沟槽934更窄且浅，并完全由电介质材料填充。在一个实施例中，器件被设计为使得沟槽939的表面面积占漂移区937的表面面积的比例随着距沟槽934的横向距离的增加而增加。这使得漂移区937的距隔离袋933最远的部分比更靠近隔离袋933的部分更容易耗尽，从而提供了与渐次变化(graded)的结终端相似的效果，这对最小化支持给定的BV所需要的横向距离是有效的。漂移区937的外边缘与P+保护环935以及底层的深P型区936间隔距离LSUB。
这里所描述的实施例旨在是示意性的而不是限制。根据这里的描述，在本发明的广阔范围内的许多备选实施例对本领域的技术人员而言是明显的。

Claims (47)

1.一种隔离的晶体管，形成在第一导电类型的半导体衬底中，所述衬底不包括外延层，所述隔离的晶体管包括：
与所述第一导电类型相反的第二导电类型的底隔离区域，埋设在所述衬底中；
第一沟槽，从所述衬底的表面至少延伸到所述底隔离区域，所述沟槽包括电介质材料，且所述沟槽和所述底隔离区域一起形成所述衬底的隔离袋；
源极区域，为所述第二导电类型，且在所述隔离袋中位于所述衬底的表面；
漏极区域，为所述第二导电类型，在所述隔离袋中位于所述衬底的表面且与所述源极区域间隔开；
栅极，在所述源极区域与所述漏极区域之间位于所述衬底的表面上方；
沟道区，在所述栅极下方邻近所述衬底的表面；以及
漂移区，为所述第二导电类型，在所述漏极区域与所述源极区域之间位于所述隔离袋中。
2.如权利要求1所述的隔离的晶体管，包括第二沟槽，该第二沟槽从所述衬底的表面至少延伸到所述底隔离区域，所述第二沟槽填充有电介质材料且将所述隔离袋分为第一部分和第二部分，所述源极区域、所述漏极区域和所述漂移区以及阱定位在所述第一部分中，所述第二部分包括从所述衬底的表面延伸到所述底隔离区域的所述第二导电类型的第二阱。
3.如权利要求1所述的隔离的晶体管，其中所述第一沟槽包括导电的中心部分，该导电的中心部分通过电介质材料与所述衬底和所述隔离袋隔离。
4.如权利要求1所述的隔离的晶体管，其中所述隔离袋的掺杂浓度与所述衬底的掺杂浓度基本相同。
5.如权利要求4所述的隔离的晶体管，其中所述隔离的晶体管具有范围为从-0.3伏特到+0.3伏特的阈值电压。
6.如权利要求1所述的隔离的晶体管，包括所述隔离袋中的所述第一导电类型的阱，所述阱包括所述沟道区。
7.如权利要求6所述的隔离的晶体管，其中所述阱包括浅部和深部，所述深部位于所述浅部之下，且所述深部的掺杂浓度高于所述浅部的掺杂浓度。
8.如权利要求1所述的隔离的晶体管，包括设置在所述源极区域之下的第一导电类型的表面下屏蔽区域，所述表面下屏蔽区域的掺杂浓度高于所述隔离袋的掺杂浓度。
9.如权利要求1所述的隔离的晶体管，包括设置在所述漏极区域之下的第一导电类型的漏极钳位区域，所述漏极钳位区域的掺杂浓度高于所述隔离袋的掺杂浓度。
10.如权利要求1所述的隔离的晶体管，包括第二沟槽，在至少部分所述漂移区上方设置在所述衬底的表面。
11.如权利要求10所述的隔离的晶体管，其中所述第二沟槽包括电介质材料，且具有小于所述第一沟槽的深度。
12.一种隔离的横向DMOS晶体管，形成在第一导电类型的半导体衬底中，所述衬底不包括外延层，所述隔离的DMOS晶体管包括：
与所述第一导电类型相反的第二导电类型的底隔离区域，埋设在所述衬底中；
沟槽，从所述衬底的表面至少延伸到所述底隔离区域，所述沟槽包括中心导电部分以及电介质材料，所述沟槽和所述底隔离区域一起形成所述衬底的隔离袋，所述电介质材料将所述导电部分与所述隔离袋和所述衬底隔离；
源极区域，为所述第二导电类型，且在所述隔离袋中位于所述衬底的表面；
漏极区域，为所述第二导电类型，在所述隔离袋中位于所述衬底的表面且与所述源极区域间隔开；
栅极，在所述源极区域与所述漏极区域之间在所述衬底的表面区域上方且位于栅极电介质层顶部；
漂移区，为所述第二导电类型，且在所述隔离袋中邻近所述衬底的表面以及所述漏极区域，所述漂移区的掺杂浓度小于所述漏极区域的掺杂浓度；以及
浅沟槽隔离(STI)结构，在所述隔离袋中邻近所述衬底的表面，所述漂移区围绕所述STI结构的侧边及底部。
13.如权利要求12所述的隔离的横向DMOS晶体管，其中所述漏极区域由所述栅极和所述源极区域横向围绕。
14.如权利要求13所述的隔离的横向DMOS晶体管，包括隔离袋中的第一导电类型的阱，所述阱延伸到所述栅极下方。
15.如权利要求14所述的隔离的横向DMOS晶体管，其中所述阱与所述漂移区间隔开。
16.如权利要求14所述的隔离的横向DMOS晶体管，其中所述阱邻接所述漂移区。
17.如权利要求12所述的隔离的横向DMOS晶体管，包括在所述源极区域下方且埋设在所述隔离袋中的第一导电类型的表面下屏蔽区域，所述骤回控制区域的掺杂浓度高于所述隔离袋的掺杂浓度。
18.如权利要求12所述的隔离的横向DMOS晶体管，包括第一导电类型的漏极钳位区域，在所述漏极区域下方且埋设在所述隔离袋中，所述第二骤回控制区域的掺杂浓度高于所述隔离袋的掺杂浓度。
19.一种隔离的横向耗尽型晶体管，形成在第一导电类型的半导体衬底中，所述衬底不包括外延层，所述隔离的耗尽型晶体管包括：
与所述第一导电类型相反的第二导电类型的底隔离区域，埋设在所述衬底中；
沟槽，从所述衬底的表面至少延伸到所述底隔离区域，所述沟槽包括电介质材料，所述沟槽和所述底隔离区域一起形成所述衬底的隔离袋；
源极区域，为所述第二导电类型，且在所述隔离袋中位于所述衬底的表面；
漏极区域，为所述第二导电类型，在所述隔离袋中位于所述衬底的表面且与所述源极区域间隔开；
栅极，在所述源极区域与所述漏极区域之间在所述衬底的表面区域上方且位于栅极电介质层顶部；以及
沟道区，为所述第一导电类型，在所述栅极下方且邻近所述衬底的表面，
其中所述衬底具有背景掺杂浓度，所述背景掺杂浓度和所述沟道区的掺杂浓度基本相等。
20.如权利要求19所述的隔离的横向耗尽型晶体管，包括所述隔离袋中的第一导电类型的埋设区域，所述埋设区域的掺杂浓度大于所述衬底的背景掺杂浓度，且至少部分所述埋设区域位于所述栅极下方。
21.如权利要求20所述的隔离的横向耗尽型晶体管，包括第一导电类型的接触区域，该接触区域从所述衬底的表面延伸到所述埋设区域，且所述接触区域的掺杂浓度高于所述衬底的背景掺杂浓度。
22.如权利要求19所述的隔离的横向耗尽型晶体管，其中所述沟槽具有由导电材料填充的中心部分以及装衬所述沟槽的壁的电介质材料。
23.一种隔离的准垂直DMOS(QVDMOS)晶体管，形成在第一导电类型的半导体衬底中，所述衬底不包括外延层，所述隔离的QVDMOS晶体管包括：
与所述第一导电类型相反的第二导电类型的底隔离区域，埋设在所述衬底中；
沟槽，从所述衬底的表面至少延伸到所述底隔离区域，所述沟槽具有中心导电部分和装衬所述沟槽的壁的电介质材料，所述沟槽和所述底隔离区域一起形成所述衬底的隔离袋；
源极区域，为所述第二导电类型，且在所述隔离袋中位于所述衬底的表面；
栅极，在所述衬底的表面区域上方邻近所述源极区域且位于栅极电介质层顶部；
体区域，为所述第一导电类型，在所述隔离袋中且所述体区域延伸到所述栅极下方；以及
漂移区，为第二导电类型，在所述隔离袋中且在所述底隔离区域与所述体区域之间延伸。
24.如权利要求23所述的隔离的QVDMOS晶体管，其中所述QVDMOS晶体管的漏极包括所述底隔离区域。
25.如权利要求23所述的隔离的QVDMOS晶体管，其中所述中心导电部分提供从所述底隔离区域到所述衬底的表面的接触。
26.一种结场效应晶体管(JFET)，形成在第一导电类型的半导体衬底中，所述衬底不包括外延层，所述隔离的JFET包括：
与所述第一导电类型相反的第二导电类型的底隔离区域，埋设在所述衬底中；
沟槽，从所述衬底的表面至少延伸到所述底隔离区域，所述沟槽包括电介质材料，所述沟槽和所述底隔离区域一起形成所述衬底的隔离袋；
源极区域，在所述隔离袋中位于所述衬底的表面；
漏极区域，在所述隔离袋中在所述衬底的表面且与所述源极区域间隔开；
顶栅区域，在所述源极区域与所述漏极区域之间位于所述衬底的表面；以及
沟道区，延伸在所述源极区域与所述漏极区域之间，在所述顶栅区域下方且在所述底隔离区域上方。
27.如权利要求26所述的隔离的JFET，包括在所述源极区域与所述顶栅区域之间的第一电介质填充沟槽以及在所述漏极区域与所述顶栅区域之间的第二电介质填充沟槽。
28.如权利要求26所述的隔离的JFET，其中所述沟槽具有由导电材料填充的中心部分以及装衬所述沟槽的壁的电介质材料。
29.如权利要求26所述的隔离的JFET，其中所述源极区域、所述漏极区域和所述沟道区为所述第一导电类型，而所述顶栅为所述第二导电类型。
30.如权利要求26所述的隔离的JFET，其中所述源极区域、所述漏极区域和所述沟道区为第二导电类型，而所述顶栅为所述第一导电类型。
31.一种隔离的结场效应晶体管(JFET)，形成在第一导电类型的半导体衬底中，该衬底不包括外延层，所述隔离的JFET包括：
与所述第一导电类型相反的第二导电类型的底隔离区域，埋设在所述衬底中；
沟槽，从所述衬底的表面至少延伸到所述底隔离区域，所述沟槽包括电介质材料，且所述沟槽和所述底隔离区域一起形成所述衬底的隔离袋；
源极区域，为所述第二导电类型，且在所述隔离袋中位于所述衬底的表面；
漏极区域，为所述第二导电类型，在所述隔离袋中位于所述衬底的表面且与所述源极区域间隔开；
顶栅区域，为所述第一导电类型，且在所述隔离袋中设置在所述源极区域与所述漏极区域之间；
底栅区域，为所述第一导电类型，且在所述顶栅区域下方埋设在所述隔离袋中；以及
沟道区，为所述第二导电类型，在所述源极区域与所述漏极区域之间延伸，所述沟道区位于所述顶栅区域下方且在所述底栅区域上方。
32.如权利要求31所述的隔离的JFET，包括位于所述源极区域与所述顶栅区域之间的第一电介质填充沟槽和位于所述漏极区域与所述顶栅区域之间的第二电介质填充沟槽。
33.如权利要求31所述的隔离的JFET，包括第一导电类型的阱，在所述隔离袋中且从所述衬底的表面延伸到所述底栅区域。
34.如权利要求33所述的隔离的JFET，其中所述阱包括邻近所述衬底的表面的底栅接触区域，该底栅接触区域的掺杂浓度高于所述阱的其他部分的掺杂浓度，且其中所述隔离的结场效应晶体管(JFET)包括邻近所述衬底的表面以及所述底栅接触区域的第三电介质填充沟槽。
35.如权利要求31所述的隔离的JFET，其中所述沟槽具有由导电材料填充的中心部分以及装衬所述沟槽的壁的电介质材料。
36.一种隔离的结场效应晶体管(JFET)，形成在第一导电类型的半导体衬底中，该衬底不包含外延层，所述隔离的JFET包括：
与所述第一导电类型相反的第二导电类型的底隔离区域，埋设在所述衬底中；
沟槽，从所述衬底的表面至少延伸到所述底隔离区域，所述沟槽包括电介质材料，且所述沟槽和所述底隔离区域一起形成所述衬底的隔离袋；
源极区域，为所述第一导电类型，且在所述隔离袋中位于所述衬底的表面；
漏极区域，为所述第一导电类型，在所述隔离袋中位于所述衬底的表面且与所述源极区域间隔开；
顶栅区域，为所述第二导电类型，在所述隔离袋中在所述衬底的表面设置在所述源极区域与所述漏极区域之间；以及
沟道区，为所述第一导电类型，在所述源极区域与所述漏极区域之间延伸，所述沟道区定位在所述顶栅区域下方且所述底隔离区域上方。
37.如权利要求36所述的隔离的JFET，包括邻近所述源极区域和所述顶栅区域且在所述源极区域和所述顶栅区域之间的第一电介质填充沟槽以及邻近所述漏极区域和所述顶栅区域且在所述漏极区域与所述顶栅区域之间的第二电介质填充沟槽。
38.如权利要求36所述的隔离的JFET，其中所述沟槽具有由导电材料填充的中心部分以及装衬所述沟槽的壁的电介质材料，所述导电材料提供从所述底隔离区域到所述衬底的表面的接触。
39.如权利要求36所述的隔离的JFET，其中所述底隔离区域包括所述JFET的底栅。
40.一种隔离的二极管，形成在第一导电类型的半导体衬底中，所述衬底不包括外延层，所述隔离的二极管包括：
与所述第一导电类型相反的第二导电类型的底隔离区域，埋设在所述衬底中；
沟槽，从所述衬底的表面至少延伸到所述底隔离区域，所述沟槽具有由导电材料填充的中心部分以及装衬所述沟槽的壁的电介质材料，所述导电材料提供从所述底隔离区域到所述衬底的表面的电接触，且所述沟槽和所述底隔离区域一起形成所述衬底的隔离袋；以及
阳极区域，为第一导电类型，且在所述隔离袋中，所述阳极区域从所述衬底的表面延伸到所述底隔离区域。
41.如权利要求40所述的隔离的二极管，包括：
电介质层，在所述衬底的表面上方，该电介质层在所述阳极区域上方具有第一开口且在所述导电材料上方具有第二开口；
阳极接触，在所述第一开口中且接触所述阳极区域；以及
阴极接触，在所述第二开口中且接触所述导电材料。
42.如权利要求40所述的隔离的二极管，其中所述阳极区域包括浅部和深部，所述浅部靠近所述衬底的表面，所述深部位于所述浅部之下，所述浅部具有第一掺杂浓度，所述深部具有第二掺杂浓度，所述第二掺杂浓度高于所述第一掺杂浓度。
43.一种隔离结构，形成在第一导电类型的半导体衬底中，该衬底不包括外延层，所述隔离结构包括：
与所述第一导电类型相反的第二导电类型的底隔离区域，埋设在所述衬底中；
沟槽，从所述衬底的表面至少延伸到所述底隔离区域，所述沟槽包括电介质材料，所述沟槽和所述底隔离区域一起形成所述衬底的隔离袋；
保护环，为第一导电类型，在所述隔离袋之外且在所述衬底的表面处，所述保护环的掺杂浓度高于所述衬底的掺杂浓度，
其中所述底隔离区域在朝着所述保护环的方向上延伸超出所述沟槽的外边缘一预定距离。
44.如权利要求43所述的隔离结构，包括在所述保护环下方的第一导电类型的埋设区域，该埋设区域的掺杂浓度高于所述衬底的掺杂浓度。
45.如权利要求43所述的隔离结构，包括在所述隔离袋之外邻近所述衬底的表面和所述沟槽的第二导电类型的漂移区，所述漂移区与所述保护环间隔开。
46.如权利要求45所述的隔离结构，至少包括第二沟槽，所述第二沟槽包括电介质材料并从所述衬底的表面延伸进入所述漂移区，所述第二沟槽的底位于所述漂移区中。
47.如权利要求43所述的隔离结构，包括从所述衬底的表面延伸的第二沟槽，该第二沟槽位于所述第一沟槽与所述保护环之间，且与所述底隔离区域的横向边缘间隔开。
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