TWI415262B - 半導體晶粒之隔離電晶體、隔離二極體及隔離與終端結構 - Google Patents

半導體晶粒之隔離電晶體、隔離二極體及隔離與終端結構 Download PDF

Info

Publication number
TWI415262B
TWI415262B TW098106510A TW98106510A TWI415262B TW I415262 B TWI415262 B TW I415262B TW 098106510 A TW098106510 A TW 098106510A TW 98106510 A TW98106510 A TW 98106510A TW I415262 B TWI415262 B TW I415262B
Authority
TW
Taiwan
Prior art keywords
region
isolation
substrate
trench
conductivity type
Prior art date
Application number
TW098106510A
Other languages
English (en)
Other versions
TW200945589A (en
Inventor
Donald R Disney
Richard K Williams
Original Assignee
Advanced Analogic Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Analogic Tech Inc filed Critical Advanced Analogic Tech Inc
Publication of TW200945589A publication Critical patent/TW200945589A/zh
Application granted granted Critical
Publication of TWI415262B publication Critical patent/TWI415262B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

半導體晶粒之隔離電晶體、隔離二極體及隔離與終端結構
本專利申請案係2008年2月14日歸檔的專利申請案第12/069,941號的部分連續申請案。
本專利申請案係2007年8月8日歸檔的專利申請案第11/890,993號的部分連續申請案。專利申請案第11/890,993號係2006年5月31日歸檔的專利申請案第11/444,102號的連續申請案及下列專利申請案的部分連續申請案：(a)2004年8月14日歸檔的專利申請案第10/918,316號，其係2002年8月14日歸檔的專利申請案第10/218,668號的一部分，現為美國專利第6,900,091號；及(b)2005年8月15日歸檔的專利申請案第11/204,215號，其係2002年8月14日歸檔的專利申請案第10/218,678號的一部分，現為美國專利第6,943,426號。上述專利申請案及專利之每一者的全部內容以提及方式併入本文中。
在半導體積體電路(IC)晶片之產製中，經常需要使半導體基板與不同裝置電隔離，且使該等不同裝置彼此電隔離。在數個裝置之間提供橫向隔離(lateral isolation)的一種方法係為人熟知的局部矽氧化(LOCOS)程序，其中晶片表面係以一相對較硬的材料(如氮化矽)遮罩，及在該遮罩中的一開口中熱生長一厚氧化層。另一方式係在矽中蝕刻一溝渠，及接著在該溝渠中填入一介電材料，如氧化矽，其亦名為溝渠隔離(trench isolation)。雖然LOCOS及溝渠隔離兩者可避免裝置之間的多餘表面傳導，但是其等無法促進完全電隔離。
完全電隔離對於整合包含雙極接面電晶體之特定類型電晶體和包含功率DMOS電晶體之各種金屬氧化物半導體(MOS)電晶體而言係必要的。完全電隔離亦需要允許CMOS控制電路在操作期間浮動至在基板電位之上的電位井。完全電隔離在類比、功率及混合信號積體電路之產製中尤其重要。
雖然傳統CMOS晶圓產製給予高密度晶圓整合度，但是其不會促進其產製裝置之完全電隔離。特定言之，包含在產製於一P型基板中之傳統CMOS電晶體對中的NMOS電晶體具其有P井「主體」或「背閘極」，其短路於該基板且因此無法浮動在接地之上。此限制係基本的，避免NMOS作為一高端開關、一類比傳輸型電晶體或作為一雙向開關。其亦使電流感測更加困難，且時常妨礙需要使NMOS突崩更加強健之整合源極-主體短路之使用。另外，由於傳統CMOS中的P型基板一般而言係偏壓於大部分的負晶載電位(定義為「接地」)，每一NMOS必需要經受多餘的基板雜訊。
典型言之，使用三重擴散、磊晶接面隔離或介電隔離達到積體裝置之完全電隔離。最常見之完全電隔離係接面隔離。雖然其不如介電隔離般理想，其中氧化物圍繞各裝置或電路；接面隔離具有歷史上給予製造成本與隔離效能之間的最佳折衷。
以傳統的接面隔離，電絕離一CMOS需求一複雜結構，其包括在由一深P型隔離之環形圈圍繞的一P型基板頂部上生長一N型磊晶層，該深P型隔離之環形圈電連接至該P型基板，以形成在所有側邊之下及之上具有P型材料的一完全隔離N型磊晶島狀區。磊晶層之生長係緩慢的且耗時，其意味著半導體晶圓產製中唯一最為昂貴的步驟。使用用於長時間持續時間(長至18小時)之高溫擴散執行的隔離擴散亦為昂貴的。為了能夠抑制寄生裝置，亦必須在磊晶生長之前遮罩及選擇性地引入一重摻雜N型埋藏層(NBL)。
為了最小化磊晶生長期間的再擴散(up-diffusion)及隔離擴散，選擇一如砷(As)或銻(Sb)的緩慢擴散體以形成該N型埋藏層(NBL)。然而，在磊晶生長之前，此NFL層必須充分地深入擴散，以減小其表面濃度，不然磊晶生長的濃度控制將會不利地受到影響。因為該NBL包括一緩慢擴散體，此預磊晶擴散(pre-epitaxy diffusion)程序可佔用十小時以上。傳統的CMOS產製僅會在隔離完成之後才開始，與傳統CMOS程序相比，對接面隔離程序之製造增加了相當多的時間及複雜性。
接面隔離產製方法仰賴高溫處理，以形成深擴散接面及生長該磊晶層。此等高溫程序係昂貴的且難以執行，及其與大直徑之晶圓製造不相容，會在裝置電性能中展現出明顯變動且阻止高電晶體積體密度。接面隔離的另一缺點係，隔離結構會浪費其面積，否則無法用於產製主動電晶體或電路。接面隔離進一步的障礙係，其設計規則(及經浪費面積的數量)取決於隔離裝置之最大電壓。顯然地，不論傳統磊晶接面隔離的電效益如何，其太浪費面積以致無法對混合信號及功率積體電路保留一可實行技術選項。
美國專利第6,855,985號揭示用於隔離積體電路裝置之一替代性方法，其係引用的方式併入本文中。揭示於其中的模組程序用於整合完全隔離的CMOS，可不需使用高溫擴散或磊晶而達成雙極及DMOS(BCD)電晶體。此模組BCD程序使用透過輪廓相吻之氧化物的高能量(MeV)離子植入，以產生自行成形的隔離結構，其實際上不要求高溫處理。此低熱預算程序效益得自「離子剛植入後(as-implanted)」的摻雜分佈，其由於無運用高溫程序而經歷少許或無摻雜重新分布。
植入透過一LOCOS場氧化物的摻雜物形成保形隔離結構，其依序用以封圍及隔離多電壓CMOS、雙極電晶體及其它裝置和共用P型基板。相同程序亦可整合雙極電晶體及各種雙接面DMOS功率裝置，皆使用不同劑量及能量之保形及連鎖離子植入定製。
雖然此「少磊晶(epi-less)」低熱預算技術具有許多優點勝於非隔離及磊晶接面隔離程序，但在某些情況中，其依賴LOCOS可能對其能力強加特定限制，以按比例調整至較小的尺寸及更高的電晶體密度。基於LOCOS之模組BCD程序中的保形離子植入的原則係，藉由植入透過一較厚氧化層，摻雜原子將會定位在靠近於矽表面，及藉由植入透過一較薄氧化層，該等經植入的原子將定位在遠離矽表面之矽中的更深層處。
如上述，雖然使用一0.35微米為主之技術輕易地實施具有輪廓相吻於LOCOS之植入物的一完全隔離BCD程序，但在按比例調整至較小之尺寸及較密的線寬時可能會遭遇到問題。為了提昇CMOS電晶體積體密度，其較佳係使該場氧化層之鳥喙錐形減小為一更垂直的結構，使得該等裝置可放置的更加緊密用於較高的堆積密度。然而，LOCOS的窄鳥喙可造成隔離側壁的寬度變得窄化，且可能犧牲隔離品質。
在此等問題係顯著的情況下，需求具有一新對策用於完全隔離的積體電路裝置，特別係高電壓裝置，其使用一低熱預算、少磊晶積體電路程序，但是消除上述窄側壁問題的該一方法允許更緊密的隔離結構。
根據此發明之具體實施例一般形成在一第一導電率類型之一半導體基板中，其不包含一磊晶層。一隔離之橫向DMOS電晶體(LDMOS)的具體實施例包括一第二導電率類型之一底板隔離區，及從該基板之一表面延伸至該底板隔離區的一介電質填充溝渠，該溝渠及該底板隔離區形成該基板的一隔離凹穴。該LDMOS包含第一導電率類型之一井，其在當作該LDMOS之主體的該隔離凹穴中，該井包括一淺部分及一深部分，該淺部分係鄰接該基板之表面，該深部分係位在該淺部分之下，該淺部分具有一第一摻雜濃度，該深部分具有一第二摻雜濃度，該第二摻雜濃度係大於該第一摻雜濃度。
在一隔離LDMOS的一第二具體實施例中，該溝渠在中心部分包括一導電材料，且該溝渠之壁係加襯有一介電材料。該隔離凹穴包括第二導電率類型之一漂移區，其鄰接汲極區；及一淺溝渠隔離(STI)結構，其鄰接該隔離凹穴中之該基板的表面，該STI結構由該漂移區封圍其側邊及底部。該隔離凹穴亦可包括第一導電率類型之潛沒突返(snapback)控制區，其位於源極區及/或汲極區之下。
在根據本發明之一隔離準垂直DMOS(QVDMOS)中，該溝渠在中心部分包括一導電材料，且該溝渠之壁係加襯有一介電材料。該隔離凹穴包括在基板之表面處的第二導電率類型之一源極區。電流水平地從該源極區流過置於一閘極之下的一通道區且接著垂直地流至包括在該QVDMOS之汲極中的底板隔離區。
在根據本發明之一隔離接面場效電晶體(JFET)中，該溝渠在中心部分包括一導電材料，且該溝渠之壁係加襯有一介電材料。該隔離凹穴包括在基板之表面處的第一導電率類型之源極區及汲極區，及第二導電率類型之頂部閘極區。第一導電率類型之一通道區係位於該頂部閘極區之一底部與該底板隔離區之間。
在一隔離接面場效電晶體(JFET)之一第二具體實施例中，該隔離凹穴包括在基板之表面處的第二導電率類型之源極區及汲極區，及第一導電率類型之頂部閘極區，和潛沒在該基板中的第一導電率類型之底部閘極區。第二導電率類型之一通道區係位於該頂部閘極區之一底部與該底部閘極區之一上邊界之間。
在根據本發明之一空乏模式MOSFET中，該溝渠在中心部分包括一導電材料，且該溝渠之壁係加襯有一介電材料。該隔離凹穴包括第二導電率類型之源極區及汲極區，及閘極之下之通道區的摻雜濃度大體上等於基板之背景摻雜濃度。為了減小碰撞電離及抑制突返，可至少部分地在該閘極之下形成第一導電率類型之一潛没區。
在根據本發明之一隔離二極體中，該隔離凹穴包括第一導電率類型之一陽極區。底板隔離區當作該二極體的陰極，且經由該溝渠中的導電材料接觸。
本發明亦包括圍住該隔離凹穴外之溝渠之區域的終端結構。可在該隔離凹穴外之基板的一表面處形成第一導電率類型之一護圈，及底板隔離區可橫向地延伸出該溝渠之外側邊緣。可在該護圈下面形成第一導電率類型之一潛沒區。第二導電率類型之一漂移區可形成鄰接該基板之表面及該隔離凹穴外之溝渠。可在該漂移區中或在該溝渠與該護圈之間的基板中形成包括一介電材料的一或多個額外溝渠。
圖1說明根據此發明製作且無需磊晶沈積或高溫擴散產製的一完全隔離N通道橫向DMOS(LDMOS)400的示意剖面圖。該LDMOS 400係產製在隔離P型區464中。P型區464及產製在P型區464中的該橫向DMOS 400藉由高能量植入之N型底板隔離區462及介電填充溝渠463A及463B而與P型基板461隔離。
該N通道LDMOS 400包括：N+汲極區468B，其藉由植入N型輕摻雜汲極(LDD)區469與閘極474間隔開，及藉由LDD區476與溝渠463B間隔開；閘極474，較佳係包括多晶矽及/或矽化物；閘極氧化層472；N+源極區468A；P+主體接觸區467，其接觸一包括LDMOS 400之主體區的P型井465。P型井465可包括至少一上方部分465A及一下方部分465B，或任何數量之包括改變能量或劑量之植入物的區域。較佳地，P型井465之較深部分465B包括一高於P型井465之上方部分465A的摻雜濃度。
側壁間隔物473及輕摻雜源極延伸部471係CMOS產製的人工製品，且不利於所需要的LDMOS 400之適當操作。因為其相對較高的摻雜濃度，故可忽略源極延伸部471對LDMOS 400產生的影響。
底板隔離區462透過N型井466及N+接觸區468D與基板461之表面電接觸。井466係位在由溝渠463A及463C界限的一區域中。應明白，溝渠463B及463C可為一形狀為封閉圖形之單一溝渠的部分，及溝渠463A可將由溝渠463B及463C封圍之基板461的部分分割成一第一區段及一第二區段，其中該第一區段包含源極區468A、汲極區468B及P型井465，及該第二區段包含井466。
DN底板隔離區462可被電偏壓至DMOS汲極區468B、P型井464、基板461之電位，或某些其它固定或可變電位。底板隔離區462與汲極區468B之間的最大電壓差動係限制在底板隔離區462與汲極區468B之間的N-I-N衝穿崩潰電壓，而底板隔離區462與P型井465之間的最大電壓差動係由底板隔離區462與P型井465之間的P-I-N透穿崩潰電壓所設定。在一具體實施例中，該底板隔離區462及汲極區468B係互相電短路，排除N-I-N衝穿崩潰電壓的可能性及限制LDMOS 400的BVDSS 在P型井465與DN底板隔離區462之間的P-I-N突崩崩潰電壓。在另一具體實施例中，該底板隔離區462及該基板461係互相電短路，使得該P型井465可被偏壓低於接地，即，偏壓至比該基板461更負電位的一電位。另一替代方案係，「浮動」該底板隔離區462，在此情況中，可改變該底板隔離區462的電位直到發生N-I-N衝穿至N+汲極區468B，隨之該底板隔離區462的電位將會跟隨汲極區468B的電位。
雖然該隔離N通道LDMOS 400係非對稱性的，但其在中心處亦可構造成與N+汲極區468B對稱。或者，LDMOS 400可在中心處以P型井465構造。
雖然該LDMOS 400的外邊緣可與溝渠463B及463C相重合，在一替代性具體實施例中，在汲極區468B之電位偏壓的N型終端區478可圍繞溝渠463C及增加LDMOS 400相對於基板461的崩潰電壓。若溝渠463B及463C的形狀係一封閉圖形，則可將終端區478置於鄰接該等溝渠463B及463C之整個外周邊。LDMOS 400亦可由P+基板接觸區474及/或由深植入P型區475所圍繞。
圖2顯示一隔離N通道橫向DMOS 300的示意剖面圖，其產製在一P型區341B中，該P型區341B藉由深植入N型底板隔離區360及填充溝渠361而與P型基板341A相隔離。在一較佳具體實施例中，填充溝渠361圍繞該LDMOS 300以提供橫向隔離，且該底板隔離區360提供垂直隔離。溝渠361包括一導電中心部分363，其由絕緣側壁364橫向性圍繞，該絕緣側壁364與該導電中心部分363相隔離。為了易於互連，該導電中心部分363提供底板隔離區360與基板341A之表面之間的電接觸。
該LDMOS 300包括一中心N+汲極區348B及N型漂移區342，中心N+汲極區348B及N型漂移區342係由佈置在閘極介電層362頂部上的閘極355外接。在一較佳具體實施例中，使用一專用植入物以形成漂移區342，以定製其摻雜分佈，用於LDMOS 300的最佳效能。在另一具體實施例中，使用一與其它CMOS裝置共用的N型井取代該專用漂移區342，其危及LDMOS 300的效能但能減少處理成本。
閘極355重疊漂移區342的一部分，且由N+源極區348A和P+主體接觸區347圍繞。P型井343較佳係包括一硼鏈植入區，其具有一非高斯(non-Gaussian)或非單調的摻雜濃度分佈，該P型井343下層疊覆閘極355及形成LDMOS 300的主體區。P型井343可包括一非單調摻雜分佈，其包含至少一上方部分343A及一下方部分343B，或任何數量之包括改變能量或劑量之植入物的區域。較佳地，P型井343之該下方部分343B包括一高於P型井343之該上方部分343A的摻雜濃度。在圖2所示的具體實施例中，P型井343之末端與漂移區342橫向地間隔開。所以，LDMOS 300的通道具有兩個摻雜濃度：P型井343之較重濃度，其設定LDMOS 300的臨限電壓及防止衝穿崩潰；及P型區341B之較輕濃度，其決定LDMOS 300的突崩崩潰電壓及碰撞電離。在另一具體實施例中，P型井343毗連漂移區342，在此情況中，LDMOS 300的通道具有一等於P型井343之摻雜濃度的單一摻雜濃度。
漂移區342部分地佈置在淺溝渠隔離(STI)結構346的下面，即，填充有氧化矽的一淺溝渠。在漂移區345上包括STI 346的一益處係，STI 346下之漂移區342的淨積分電荷會因為溝渠形成期間摻雜物的移除而減少。漂移區342的淨積分電荷(測量單位為原子/平方公分(atoms/cm2 ))係自STI 346之底部的氧化矽界面至漂移區342之底部的漂移區342的摻雜濃度積分，即為
變數α表示於STI 346形成後漂移區342中剩餘之經植入正常電荷的百分比，即未藉由蝕刻固持STI 346之溝渠而移除的摻雜物。經減少的電荷造成閘極355下方之表面電場的減少，且與閘極355的電場板效應結合，減少碰撞電離及熱載子損傷之風險。
在產製可靠及穩健之高電壓及功率LDMOS裝置中，控制崩潰的位置及碰撞電離的量值係一重要的考量因素。在LDMOS 300中包括主體區343有助於防止衝穿崩潰，及減少LDMOS 300由於限制出現在LDMOS 300中之寄生橫向NPN雙極電晶體之增益而對雙極注入及突返的靈敏度，其包括由源極區348A表示的射極，由主體區343及P型區341B表示的基極，及由漂移區342及汲極區348B表示的集極。然而，LDMOS 300的主體無法防止由於漂移區342中之局部化碰撞電離產生之背景摻雜濃度之調變所致的突返。
根據此發明，使用兩種方法來控制突返。首先，再度參考圖2，一深植入P型區365係佈置在源極區348A的下面，且係用以抑制閘極下之電場及將高電場位置移離高電流密度的區域。此處，此方法係稱作「次表面屏蔽(subsurface shielding)」，及深P型區365可稱作一次表面屏蔽區。第二種方法係，箝制LDMOS 300的最大汲極電壓在一低於突返之開始的電壓，以致不會發生突返現象。此處，此方法係稱作「汲極箝制(drain clamping)」，且可由汲極區348B下方之一DP區366的內含物實施。DP區366集中該汲極區348B下方之垂直電場，以迫使塊體，即非表面，突崩崩潰遠離熱載子敏感閘極介電層362。DP區366可稱作一汲極箝制區。
一橫向DMOS電晶體的一替代方案係準垂直DMOS電晶體。在一橫向DMOS中，電流橫向地流動，即，平行於晶圓表面，流過其輕摻雜漂移區。在該準垂直DMOS中，電流橫向地及垂直地流動，即大體上垂直於晶圓表面。電流從裝置之DMOS表面通道區向下流至一重摻雜的次表面層中，在此電流為橫向流動，及接著垂直地向上流回至汲極接點，因此命名為「準垂直」。
圖3顯示一N通道準垂直DMOS(QVDMOS)電晶體500的示意剖面圖。此裝置包括閘極510，其較佳形成為一連串之條狀或封閉幾合形狀；N+源極區506；P型主體區504；P+主體接觸區505。該等P型主體區係形成在N型井502的內部，該N型井502包括QVDMOS 500的漂移區且重疊在N型底板隔離區501的上面，其潛沒在P型基板511中且包括在QVDMOS 500的汲極中。
填充溝渠507橫向地封圍該QVDMOS 500，提供與產製在基板500中之其它裝置的隔離。填充溝渠507在一中心部分具有一導電材料508，其從基板500之表面向下延伸至底板隔離區501。該導電材料508係由一絕緣材料509橫向地圍繞，該絕緣材料509加襯在該溝渠507之側壁，使得導電材料508係與N井502及基板511電隔離。當該QVDMOS 500係於導通狀態時，電子電流從N+源極區506，橫向地流過形成在P型主體區504之表面的通道，垂直地向下流過N井502，橫向地流過底板隔離區501，及垂直地向上流過在填充溝渠507中的導電材料508。因此，輕易地達成該等源極區506及該汲極(底板隔離區501)與該基板511之表面的接觸。
P型主體區504可在閘極510形成之前植入，在此情況中，其等將不會與閘極510自對準。或者，P型主體區504可在閘極510形成之後使用一大傾斜角度植入，其使P型主體區504與閘極510之邊緣自對準。大傾斜角度植入允許P型主體區504與閘極510形成一相對較大之重疊，其不需要高溫擴散。
在QVDMOS的另一具體實施例中(未示出)，可在閘極505之每一邊緣形成側壁間隔物及N型輕摻雜源極區，如同使用相同閘極層之CMOS產製的一人工製品。若使用一專用閘極層形成閘極505，如圖3所示，則該等側壁間隔物將不會出現在該裝置中。在此一情況中，該等N+源極區將會與該閘極510自對準；否則，該等N+源極區會與該等側壁間隔物自對準及該等N-源極延伸部會與該閘極自對準。
上述之次表面屏蔽及汲極箝制的技術可與根據此發明製成之各種不同的汲極及汲極延伸結構結合。JFET及空乏模式MOSFET
不同於傳統的「常關型(normally-off)」裝置之增強模式MOSFET，JFET及空乏模式MOSFET傳導汲極電流，即使當其閘極被偏壓至其源極電位時，即，其等在VGS =0時傳導。因為該等電晶體通常為「導通」，此等裝置在當其它電晶體尚未可操作時對於形成用於起動電路的電流源而言為方便。
在一空乏模式N通道場效電晶體中，臨限電壓必須低於零伏特，使得即使處於一零伏特或大於閘極偏壓條件，該裝置仍處於其傳導狀態中。雖然一JFET的臨限電壓係稱為「夾止」電壓或Vpn ，一N通道JFET在一零伏特閘極驅動處亦可為「導通」。N通道空乏模式裝置及JFET僅可藉由加偏壓其閘極至一負電位而關閉。相反地，一正閘極偏壓增加一N通道裝置的汲極偏壓。然而，N通道JFET限制其最大閘極驅動在閘極至源極P-N二極體的正向偏壓電壓。P通道JFET亦會在一零伏特閘極驅動處傳導，但是一正閘極驅動，即被偏壓至比該源極更正電位之一電位的閘極，會要求關閉P通道JFET。
圖4顯示一隔離P通道JFET 100的示意剖面圖。P通道JFET 100包括P+汲極區107、P型通道區111、一包括N+區106及可選N型區108的N型頂部閘極、一包括N型底板隔離區102的底部閘極，及P+源極區105。該N型閘極的長度LG 較佳地1至20微米，且係由頂部閘極的長度界定，不論N+區106還是N型區108哪一者較長。
JFET 100藉由底板隔離區102垂直地及藉由填充溝渠104橫向地與P型基板101隔離。該底板隔離區102當作該JFET 100的底部閘極。藉由在該填充溝渠104之中心部分處的導電材料112提供與該基板101之表面的電接觸。絕緣材料113橫向地圍繞該導電材料112，以絕緣導電材料112與基板101及P型通道區111。底部閘極(底板隔離區102)在一電位「BG」處電偏壓，且此底部閘極偏壓BG可與頂部閘極(N+區及N型區108)之電位「TG」成比例變化，或BG可設定在一固定電位。
JFET 100的夾止電壓係由通道區111之摻雜濃度和NB區108與底板隔離區102之間之通道區111的垂直距離所決定。在一具體實施例中，通道區111之摻雜濃度係大體相同於基板101的摻雜濃度。在另一具體實施例中，藉由植入額外摻雜物而增加通道區111之摻雜濃度，以定製JFET 100的夾止電壓。
淺溝渠110可佈置在N型區108的周圍，以隔離N型區108與源極105及汲極107。在一較佳具體實施例中，因為溝渠110不應該接觸底板隔離區102，溝渠110比溝渠104更淺及更窄。溝渠107較佳係以一介電材料完全地填充。
圖5顯示一隔離N通道JFET 200的示意剖面圖。JFET 200包括N+汲極區203、N型通道區204、一包括P+區205及可選P型區206的P型頂部閘極、一包括隔離P型凹穴207及可選深植入P型區208的底部閘極，及P+源極區209。該底部閘極透過P型井210及P+底部閘極接觸區211予以電偏壓於一電位「BG」。該底部閘極偏壓BG可與頂部閘極之電位「TG」成比例變化，或BG可設定在一固定電位。JFET 200的夾止電壓係由N型通道區204之摻雜濃度及厚度所決定。
JFET 200藉由N型底板隔離區202垂直地及藉由填充溝渠214橫向地與P型基板201隔離。藉由在該填充溝渠214之中心部分處的導電材料212提供與該基板之表面的電接觸。絕緣材料213橫向地圍繞該導電材料212，以絕緣導電材料212與基板201及P型區210、208及207。
淺溝渠210可佈置在P型區206的周圍，以隔離頂部閘極206與源極區209及汲極區203。此外，淺溝渠215可用以橫向地隔離P+底部閘極接觸區211與通道區204、源極區209及汲極區203。在一較佳具體實施例中，因為溝渠210及215不應該接觸底板隔離區202，溝渠210及215比溝渠214更淺及更窄。溝渠210及215較佳係以一介電材料完全地填充。
在另一具體實施例中，可排除該底板隔離區202，使得該N通道JFET 200的底部閘極包括該P型基板201及/或該可選深P型區208。
圖6顯示一N通道空乏模式MOSFET 600的示意剖面圖。MOSFET 600的構造相似於圖1所示之該隔離N通道橫向DMOS電晶體400，但不具有可相比於出現在隔離凹穴664中之P型井465的一井。沒有隔離凹穴664中之P型井，MOSFET 600的臨限電壓係由閘極氧化層672之厚度及隔離P型凹穴664之摻雜濃度所設定，該隔離P型凹穴664之摻雜濃度大體上等於基板661之背景摻雜濃度。此臨限電壓可大約從-0.3V變化至+0.3V。即使該臨限電壓為輕微正電壓，該MOSFET 600仍將會在VGS =0處傳導足夠電流用以起動電路。
空乏模式N通道MOSFET中的突返效應相似於增強模式MOSFET中的突返效應。可以任何組合應用圖2所示之防止LDMOS 300之突返的結構至空乏模式裝置。
圖6之空乏模式MOSFET 600包括一N+汲極區668B，其具有一在閘極674與汲極668B之間的N型LDD漂移區669。閘極674座落於閘極介電層672之頂部上。LDD區678從汲極668B延伸至填充溝渠663。輕摻雜源極(LDS)區671，即CMOS程序的人工製品，係出現在側壁間隔物673A的下面。N+源極區668A與側壁間隔物673A自對準。
深P型區675係佈置在閘極674之至少一部分之下，且可橫向地延伸超出閘極674，以下層疊覆LDD漂移區669，進而減少碰撞電離及抑制突返。深P型區675透過P+主體接觸區667與基板661之表面電繫結。
閘極674下方之通道區676中之P型凹穴664之濃度大體上相同於P型基板661之濃度。在一較佳具體實施例中，DP區675之上方部分係足夠深以避免摻雜通道區676，使得可最小化MOSFET 600的臨限電壓。在其它具體實施例中，可調整深P型區675的摻雜及深度，以允許其摻雜分佈補充通道區676中的摻雜，以增加該臨限電壓至一所需值。
圖6之空乏模式MOSFET藉由N型底板隔離區602垂直地及藉由填充溝渠663橫向地與P型基板661隔離，該填充溝渠663橫向地封圍隔離凹穴664。藉由在該填充溝渠663之中心部分處的導電材料680提供該基板661之表面至底板隔離區662的電接觸。絕緣材料681橫向地圍繞該導電材料680，以絕緣導電材料與基板661及隔離凹穴664。
空乏模式MOSFET之其它具體實施例可製成相似於圖2之該LDMOS 300，但不具有P型主體區343，使得臨限電壓為低，且係藉由隔離凹穴341B及可能藉由深P型區365之上方部分的摻雜所設定。
隔離二極體
在許多電力應用中，需求一隔離高電壓整流二極體，例如，以在切換轉換器時的先斷後合(break-before-make)間隔期間再循環電感器電流。
圖7說明一隔離二極體700的一具體實施例，其包括一N型埋藏區702，當作二極體700之陰極；及一或多個P+接觸區707，其封圍在隔離P型區706中，當作二極體700之陽極。填充溝渠705橫向地圍繞該二極體700，提供與P型基板701的橫向隔離，而N型埋藏區702提供垂直隔離。藉由在該填充溝渠705之中心部分的導電材料712提供基板701之表面至N型埋藏區702的電接觸。絕緣材料713橫向地圍繞該導電材料712，以絕緣導電材料與基板701及P型區706。一介電層715係形成在基板701之表面上，且圖案化以形成陽極接點716及陰極接點717的開口。
可包括額外填充溝渠708以將該二極體分成較小的P型區，及提供一對於埋藏區702的較低電阻接觸。在一較佳具體實施例中，隔離P型區706可具有與P型基板701大體上相同的摻雜濃度。此在陰極-陽極接面處提供最低的可能摻雜，允許最高的崩潰電壓BV。或者，可引入一額外P型井植入物以增加P型區706的摻雜濃度，提供陽極區中的經降減電阻及供予自訂該BV至一較低值的能力。
在一具體實施例中，該P型井706具有一非單調摻雜分佈，包括至少一上方部分706A及一下方部分706B，其較佳係使用不同能量及劑量的一硼鏈植入物形成。在一具體實施例中，該下方部分706B具有一高於該上方部分706A的摻雜濃度。
在功率積體電路中，時常要求形成一齊納(Zener)電壓箝制，即意謂以反向偏壓正常操作且經常處於突崩崩潰模式中的一P-N二極體，以箝制一電路電壓至最大值。為了提供適當保護，齊納二極體必須時常展現良好控制崩潰電壓介於6V與20V之間，且此要求具有相對較高摻雜濃度之P-N接面的使用，以產生此等低BV。表面接面，如由重疊淺N+至P+區形成的一接面，不會造成可靠的齊納二極體箝制，因為其剖面面積太薄，且突崩崩潰發生在氧化矽界面附近。因此，較佳係使用埋藏P-N接面形成齊納二極體箝制，以達成次表面突崩崩潰。
圖8說明一隔離齊納二極體800，其包括重摻雜埋藏N型陰極區802及重摻雜P型陽極區803。P型陽極區803較佳係由一高劑量、高能量的植入物形成。由P+接觸區805及可選P井804提供基板801之表面至陽極區803的接觸。若未含有P井804，則此區域中的摻雜將會大體相同於基板801之摻雜。藉由在填充溝渠806之中心部分的導電材料812提供基板之表面至陰極區802的電接觸。絕緣材料813橫向地圍繞該導電材料812，以絕緣導電材料與基板801及P型區803及804。一介電層815係形成在基板801之表面上，且圖案化以形成陽極接點816及陰極接點817的開口。
可包括額外填充溝渠807以將該二極體800分成較小的陽極區803，及提供一對於陰極區802的較低電阻接觸。
在典型操作中，該陰極區802係偏壓在等於或高於接地基板801之電位的一電位。該陽極區803可相對於該陰極反向偏壓，直到由陽極-陰極接面之每一側上的摻雜設定的崩潰電壓。此BV可藉由高能量植入物的深度及劑量作調整，該等植入物較佳係用以形成該等埋藏陽極及陰極區。舉例說明，該等埋藏陽極區可藉由1E13至1E14cm-2 之範圍的劑量及2000至3000keV之能量的一磷植入物形成，及該陰極區可藉由1E13至1E14cm-2 之範圍的劑量及400至2000keV之範圍的能量的一硼植入物形成。
I型隔離裝置之高電壓終端
功率積體電路之另一所需特徵係允許隔離裝置「浮動」至高於基板電位之高電壓的能力。一浮動裝置或隔離凹穴的最大電壓不係取決於該隔離凹穴內部的內容物，而是取決於如何終止該凹穴，即圍住該溝渠隔離側壁之外部的邊界有何特色。
遍及此揭示內容說明的一種方法係，以填充溝渠終止隔離區及限制該底板隔離區至該等溝渠之外邊緣的橫向範圍。如先前所討論般，此等溝渠可全部地用介電材料填充，或該等溝渠可包括位於中心的導電材料及橫向地封圍該導電材料的介電材料。雖然此方法能夠支援高電壓，但其無法控制表面電場且可能遭受放電及其它時間相依表面相關現象。
另一方法係，以一或多個植入接面、電場釋放區及通道停止部圍繞或圍住該等側壁隔離溝渠之外部，其共同地包括一高電壓「終端」，如圖9A-9D所示之一連串剖面所說明。在每一圖解中，一P型凹穴係藉由一填充溝渠與外圍基板橫向地隔離，及藉由一植入底板隔離區與外圍基板垂直地隔離。雖然所示之該等填充溝渠在其中心處包括導電材料，但在其它具體實施例中可使用完全介電填充的溝渠。
圖9A-9D之剖面所示的隔離P型凹穴可包含CMOS、DMOS電晶體、JFET及空乏模式MOSFET、NPN及PNP雙極電晶體、齊納及整流二極體或更被動組件(如電阻器及電容器)之任何組合，其皆根據此發明構造及製成。每一圖包括一「CL」中心線標記，表示一旋轉軸，使得P型凹穴的所有側邊由一具有一環形或封閉幾何形狀的隔離溝渠封圍。
在每一範例中，所示的DN底板隔離區係延伸超出該溝渠達一距離LDN ，可從長度零至數十微米參數地改變一尺度。當LDN 係零時，該DN底板隔離區之橫向邊緣與該溝渠之外邊緣相重合。該DN底板隔離區係假設透過接觸一重疊N型井(例如，如圖1所示)或藉由該填充溝渠中的導電材料而予以電偏壓。該終端之外邊緣係由一P+護圈識別出，避免表面逆轉及當作一通道停止部。尺度涉及該溝渠的外邊緣及該P+護圈之內邊緣。該P+護圈可包括一在其之下的任選深P型DP層，以包含橫向的少數載子，及可包括一中介P型井，作為該護圈結構的部分。
圖9A顯示一邊緣終端結構，其包括N型底板隔離區902及填充溝渠904，及可包含的任何裝置，底板隔離區902及填充溝渠904一起隔離P型凹穴903與P型基板901。底板隔離區902延伸超出溝渠904達一距離LDN 。當底板隔離區902被偏壓至一比基板901更正電位的電位時，一空乏區散佈至基板901高於底板隔離區902之延伸部分的部分中，且此空乏區減少矽表面處的電場。底板隔離區902之邊緣和P+護圈905與下伏潛没P型區906之間的橫向距離係以尺度LSUB 標示，及範圍可從一微米至數十微米。
圖9B顯示一邊緣終端結構，其包括底板隔離區912及填充溝渠914，及可包含的任何裝置，底板隔離區912及填充溝渠914一起隔離P型凹穴913與P型基板911。底板隔離區912延伸超出溝渠914達一距離LDN 。藉由N+區918接觸長度LD3 的深植入N型漂移區917。漂移區917可被偏壓在與底板隔離區912相同的電位，或可被偏壓至一固定電位。漂移區917之外邊緣係與P+護圈915及下伏深P型區916隔開一間隔LSUB 。
漂移區917的作用係藉由展現二維空乏散佈效應抑制表面電場。提供該漂移區917具有足夠低的積分電荷QD ，一般而言範圍在1×1012 cm-2 至5×1012 cm-2 ，增加由漂移區917及P型基板911形成之P-N接面的施加電壓，會造成空乏散佈至漂移區917中及終究會造成漂移區917的完全空乏。在此條件下，漂移區917表現出相似於一P-I-N二極體中之本質材料的行為，及該表面電場根據二維電感應P-I-N接面之已知RESURF原則而大體下降。另外，底板隔離區912上之漂移區917的垂直重疊增強了介於該等區域917及912間之中介區域中的P型基板911的空乏，進一步減少該終端內的表面電場。
圖9C顯示一邊緣終端結構，其包括底板隔離區922及填充溝渠924，及可包含的任何裝置，底板隔離區922及填充溝渠924一起隔離P型凹穴923與P型基板921。底板隔離區922延伸超出溝渠924達一距離LDN ，且與溝渠927間隔開一距離LSUB 。在此具體實施例中，底板隔離區922與溝渠927之間的間隙，即尺度LSUB 的間隙，控制介於溝渠924與927之間的表面區域(即標誌為928之區域)中的P型基板921的電位。當底板隔離區922與溝渠927之間的該間隙變成完全空乏時，P型區928之電位開始浮動。切斷該基板電位，該表面電場下降。一P+護圈925外接該裝置且可包括下伏深P型區926。
圖9D顯示一邊緣終端結構，其包括底板隔離區932及填充溝渠934，及可包含的任何裝置，底板隔離區932及填充溝渠934一起隔離P型凹穴933與P型基板931。底板隔離區932延伸超出溝渠934。藉由N+區938接觸深植入N型漂移區937。漂移區937可被偏壓在與底板隔離區932相同的電位，或可被偏壓至一固定電位。在漂移區937中，形成一或多個填充溝渠939。每一溝渠939減少漂移區937中的局部摻雜濃度，其允許漂移區937之鄰接部分更容易被空乏，進一步降低局部電場。在一較佳具體實施例中，溝渠939比溝渠934更窄及更淺，且以介電材料完全地填充。在一具體實施例中，該裝置係設計成使得溝渠939之表面積與漂移區937之表面積的比例隨著溝渠934之橫向距離增加而增加。此允許空乏漂移區937最遠離隔離凹穴933之部分要比空乏較接近凹穴933之部分要容易得多，因此提供一相似於一漸變接面終端的效果，其有效地最小化支援一給定BV所需之橫向距離。漂移區937之外邊緣係與P+護圈935及下伏深P型區936隔開一間隔LSUB 。
此處描述的該等具體實施例意欲用於說明而非限制。從此處的描述說明中，熟知本技術者人士應明白此發明之廣大範疇內的許多替代性具體實施例。
100．．．隔離P通道JFET
101．．．P型基板
102．．．N型底板隔離區
104．．．填充溝渠
105．．．P+源極區
106．．．N+區
107．．．P+汲極區
108．．．N型區
110．．．淺溝渠
111．．．P型通道區
112．．．導電材料
113．．．絕緣材料
200．．．隔離N通道JFET
201．．．P型基板
202．．．N型底板隔離區
203．．．N+汲極區
204．．．N型通道區
205．．．P+區
206．．．可選P型區
207．．．隔離P型凹穴
208．．．可選深植入P型區
209．．．P+源極區
210．．．P型井/溝渠
211．．．P+底部閘極接觸區
212．．．導電材料
213．．．絕緣材料
214．．．填充溝渠
215．．．淺溝渠
300．．．隔離N通道橫向DMOS
341A．．．P型基板
341B．．．P型區/隔離凹穴
342．．．N型漂移區
343．．．P型井/主體區
343A．．．P型井343之上方部分
343B．．．P型井343之下方部分
346．．．STI
347．．．P+主體接觸區
348A．．．N+源極區
348B．．．中心N+汲極區
355．．．閘極
360．．．深植入N型底板隔離區
361．．．填充溝渠
362．．．閘極介電層
363．．．導電中心部分
364．．．絕緣側壁
365．．．深植入P型區
366．．．DP區
400．．．橫向擴散金屬氧化物半導體(LDMOS)
461．．．P型基板
462．．．N型底板隔離區
463A．．．介電填充溝渠
463B．．．介電填充溝渠
463C．．．溝渠
464．．．P型區
465．．．P型井
465A．．．P型井465之上方部分
465B．．．P型井465之下方部分
466．．．N型井
467．．．P+主體接觸區
468A．．．N+源極區
468B．．．N+汲極區
468D．．．N+接觸區
469．．．N型輕量摻雜汲極(LDD)區
471．．．輕量摻雜源極延伸部
472．．．閘極氧化層
473．．．側壁間隔物
474．．．P+基板接觸區/閘極
475．．．深植入P型區
476．．．LDD區
478．．．N型終端區
500．．．N通道準垂直DMOS(QVDMOS)電晶體
501．．．N型底板隔離區
502．．．N型井
504．．．P型主體區
505．．．P+主體接觸區
506．．．N+源極區
507．．．填充溝渠
508．．．導電材料
509．．．絕緣材料
510．．．閘極
511．．．P型基板
600．．．N通道空乏模式MOSFET
661．．．P型基板
662．．．N型底板隔離區
663．．．填充溝渠
664．．．隔離凹穴
667．．．P+主體接觸區
668A．．．N+源極區
668B．．．N+汲極區
669．．．N型LDD漂移區
671．．．輕摻雜源極(LDS)區
672．．．閘極介電層
673A．．．側壁間隔物
674．．．閘極
675．．．深P型區
676．．．通道區
678．．．LDD區
680．．．導電材料
681．．．絕緣材料
700．．．隔離二極體
701．．．P型基板
702．．．N型埋藏區
705．．．填充溝渠
706．．．隔離P型區
706A．．．P型井之上方部分
706B．．．P型井之下方部分
707．．．P+接觸區
708．．．額外填充溝渠
712．．．導電材料
713．．．絕緣材料
715．．．介電層
716．．．陽極接點
717．．．陰極接點
800．．．隔離齊納二極體
801．．．基板
802．．．重摻雜埋藏N型陰極區
803．．．重摻雜P型陽極區
804．．．可選P井
805．．．P+接觸區
806．．．填充溝渠
807．．．額外填充溝渠
812．．．導電材料
813．．．絕緣材料
815．．．介電層
816．．．陽極接點
817．．．陰極接點
901．．．P型基板
902．．．N型底板隔離區
903．．．P型凹穴
904．．．填充溝渠
905．．．P+護圈905
906．．．下伏潛没P型區
911．．．P型基板
912．．．底板隔離區
913．．．P型凹穴
914．．．填充溝渠
915．．．P+護圈
916．．．下伏深P型區
917．．．深植入N型漂移區
918．．．N+區
921．．．P型基板
922．．．底板隔離區
923．．．P型凹穴
924．．．填充溝渠
925．．．P+護圈
926．．．下伏深P型區
927．．．溝渠
928．．．P型區
931．．．P型基板
932．．．底板隔離區
933．．．P型凹穴
934．．．填充溝渠
935．．．P+護圈
936．．．下伏深P型區
937．．．深植入N型漂移區
938．．．N+區
939．．．填充溝渠
圖1說明一完全隔離N通道橫向DMOS(LDMOS)的剖面圖。
圖2說明一隔離N通道橫向LDMOS之一替代性具體實施例的剖面圖。
圖3說明一隔離N通道準垂直DMOS的剖面圖。
圖4說明一隔離P通道JFET的剖面圖。
圖5說明一隔離N通道JFET的剖面圖。
圖6說明一N通道空乏模式MOSFET的剖面圖。
圖7說明一隔離二極體的剖面圖。
圖8說明一隔離齊納二極體的剖面圖。
圖9A-9D說明用於控制表面電場及減少放電及其它時間相依表面相關現象之終端結構的剖面圖。
400．．．橫向擴散金屬氧化物半導體(LDMOS)
461．．．P型基板
462．．．N型底板隔離區
463A．．．介電填充溝渠
463B．．．介電填充溝渠
463C．．．溝渠
464．．．P型區
465．．．P型井
465A．．．P型井465之上方部分
465B．．．P型井465之下方部分
466．．．N型井
467．．．P+主體接觸區
468A．．．N+源極區
468B．．．N+汲極區
468D．．．N+接觸區
469．．．N型輕量摻雜汲極(LDD)區
471．．．輕量摻雜源極延伸部
472．．．閘極氧化層
473．．．側壁間隔物
474．．．P+基板接觸區/閘極
475．．．深植入P型區
476．．．LDD區
478．．．N型終端區

Claims (47)

  1. 一種隔離電晶體，其形成在一第一導電率類型之一半導體基板中，該基板不包括一磊晶層，該隔離電晶體包括：與該第一導電率類型相反之一第二導電率類型之一底板隔離區，其潛沒在該基板中；一第一溝渠，其從該基板之一表面至少延伸至該底板隔離區，該溝渠包括一介電材料，該溝渠及該底板隔離區一起形成該基板之一隔離凹穴；該第二導電率類型之一源極區，其位在該隔離凹穴中之該基板的該表面處；該第二導電率類型之一汲極區，其位在該隔離凹穴中之該基板的該表面處且與該源極區間隔開；一閘極，其位在該基板之該表面上，介於該源極區與該汲極區之間；一通道區，其鄰接在該閘極之下之該基板之該表面；以及該第二導電率類型之一漂移區，其位在該隔離凹穴中介於該汲極區與該通道區之間。
  2. 如請求項1之隔離電晶體，其包括一第二溝渠，其從該基板之該表面至少延伸至該底板隔離區，該第二溝渠係填充有一介電材料且將該隔離凹穴分成一第一區段及一第二區段，該源極區、該汲極區、該漂移區及井係位在該第一區段中，該第二區段包括該第二導電率類型之一第二井，其從該基板之該表面延伸至該底板隔離區。
  3. 如請求項1之隔離電晶體，其中該第一溝渠包括一導電中心部分，該導電中心部分係藉由該介電材料而與該基板及該隔離凹穴相隔離。
  4. 如請求項1之隔離電晶體，其中該隔離凹穴的一摻雜濃度大體上相同於該基板的一摻雜濃度。
  5. 如請求項4之隔離電晶體，其中該隔離電晶體具有一範圍在-0.3至+0.3伏特的臨限電壓。
  6. 如請求項1之隔離電晶體，其包括該隔離凹穴中之該第一導電率類型之一井，該井包括該通道區。
  7. 如請求項6之隔離電晶體，其中該井包括一淺部分及一深部分，該深部分的位置係低於該淺部分，該深部分之一摻雜濃度係大於該淺部分之一摻雜濃度。
  8. 如請求項1之隔離電晶體，其包括該第一導電率類型之一次表面屏蔽區，其佈置在該源極區的下方且具有一大於該隔離凹穴之一摻雜濃度之摻雜濃度。
  9. 如請求項1之隔離電晶體，其包括該第一導電率類型之一汲極箝制區，其佈置在該汲極區的下方且具有一大於該隔離凹穴之一摻雜濃度之摻雜濃度。
  10. 如請求項1之隔離電晶體，其包括一第二溝渠，其佈置在該漂移區之至少一部分之上的該基板之該表面。
  11. 如請求項10之隔離電晶體，其中該第二溝渠包括該介電材料，且具有一低於該第一溝渠的一深度之深度。
  12. 一種隔離橫向擴散金屬氧化物半導體(DMOS)電晶體，其形成在一第一導電率類型之一半導體基板中，該基板不包括一磊晶層，該隔離DMOS電晶體包括：與該第一導電率類型相反之一第二導電率類型之一底板隔離區，其潛沒在該基板中；一溝渠，其從該基板之一表面至少延伸至該底板隔離區，該溝渠包括一中心導電部分及一介電材料，該溝渠及該底板隔離區一起形成該基板之一隔離凹穴，該介電材料隔離該導電部分與該隔離凹穴及該基板；該第二導電率類型之一源極區，其位在該隔離凹穴中之該基板的該表面處；該第二導電率類型之一汲極區，其位在該隔離凹穴中之該基板的該表面處且與該源極區間隔開；一閘極，其位在一閘極介電層之頂部上，其係在該基板之該表面介於該源極區與該汲極區之間的一區域之上；該第二導電率類型之一漂移區，其鄰接該隔離凹穴中之該基板的該表面及該汲極區，該漂移區具有一低於該汲極區之摻雜濃度；以及一淺溝渠隔離(STI)結構，其鄰接該隔離凹穴中之該基板的該表面，該STI結構之側邊及底部係由該漂移區封圍。
  13. 如請求項12之隔離橫向DMOS電晶體，其中該汲極區係由該閘極及該源極區橫向地圍繞。
  14. 如請求項13之隔離橫向DMOS電晶體，其包括該隔離凹穴中之該第一導電率類型之一井，該井延伸在該閘極之下。
  15. 如請求項14之隔離橫向DMOS電晶體，其中該井係與該漂移區間隔開。
  16. 如請求項14之隔離橫向DMOS電晶體，其中該井毗連該漂移區。
  17. 如請求項12之隔離橫向DMOS電晶體，其包括該第一導電率類型之一次表面屏蔽區，其潛没在該源極區下方之該隔離凹穴中，突返控制區具有一大於該隔離凹穴之一摻雜濃度之摻雜濃度。
  18. 如請求項12之隔離橫向DMOS電晶體，其包括該第一導電率類型之一汲極箝制區，其潛没在該汲極區下方之該隔離凹穴中，第二突返控制區具有一大於該隔離凹穴之一摻雜濃度之摻雜濃度。
  19. 一種隔離橫向空乏模式電晶體，其形成在一第一導電率類型之一半導體基板中，該基板不包括一磊晶層，該隔離空乏模式電晶體包括：與該第一導電率類型相反之一第二導電率類型之一底板隔離區，其潛沒在該基板中；一溝渠，其從該基板之一表面至少延伸至該底板隔離區，該溝渠包括一介電材料，該溝渠及該底板隔離區一起形成該基板之一隔離凹穴；該第二導電率類型之一源極區，其位在該隔離凹穴中之該基板的該表面處；該第二導電率類型之一汲極區，其位在該隔離凹穴中之該基板的該表面處且與該源極區間隔開；一閘極，其位在一閘極介電層之頂部上，其係在該基板之該表面介於該源極區與該汲極區之間的一區域之上；以及該第一導電率類型之一通道區，其鄰接該閘極之下之該基板的該表面；其中該基板具有一背景摻雜濃度，該背景摻雜濃度與該通道區之一摻雜濃度係大體上相等。
  20. 如請求項19之隔離橫向空乏模式電晶體，其包括在該隔離凹穴中之該第一導電率類型之一潛没區，該潛没區具有一大於該基板之該背景摻雜濃度之摻雜濃度，該潛沒區之至少一部分係位在該閘極之下。
  21. 如請求項20之隔離橫向空乏模式電晶體，其包括該第一導電率類型之一接觸區，其從該基板之該表面延伸至該潛没區，該接觸區具有一大於該基板之該背景摻雜濃度之摻雜濃度。
  22. 如請求項19之隔離橫向空乏模式電晶體，其中該溝渠具有填充有一導電材料之一中心部分，及在該溝渠之各壁加襯有介電材料。
  23. 一種隔離準垂直DMOS(QVDMOS)電晶體，其形成在一第一導電率類型之一半導體基板中，該基板不包括一磊晶層，該隔離QVDMOS電晶體包括：與該第一導電率類型相反之一第二導電率類型之一底板隔離區，其潛沒在該基板中；一溝渠，其從該基板之一表面至少延伸至該底板隔離區，該溝渠具有一中心導電部分及一加襯在該溝渠之各壁的介電材料，該溝渠及該底板隔離區一起形成該基板之一隔離凹穴；該第二導電率類型之一源極區，其位在該隔離凹穴中之該基板的該表面處；一閘極，其位在一閘極介電層之頂部上，其係在該基板之該表面鄰接該源極區的一區域之上；在該隔離凹穴中之該第一導電率類型之一主體區，該主體區延伸在該閘極之下；以及在該隔離凹穴中之該第二導電率類型之一漂移區，其延伸介於該底板隔離區與該主體區之間。
  24. 如請求項23之隔離QVDMOS電晶體，其中該QVDMOS電晶體之一汲極包括該底板隔離區。
  25. 如請求項23之隔離QVDMOS電晶體，其中該中心導電部分提供自該底板隔離區至該基板之該表面的接觸。
  26. 一種隔離接面場效電晶體(JFET)，其形成在一第一導電率類型之一半導體基板中，該基板不包括一磊晶層，該隔離JFET包括：與該第一導電率類型相反之一第二導電率類型之一底板隔離區，其潛沒在該基板中；一溝渠，其從該基板之一表面至少延伸至該底板隔離區，該溝渠包括一介電材料，該溝渠及該底板隔離區一起形成該基板之一隔離凹穴；一源極區，其位在該隔離凹穴中之該基板的該表面處；一汲極區，其位在該隔離凹穴中之該基板的該表面處且與該源極區間隔開；一頂部閘極區，其位在該基板之該表面介於該源極區與該汲極區之間；以及一通道區，其延伸介於該源極區與該汲極區之間，且位在該頂部閘極區之下及該底板隔離區之上。
  27. 如請求項26之隔離JFET，其包括一第一介電填充溝渠，其介於該源極區與該頂部閘極區之間；及一第二介電填充溝渠，其介於該汲極區與該頂部閘極區之間。
  28. 如請求項26之隔離JFET，其中該溝渠具有填充有一導電材料的一中心部分及加襯在該溝渠之各壁的一介電材料。
  29. 如請求項26之隔離JFET，其中該源極區、該汲極區及該通道區係該第一導電率類型，及該頂部閘極係該第二導電率類型。
  30. 如請求項26之隔離JFET，其中該源極區、該汲極區及該通道區係該第二導電率類型，及該頂部閘極係該第一導電率類型。
  31. 一種隔離接面場效電晶體(JFET)，其形成在一第一導電率類型之一半導體基板中，該基板不包括一磊晶層，該隔離JFET包括：與該第一導電率類型相反之一第二導電率類型之一底板隔離區，其潛沒在該基板中；一溝渠，其從該基板之一表面至少延伸至該底板隔離區，該溝渠包括一介電材料，該溝渠及該底板隔離區一起形成該基板之一隔離凹穴；該第二導電率類型之一源極區，其位在該隔離凹穴中之該基板的該表面處；該第二導電率類型之一汲極區，其位在該隔離凹穴中之該基板的該表面處且與該源極區間隔開；該第一導電率類型之一頂部閘極區，其佈置在該隔離凹穴中介於該源極區與該汲極區之間；該第一導電率類型之一底部閘極區，其潛没在該頂部閘極區之下的該隔離凹穴中；以及該第二導電率類型之一通道區，其延伸介於該源極區與該汲極區之間，該通道區位在該頂部閘極區之下及該底部閘極區之上。
  32. 如請求項31之隔離JFET，其包括：一第一介電填充溝渠，其介於該源極區與該頂部閘極區之間；及一第二介電填充溝渠，其介於該汲極區與該頂部閘極區之間。
  33. 如請求項31之隔離JFET，其包括在該隔離凹穴中之該第一導電率類型之一井，其從該基板之該表面延伸至該底部閘極區。
  34. 如請求項33之隔離JFET，其中該井包括一底部閘極接觸區，該底部閘極接觸區鄰接該基板之該表面，該底部閘極接觸區具有一大於該井之一剩餘部分的一摻雜濃度之摻雜濃度，及其中該隔離接面場效電晶體(JFET)包括一第三介電填充溝渠，該第三介電填充溝渠鄰接該基板之該表面及該底部閘極接觸區。
  35. 如請求項31之隔離JFET，其中該溝渠具有填充有一導電材料之一中心部分及加襯在該溝渠之各壁的一介電材料。
  36. 一種隔離接面場效電晶體(JFET)，其形成在一第一導電率類型之一半導體基板中，該基板不包括一磊晶層，該隔離JFET包括：與該第一導電率類型相反之一第二導電率類型之一底板隔離區，其潛沒在該基板中；一溝渠，其從該基板之一表面至少延伸至該底板隔離區，該溝渠包括一介電材料，該溝渠及該底板隔離區一起形成該基板之一隔離凹穴；該第一導電率類型之一源極區，其位在該隔離凹穴中之該基板的該表面處；該第一導電率類型之一汲極區，其位在該隔離凹穴中之該基板的該表面處且與該源極區間隔開；該第二導電率類型之一頂部閘極區，其佈置在該隔離凹穴中之該基板的該表面處介於該源極區與該等汲極區之間；以及該第一導電率類型之一通道區，其延伸介於該源極區與該汲極區之間，該通道區位在該頂部閘極區之下及該底板隔離區之上。
  37. 如請求項36之隔離JFET，其包括：一第一介電填充溝渠，該第一介電填充溝渠係介於該源極區與該頂部閘極區之間並與其鄰接；及一第二介電填充溝渠，該第二介電填充溝渠係介於該汲極區與該頂部閘極區之間並與其鄰接。
  38. 如請求項36之隔離JFET，其中該溝渠具有填充有一導電材料之一中心部分及加襯在該溝渠之各壁的一介電材料，該導電材料提供自該底板隔離區至該基板之該表面的接觸。
  39. 如請求項36之隔離JFET，其中該底板隔離區包括該JFET的一底部閘極。
  40. 一種隔離二極體，其形成在一第一導電率類型之一半導體基板中，該基板不包括一磊晶層，該隔離二極體包括：與該第一導電率類型相反之一第二導電率類型之一底板隔離區，其潛沒在該基板中；一溝渠，其從該基板之一表面至少延伸至該底板隔離區，該溝渠具有填充有一導電材料之一中心部分及加襯在該溝渠之各壁的一介電材料，該導電材料提供自該底板隔離區至該基板之該表面的電接觸，該溝渠及該底板隔離區一起形成該基板之一隔離凹穴；以及在該隔離凹穴中之該第一導電率類型之一陽極區，該陽極區從該基板之該表面延伸至該底板隔離區。
  41. 如請求項40之隔離二極體，其包括：一介電層，其在該基板之該表面之上，該介電層具有一第一開口在該陽極區之上及一第二開口在該導電材料之上；一陽極接點，其在該第一開口中，與該陽極區接觸；以及一陰極接點，其在該第二開口中，與該導電材料接觸。
  42. 如請求項40之隔離二極體，其中該陽極區包括一淺部分及一深部分，該淺部分係位於鄰接該基板之該表面，該深部分係位於該淺部分之下，該淺部分具有一第一摻雜濃度，該深部分具有一第二摻雜濃度，該第二摻雜濃度係大於該第一摻雜濃度。
  43. 一種隔離結構，其形成在一第一導電率類型之一半導體基板中，該基板不包括一磊晶層，該隔離結構包括：與該第一導電率類型相反之一第二導電率類型之一底板隔離區，其潛沒在該基板中；一溝渠，其從該基板之一表面至少延伸至該底板隔離區，該溝渠包括一介電材料，該溝渠及該底板隔離區一起形成該基板之一隔離凹穴；該第一導電率類型之一護圈，其位在該隔離凹穴外之該基板的該表面處，該護圈具有一大於該基板之一摻雜濃度之摻雜濃度；其中該底板隔離區在朝向該護圈的一方向中延伸超出該溝渠之一外部邊緣達一預定距離。
  44. 如請求項43之隔離結構，其包括該護圈下方之該第一導電率類型之一潛没區，該潛没區具有一大於該基板之該摻雜濃度之摻雜濃度。
  45. 如請求項43之隔離結構，其包括該第二導電率類型之一漂移區，其鄰接該基板之該表面及該隔離凹穴外的溝渠，該漂移區係與該護圈間隔開。
  46. 如請求項45之隔離結構，其包括至少一第二溝渠，該第二溝渠包括一介電材料且從該基板之該表面延伸入該漂移區中，該第二溝渠之一底板係位在該漂移區中。
  47. 如請求項43之隔離結構，其包括從該基板之該表面延伸的一第二溝渠，該第二溝渠係位在該第一溝渠與該護圈之間，且與該底板隔離區之一橫向邊緣間隔開。
TW098106510A 2008-02-27 2009-02-27 半導體晶粒之隔離電晶體、隔離二極體及隔離與終端結構 TWI415262B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/072,615 US7667268B2 (en) 2002-08-14 2008-02-27 Isolated transistor

Publications (2)

Publication Number Publication Date
TW200945589A TW200945589A (en) 2009-11-01
TWI415262B true TWI415262B (zh) 2013-11-11

Family

ID=41016649

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098106510A TWI415262B (zh) 2008-02-27 2009-02-27 半導體晶粒之隔離電晶體、隔離二極體及隔離與終端結構

Country Status (8)

Country Link
US (3) US7667268B2 (zh)
EP (1) EP2248162A4 (zh)
JP (1) JP5449203B2 (zh)
KR (4) KR101456408B1 (zh)
CN (2) CN102867843B (zh)
HK (1) HK1176462A1 (zh)
TW (1) TWI415262B (zh)
WO (1) WO2009108311A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI578537B (zh) * 2014-08-01 2017-04-11 旺宏電子股份有限公司 高壓半導體元件
US10121889B2 (en) 2014-08-29 2018-11-06 Macronix International Co., Ltd. High voltage semiconductor device

Families Citing this family (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080197408A1 (en) * 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
US7956391B2 (en) 2002-08-14 2011-06-07 Advanced Analogic Technologies, Inc. Isolated junction field-effect transistor
US8089129B2 (en) * 2002-08-14 2012-01-03 Advanced Analogic Technologies, Inc. Isolated CMOS transistors
US7812403B2 (en) * 2002-08-14 2010-10-12 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuit devices
US7902630B2 (en) * 2002-08-14 2011-03-08 Advanced Analogic Technologies, Inc. Isolated bipolar transistor
US8513087B2 (en) * 2002-08-14 2013-08-20 Advanced Analogic Technologies, Incorporated Processes for forming isolation structures for integrated circuit devices
US7834421B2 (en) * 2002-08-14 2010-11-16 Advanced Analogic Technologies, Inc. Isolated diode
US7825488B2 (en) * 2006-05-31 2010-11-02 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuits and modular methods of forming the same
US7939420B2 (en) * 2002-08-14 2011-05-10 Advanced Analogic Technologies, Inc. Processes for forming isolation structures for integrated circuit devices
US7667268B2 (en) * 2002-08-14 2010-02-23 Advanced Analogic Technologies, Inc. Isolated transistor
KR100867977B1 (ko) 2006-10-11 2008-11-10 한국과학기술원 인도시아닌 그린 혈중 농도 역학을 이용한 조직 관류 분석장치 및 그를 이용한 조직 관류 분석방법
US7737526B2 (en) * 2007-03-28 2010-06-15 Advanced Analogic Technologies, Inc. Isolated trench MOSFET in epi-less semiconductor sustrate
US7795681B2 (en) * 2007-03-28 2010-09-14 Advanced Analogic Technologies, Inc. Isolated lateral MOSFET in epi-less substrate
KR101035596B1 (ko) * 2007-12-28 2011-05-19 매그나칩 반도체 유한회사 딥 트렌치 구조를 갖는 반도체 소자
US8298889B2 (en) * 2008-12-10 2012-10-30 Semiconductor Components Industries, Llc Process of forming an electronic device including a trench and a conductive structure therein
JP5537814B2 (ja) * 2009-01-06 2014-07-02 ラピスセミコンダクタ株式会社 半導体装置、及びその製造方法
US7943445B2 (en) * 2009-02-19 2011-05-17 International Business Machines Corporation Asymmetric junction field effect transistor
CN101521203B (zh) * 2009-04-07 2010-08-04 电子科技大学 一种半导体横向器件和高压器件
TWI405332B (zh) 2010-03-10 2013-08-11 Macronix Int Co Ltd 接面場效應電晶體元件
US9293577B2 (en) * 2010-03-30 2016-03-22 Volterra Semiconductor LLC LDMOS with no reverse recovery
CN102270580A (zh) * 2010-06-04 2011-12-07 和舰科技(苏州)有限公司 一种制造高压nmos管的方法
WO2011155105A1 (ja) * 2010-06-07 2011-12-15 パナソニック株式会社 半導体装置及びその製造方法
US8462477B2 (en) * 2010-09-13 2013-06-11 Analog Devices, Inc. Junction field effect transistor for voltage protection
JP5581977B2 (ja) * 2010-11-03 2014-09-03 株式会社デンソー 半導体装置の製造方法
US8629026B2 (en) 2010-11-12 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Source tip optimization for high voltage transistor devices
JP5504187B2 (ja) * 2011-01-26 2014-05-28 株式会社東芝 半導体装置及びその製造方法
US8618583B2 (en) * 2011-05-16 2013-12-31 International Business Machines Corporation Junction gate field effect transistor structure having n-channel
JP5743831B2 (ja) * 2011-09-29 2015-07-01 株式会社東芝 半導体装置
US8518764B2 (en) * 2011-10-24 2013-08-27 Freescale Semiconductor, Inc. Semiconductor structure having a through substrate via (TSV) and method for forming
JP5739826B2 (ja) * 2012-01-23 2015-06-24 株式会社東芝 半導体装置
JP5964091B2 (ja) * 2012-03-12 2016-08-03 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6001309B2 (ja) * 2012-04-17 2016-10-05 エスアイアイ・セミコンダクタ株式会社 半導体装置
US9236472B2 (en) * 2012-04-17 2016-01-12 Freescale Semiconductor, Inc. Semiconductor device with integrated breakdown protection
US8853780B2 (en) 2012-05-07 2014-10-07 Freescale Semiconductor, Inc. Semiconductor device with drain-end drift diminution
US9093517B2 (en) 2012-05-25 2015-07-28 Microsemi SoC Corporation TID hardened and single event transient single event latchup resistant MOS transistors and fabrication process
US20130313650A1 (en) * 2012-05-25 2013-11-28 Microsemi Soc Corp. Tid hardened mos transistors and fabrication process
US9231083B2 (en) * 2012-06-29 2016-01-05 Freescal Semiconductor Inc. High breakdown voltage LDMOS device
US8921934B2 (en) * 2012-07-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with trench field plate
JP6132539B2 (ja) * 2012-12-13 2017-05-24 ルネサスエレクトロニクス株式会社 半導体装置
US8890250B2 (en) * 2012-12-28 2014-11-18 United Microelectronics Corporation Electrostatic discharge protection structure
US9378958B2 (en) * 2012-12-28 2016-06-28 United Microelectronics Corporation Electrostatic discharge protection structure and fabricating method thereof
CN103050541B (zh) * 2013-01-06 2015-08-19 上海华虹宏力半导体制造有限公司 一种射频ldmos器件及其制造方法
US9490322B2 (en) 2013-01-23 2016-11-08 Freescale Semiconductor, Inc. Semiconductor device with enhanced 3D resurf
JP2014170831A (ja) 2013-03-04 2014-09-18 Seiko Epson Corp 回路装置及び電子機器
JP2014203851A (ja) * 2013-04-01 2014-10-27 株式会社東芝 半導体装置及びその製造方法
CN104241354B (zh) * 2013-06-09 2018-03-06 中芯国际集成电路制造(上海)有限公司 Ldmos晶体管及其形成方法
JP6295444B2 (ja) * 2013-07-16 2018-03-20 パナソニックＩｐマネジメント株式会社 半導体装置
US9076863B2 (en) 2013-07-17 2015-07-07 Texas Instruments Incorporated Semiconductor structure with a doped region between two deep trench isolation structures
US9059278B2 (en) * 2013-08-06 2015-06-16 International Business Machines Corporation High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region
CN104425344B (zh) * 2013-08-28 2017-06-13 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US9006825B1 (en) * 2013-09-27 2015-04-14 Mediatek Inc. MOS device with isolated drain and method for fabricating the same
US9177952B2 (en) * 2013-10-15 2015-11-03 Freescale Semiconductor, Inc. ESD protection with asymmetrical bipolar-based device
CN104638003B (zh) * 2013-11-14 2019-04-09 上海华虹宏力半导体制造有限公司 射频ldmos器件及工艺方法
WO2015077361A1 (en) 2013-11-21 2015-05-28 Microsemi SoC Corporation High voltage device fabricated using low-voltage processes
CN104701365B (zh) * 2013-12-05 2018-02-16 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US9543379B2 (en) 2014-03-18 2017-01-10 Nxp Usa, Inc. Semiconductor device with peripheral breakdown protection
JP2016001671A (ja) * 2014-06-12 2016-01-07 サンケン電気株式会社 半導体装置
US9425304B2 (en) * 2014-08-21 2016-08-23 Vishay-Siliconix Transistor structure with improved unclamped inductive switching immunity
JP6355481B2 (ja) * 2014-08-25 2018-07-11 ルネサスエレクトロニクス株式会社 半導体装置
KR102143520B1 (ko) * 2014-09-17 2020-08-11 삼성전자 주식회사 펌핑 캐패시터
CN105720098B (zh) * 2014-12-02 2019-01-29 中芯国际集成电路制造(上海)有限公司 Nldmos及其制作方法
CN105810583B (zh) * 2014-12-30 2019-03-15 无锡华润上华科技有限公司 横向绝缘栅双极型晶体管的制造方法
KR102354463B1 (ko) 2015-01-09 2022-01-24 삼성전자주식회사 레트로그레이드 채널을 갖는 반도체 소자 및 그 제조방법
US9806148B2 (en) 2015-04-07 2017-10-31 Texas Instruments Incorporated Device isolator with reduced parasitic capacitance
CN106298768B (zh) * 2015-06-10 2019-03-19 联华电子股份有限公司 半导体元件及半导体元件的操作方法
KR101692625B1 (ko) * 2015-06-18 2017-01-03 주식회사 동부하이텍 고비저항 기판 상에 형성된 반도체 소자 및 무선 주파수 모듈
KR101666753B1 (ko) * 2015-06-18 2016-10-14 주식회사 동부하이텍 고비저항 기판 상에 형성된 반도체 소자 및 무선 주파수 모듈
JP2017045884A (ja) * 2015-08-27 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US10217860B2 (en) * 2015-09-11 2019-02-26 Nxp Usa, Inc. Partially biased isolation in semiconductor devices
US9722097B2 (en) 2015-09-16 2017-08-01 Vanguard International Semiconductor Corporation Semiconductor device and method for manufacturing the same
US10446695B2 (en) * 2015-10-21 2019-10-15 United Silicone Carbide, Inc. Planar multi-implanted JFET
TWI594334B (zh) * 2015-11-12 2017-08-01 世界先進積體電路股份有限公司 半導體裝置及其製造方法
CN107026082B (zh) * 2016-02-02 2019-11-19 璟茂科技股份有限公司 功率整流二极管的制法
JP6591312B2 (ja) 2016-02-25 2019-10-16 ルネサスエレクトロニクス株式会社 半導体装置
US9871135B2 (en) 2016-06-02 2018-01-16 Nxp Usa, Inc. Semiconductor device and method of making
TWI693713B (zh) * 2016-07-22 2020-05-11 立積電子股份有限公司 半導體結構
CN107785366B (zh) 2016-08-31 2020-04-14 无锡华润上华科技有限公司 集成有结型场效应晶体管的器件及其制造方法
US10032766B2 (en) * 2016-09-16 2018-07-24 Globalfoundries Singapore Pte. Ltd. VDMOS transistors, BCD devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices
US10347621B2 (en) * 2016-10-12 2019-07-09 Texas Instruments Incorporated Electrostatic discharge guard ring with snapback protection
US9905687B1 (en) 2017-02-17 2018-02-27 Nxp Usa, Inc. Semiconductor device and method of making
JP6416969B2 (ja) * 2017-04-13 2018-10-31 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN107359208A (zh) * 2017-04-24 2017-11-17 杭州立昂微电子股份有限公司 一种肖特基势垒二极管及其制造方法
US10043826B1 (en) * 2017-07-26 2018-08-07 Qualcomm Incorporated Fully depleted silicon on insulator integration
CN108039361A (zh) * 2017-12-08 2018-05-15 深圳市晶特智造科技有限公司 半导体功率器件、半导体功率器件的终端结构及其制作方法
TWI667788B (zh) * 2018-03-23 2019-08-01 世界先進積體電路股份有限公司 半導體結構及其製造方法
CN110350018B (zh) * 2018-04-02 2023-05-26 世界先进积体电路股份有限公司 半导体结构及其制造方法
US10607880B2 (en) * 2018-08-30 2020-03-31 Nxp Usa, Inc. Die with buried doped isolation region
US11069804B2 (en) * 2018-08-31 2021-07-20 Alpha And Omega Semiconductor (Cayman) Ltd. Integration of HVLDMOS with shared isolation region
JP6937281B2 (ja) * 2018-09-14 2021-09-22 株式会社東芝 半導体装置
CN109616518B (zh) * 2018-12-13 2022-08-23 中国科学院微电子研究所 一种mos栅控晶闸管
JP7195167B2 (ja) * 2019-02-08 2022-12-23 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
TWI732182B (zh) * 2019-02-23 2021-07-01 世界先進積體電路股份有限公司 半導體裝置及其形成方法
CN110024134B (zh) 2019-02-28 2020-06-26 长江存储科技有限责任公司 具有增大的击穿电压的高电压半导体器件及其制造方法
US10892320B2 (en) 2019-04-30 2021-01-12 Vanguard International Semiconductor Corporation Semiconductor devices having stacked trench gate electrodes overlapping a well region
JP7227110B2 (ja) * 2019-09-18 2023-02-21 株式会社東芝 半導体装置
US11552190B2 (en) * 2019-12-12 2023-01-10 Analog Devices International Unlimited Company High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region
US11049957B1 (en) * 2020-04-16 2021-06-29 Monolithic Power Systems, Inc. LDMOS device with sinker link
TWI730814B (zh) * 2020-06-16 2021-06-11 力晶積成電子製造股份有限公司 絕緣閘雙極電晶體結構及其製造方法
TWI773254B (zh) * 2021-04-19 2022-08-01 立錡科技股份有限公司 高壓元件及其製造方法
CN114744049B (zh) * 2022-06-13 2022-09-27 瑞能半导体科技股份有限公司 碳化硅mosfet半导体器件及制作方法
CN115188832B (zh) * 2022-07-11 2023-04-14 东莞市金誉半导体有限公司 一种高压jfet器件及其制备方法
CN114975601A (zh) * 2022-07-28 2022-08-30 合肥晶合集成电路股份有限公司 一种半导体器件及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130458A (en) * 1996-03-28 2000-10-10 Kabushiki Kaisha Toshiba Power IC having SOI structure
US6958515B2 (en) * 2000-12-31 2005-10-25 Texas Instruments Incorporated N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects
TWI256673B (en) * 2005-09-05 2006-06-11 United Microelectronics Corp High voltage metal oxide semiconductor and fabricating method thereof
TWI256676B (en) * 2004-03-26 2006-06-11 Siliconix Inc Termination for trench MIS device having implanted drain-drift region

Family Cites Families (112)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
JPS5824018B2 (ja) * 1979-12-21 1983-05-18 富士通株式会社 バイポ−ラｉｃの製造方法
FR2498812A1 (fr) * 1981-01-27 1982-07-30 Thomson Csf Structure de transistors dans un circuit integre et son procede de fabrication
US4454647A (en) 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
JPS58100441A (ja) 1981-12-10 1983-06-15 Toshiba Corp 半導体装置の製造方法
US4655875A (en) * 1985-03-04 1987-04-07 Hitachi, Ltd. Ion implantation process
US6740958B2 (en) 1985-09-25 2004-05-25 Renesas Technology Corp. Semiconductor memory device
US4980747A (en) * 1986-12-22 1990-12-25 Texas Instruments Inc. Deep trench isolation with surface contact to substrate
US4819052A (en) * 1986-12-22 1989-04-04 Texas Instruments Incorporated Merged bipolar/CMOS technology using electrically active trench
JPS63173360A (ja) * 1987-01-13 1988-07-16 Nec Corp 半導体記憶装置
US5156989A (en) * 1988-11-08 1992-10-20 Siliconix, Incorporated Complementary, isolated DMOS IC technology
US5410175A (en) 1989-08-31 1995-04-25 Hamamatsu Photonics K.K. Monolithic IC having pin photodiode and an electrically active element accommodated on the same semi-conductor substrate
JP2662446B2 (ja) * 1989-12-11 1997-10-15 キヤノン株式会社 記録ヘッド及び記録ヘッド用素子基板
JP3093771B2 (ja) * 1990-03-22 2000-10-03 沖電気工業株式会社 半導体記憶装置
US5386136A (en) * 1991-05-06 1995-01-31 Siliconix Incorporated Lightly-doped drain MOSFET with improved breakdown characteristics
KR100292851B1 (ko) * 1991-09-27 2001-09-17 스콧 티. 마이쿠엔 높은얼리전압,고주파성능및고항복전압특성을구비한상보형바이폴라트랜지스터및그제조방법
EP0537684B1 (en) * 1991-10-15 1998-05-20 Texas Instruments Incorporated Improved performance lateral double-diffused MOS transistor and method of fabrication thereof
JPH05109886A (ja) * 1991-10-17 1993-04-30 N M B Semiconductor:Kk フイールドシールド分離構造の半導体装置およびその製造方法
US5856695A (en) * 1991-10-30 1999-01-05 Harris Corporation BiCMOS devices
US5374569A (en) 1992-09-21 1994-12-20 Siliconix Incorporated Method for forming a BiCDMOS
US5324973A (en) * 1993-05-03 1994-06-28 Motorola Inc. Semiconductor SRAM with trench transistors
US5420061A (en) * 1993-08-13 1995-05-30 Micron Semiconductor, Inc. Method for improving latchup immunity in a dual-polysilicon gate process
US5892264A (en) * 1993-10-04 1999-04-06 Harris Corporation High frequency analog transistors, method of fabrication and circuit implementation
JP3252569B2 (ja) * 1993-11-09 2002-02-04 株式会社デンソー 絶縁分離基板及びそれを用いた半導体装置及びその製造方法
US5498554A (en) * 1994-04-08 1996-03-12 Texas Instruments Incorporated Method of making extended drain resurf lateral DMOS devices
US5438005A (en) * 1994-04-13 1995-08-01 Winbond Electronics Corp. Deep collection guard ring
US5506431A (en) * 1994-05-16 1996-04-09 Thomas; Mammen Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications
US5684305A (en) * 1995-06-07 1997-11-04 Harris Corporation Pilot transistor for quasi-vertical DMOS device
WO1997004488A2 (en) * 1995-07-19 1997-02-06 Philips Electronics N.V. Semiconductor device of hv-ldmost type
FR2744285B1 (fr) 1996-01-25 1998-03-06 Commissariat Energie Atomique Procede de transfert d'une couche mince d'un substrat initial sur un substrat final
JPH09252049A (ja) * 1996-03-15 1997-09-22 Mitsubishi Electric Corp 多層埋め込みトレンチアイソレーション
US5807783A (en) * 1996-10-07 1998-09-15 Harris Corporation Surface mount die by handle replacement
KR100205609B1 (ko) 1997-01-06 1999-07-01 윤종용 정전기 보호 소자
US6163052A (en) * 1997-04-04 2000-12-19 Advanced Micro Devices, Inc. Trench-gated vertical combination JFET and MOSFET devices
US6011297A (en) * 1997-07-18 2000-01-04 Advanced Micro Devices,Inc. Use of multiple slots surrounding base region of a bipolar junction transistor to increase cumulative breakdown voltage
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
US5914523A (en) * 1998-02-17 1999-06-22 National Semiconductor Corp. Semiconductor device trench isolation structure with polysilicon bias voltage contact
KR100282710B1 (ko) * 1998-03-12 2001-02-15 윤종용 바이폴라 트랜지스터의 제조 방법 및 그 구조
US6331456B1 (en) * 1998-05-04 2001-12-18 Texas Instruments - Acer Incorporated Fipos method of forming SOI CMOS structure
US6013936A (en) * 1998-08-06 2000-01-11 International Business Machines Corporation Double silicon-on-insulator device and method therefor
US20010013636A1 (en) * 1999-01-22 2001-08-16 James S. Dunn A self-aligned, sub-minimum isolation ring
US6316336B1 (en) 1999-03-01 2001-11-13 Richard A. Blanchard Method for forming buried layers with top-side contacts and the resulting structure
US6225674B1 (en) * 1999-04-02 2001-05-01 Motorola, Inc. Semiconductor structure and method of manufacture
DE69931890T2 (de) * 1999-04-06 2007-01-11 Stmicroelectronics S.R.L., Agrate Brianza Integrierter Leistungsschaltkreis mit vertikalem Stromfluss und dessen Herstellungsverfahren
US6225181B1 (en) * 1999-04-19 2001-05-01 National Semiconductor Corp. Trench isolated bipolar transistor structure integrated with CMOS technology
US6144086A (en) 1999-04-30 2000-11-07 International Business Machines Corporation Structure for improved latch-up using dual depth STI with impurity implant
KR100300069B1 (ko) * 1999-05-10 2001-09-26 김영환 반도체 소자 및 그 제조방법
US6798024B1 (en) * 1999-07-01 2004-09-28 Intersil Americas Inc. BiCMOS process with low temperature coefficient resistor (TCRL)
JP2001135719A (ja) * 1999-11-01 2001-05-18 Denso Corp 半導体装置の素子分離構造
US6448124B1 (en) 1999-11-12 2002-09-10 International Business Machines Corporation Method for epitaxial bipolar BiCMOS
US6489653B2 (en) * 1999-12-27 2002-12-03 Kabushiki Kaisha Toshiba Lateral high-breakdown-voltage transistor
US6835627B1 (en) 2000-01-10 2004-12-28 Analog Devices, Inc. Method for forming a DMOS device and a DMOS device
US6399990B1 (en) * 2000-03-21 2002-06-04 International Business Machines Corporation Isolated well ESD device
IT1316871B1 (it) * 2000-03-31 2003-05-12 St Microelectronics Srl Dispositivo elettronico integrato monoliticamente e relativo processodi fabbricazione
IT1317516B1 (it) * 2000-05-11 2003-07-09 St Microelectronics Srl Dispositivo integrato con struttura d'isolamento a trench e relativoprocesso di realizzazione.
US6663167B2 (en) * 2000-05-15 2003-12-16 Jeffrey O. Phillips Collapsible shelter/camper/storage unit with a suspended floor
JP4984345B2 (ja) * 2000-06-21 2012-07-25 富士電機株式会社 半導体装置
SE518797C2 (sv) * 2000-07-19 2002-11-19 Ericsson Telefon Ab L M Effekt-LDMOS-transistor innefattande ett flertal parallellkopplade transistorsegment med olika tröskelspänningar
JP2002094063A (ja) * 2000-09-11 2002-03-29 Toshiba Corp 半導体装置
US6849871B2 (en) * 2000-10-20 2005-02-01 International Business Machines Corporation Fully-depleted-collector silicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS
JP2002198436A (ja) 2000-12-25 2002-07-12 Sanyo Electric Co Ltd 半導体集積回路装置およびその製造方法
JP2002198439A (ja) 2000-12-26 2002-07-12 Sharp Corp 半導体装置および携帯電子機器
US6600199B2 (en) 2000-12-29 2003-07-29 International Business Machines Corporation Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity
JP2002237575A (ja) * 2001-02-08 2002-08-23 Sharp Corp 半導体装置及びその製造方法
US20020117714A1 (en) * 2001-02-28 2002-08-29 Linear Technology Corporation High voltage MOS transistor
TW475250B (en) * 2001-03-14 2002-02-01 Taiwan Semiconductor Mfg ESD protection circuit to be used in high-frequency input/output port with low capacitance load
JP4811895B2 (ja) * 2001-05-02 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2003100862A (ja) * 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6563181B1 (en) * 2001-11-02 2003-05-13 Motorola, Inc. High frequency signal isolation in a semiconductor device
KR100456691B1 (ko) 2002-03-05 2004-11-10 삼성전자주식회사 이중격리구조를 갖는 반도체 소자 및 그 제조방법
JP2004039866A (ja) * 2002-07-03 2004-02-05 Toshiba Corp 半導体装置及びその製造方法
US7179691B1 (en) * 2002-07-29 2007-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for four direction low capacitance ESD protection
US6867462B2 (en) * 2002-08-09 2005-03-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device using an SOI substrate and having a trench isolation and method for fabricating the same
US7667268B2 (en) * 2002-08-14 2010-02-23 Advanced Analogic Technologies, Inc. Isolated transistor
US7956391B2 (en) * 2002-08-14 2011-06-07 Advanced Analogic Technologies, Inc. Isolated junction field-effect transistor
US7741661B2 (en) * 2002-08-14 2010-06-22 Advanced Analogic Technologies, Inc. Isolation and termination structures for semiconductor die
US7939420B2 (en) 2002-08-14 2011-05-10 Advanced Analogic Technologies, Inc. Processes for forming isolation structures for integrated circuit devices
US20080197408A1 (en) * 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
US7902630B2 (en) 2002-08-14 2011-03-08 Advanced Analogic Technologies, Inc. Isolated bipolar transistor
US6900091B2 (en) * 2002-08-14 2005-05-31 Advanced Analogic Technologies, Inc. Isolated complementary MOS devices in epi-less substrate
US8089129B2 (en) 2002-08-14 2012-01-03 Advanced Analogic Technologies, Inc. Isolated CMOS transistors
US7834421B2 (en) * 2002-08-14 2010-11-16 Advanced Analogic Technologies, Inc. Isolated diode
US6943426B2 (en) * 2002-08-14 2005-09-13 Advanced Analogic Technologies, Inc. Complementary analog bipolar transistors with trench-constrained isolation diffusion
US7825488B2 (en) * 2006-05-31 2010-11-02 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuits and modular methods of forming the same
US7719054B2 (en) * 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US7576388B1 (en) * 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
SE0303099D0 (sv) * 2003-11-21 2003-11-21 Infineon Technologies Ag Method in the fabrication of a monolithically integrated high frequency circuit
US7205584B2 (en) * 2003-12-22 2007-04-17 Micron Technology, Inc. Image sensor for reduced dark current
US20050179111A1 (en) * 2004-02-12 2005-08-18 Iwen Chao Semiconductor device with low resistive path barrier
US7304354B2 (en) * 2004-02-17 2007-12-04 Silicon Space Technology Corp. Buried guard ring and radiation hardened isolation structures and fabrication methods
WO2005078801A1 (en) * 2004-02-17 2005-08-25 Nanyang Technological University Method and device for wavelength-sensitive photo-sensing
JP4429036B2 (ja) * 2004-02-27 2010-03-10 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
TWI231986B (en) 2004-03-22 2005-05-01 Sunplus Technology Co Ltd ESD protection device for high voltage and negative voltage tolerance
US7009271B1 (en) * 2004-04-13 2006-03-07 Advanced Micro Devices, Inc. Memory device with an alternating Vss interconnection
US7183610B2 (en) * 2004-04-30 2007-02-27 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
JP4592340B2 (ja) 2004-06-29 2010-12-01 三洋電機株式会社 半導体装置の製造方法
JP2006074012A (ja) * 2004-08-06 2006-03-16 Renesas Technology Corp 双方向型静電気放電保護素子
US7335948B2 (en) * 2004-08-23 2008-02-26 Enpirion, Inc. Integrated circuit incorporating higher voltage devices and low voltage devices therein
US20060076629A1 (en) * 2004-10-07 2006-04-13 Hamza Yilmaz Semiconductor devices with isolation and sinker regions containing trenches filled with conductive material
JP4959140B2 (ja) * 2005-02-04 2012-06-20 株式会社日立超エル・エス・アイ・システムズ 半導体装置
CN2821868Y (zh) * 2005-05-19 2006-09-27 崇贸科技股份有限公司 具有隔离结构的mos场效应晶体管
JP4519716B2 (ja) 2005-06-02 2010-08-04 富士通セミコンダクター株式会社 整流回路用ダイオードを有する半導体装置
US7719080B2 (en) 2005-06-20 2010-05-18 Teledyne Scientific & Imaging, Llc Semiconductor device with a conduction enhancement layer
US20070132056A1 (en) * 2005-12-09 2007-06-14 Advanced Analogic Technologies, Inc. Isolation structures for semiconductor integrated circuit substrates and methods of forming the same
US20070158779A1 (en) * 2006-01-12 2007-07-12 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a buried damage layer
US7718481B2 (en) * 2006-04-17 2010-05-18 International Business Machines Corporation Semiconductor structure and method of manufacture
US7626243B2 (en) * 2006-08-04 2009-12-01 Advanced Analogic Technologies, Inc. ESD protection for bipolar-CMOS-DMOS integrated circuit devices
US7737526B2 (en) * 2007-03-28 2010-06-15 Advanced Analogic Technologies, Inc. Isolated trench MOSFET in epi-less semiconductor sustrate
US7795681B2 (en) * 2007-03-28 2010-09-14 Advanced Analogic Technologies, Inc. Isolated lateral MOSFET in epi-less substrate
US7541247B2 (en) * 2007-07-16 2009-06-02 International Business Machines Corporation Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication
US7683427B2 (en) * 2007-09-18 2010-03-23 United Microelectronics Corp. Laterally diffused metal-oxide-semiconductor device and method of making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130458A (en) * 1996-03-28 2000-10-10 Kabushiki Kaisha Toshiba Power IC having SOI structure
US6958515B2 (en) * 2000-12-31 2005-10-25 Texas Instruments Incorporated N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects
TWI256676B (en) * 2004-03-26 2006-06-11 Siliconix Inc Termination for trench MIS device having implanted drain-drift region
TWI256673B (en) * 2005-09-05 2006-06-11 United Microelectronics Corp High voltage metal oxide semiconductor and fabricating method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI578537B (zh) * 2014-08-01 2017-04-11 旺宏電子股份有限公司 高壓半導體元件
US10121889B2 (en) 2014-08-29 2018-11-06 Macronix International Co., Ltd. High voltage semiconductor device

Also Published As

Publication number Publication date
JP2011514675A (ja) 2011-05-06
KR20120115600A (ko) 2012-10-18
CN102867843A (zh) 2013-01-09
KR101483404B1 (ko) 2015-01-15
TW200945589A (en) 2009-11-01
KR101456408B1 (ko) 2014-11-04
JP5449203B2 (ja) 2014-03-19
KR101363663B1 (ko) 2014-02-14
KR20130103640A (ko) 2013-09-23
CN102867843B (zh) 2015-05-20
US8664715B2 (en) 2014-03-04
US20110260246A1 (en) 2011-10-27
CN102037562A (zh) 2011-04-27
WO2009108311A2 (en) 2009-09-03
KR101303405B1 (ko) 2013-09-05
US7667268B2 (en) 2010-02-23
WO2009108311A3 (en) 2009-10-22
HK1176462A1 (zh) 2013-07-26
US20080191277A1 (en) 2008-08-14
US8659116B2 (en) 2014-02-25
CN102037562B (zh) 2014-11-26
KR20110007109A (ko) 2011-01-21
KR20140065485A (ko) 2014-05-29
EP2248162A2 (en) 2010-11-10
US20100133611A1 (en) 2010-06-03
EP2248162A4 (en) 2015-08-12

Similar Documents

Publication Publication Date Title
TWI415262B (zh) 半導體晶粒之隔離電晶體、隔離二極體及隔離與終端結構
US7741661B2 (en) Isolation and termination structures for semiconductor die
US7956391B2 (en) Isolated junction field-effect transistor
US7834421B2 (en) Isolated diode
US20200381513A1 (en) Semiconductor chip integrating high and low voltage devices
US20080197408A1 (en) Isolated quasi-vertical DMOS transistor
US7649225B2 (en) Asymmetric hetero-doped high-voltage MOSFET (AH2MOS)
US7187033B2 (en) Drain-extended MOS transistors with diode clamp and methods for making the same
WO2019040375A1 (en) INTEGRATED CIRCUIT, TRAPEZOIDAL JFET LDMOS, LOWER TRIGGER AND BALLAST DRIVE AND METHOD OF MANUFACTURE
JP2012191053A (ja) 半導体装置およびその製造方法
TWI576989B (zh) 集成高壓器件的方法
CN118173559A (zh) 防闩锁效应的保护环结构、半导体装置及形成方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees