JP5504187B2 - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims description 44
- 239000012535 impurity Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 7
- 210000000746 body region Anatomy 0.000 description 42
- 238000012986 modification Methods 0.000 description 15
- 230000004048 modification Effects 0.000 description 15
- 108091006146 Channels Proteins 0.000 description 11
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- 230000015556 catabolic process Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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Description
第1の実施形態にかかる半導体装置31を示す図1を参照して、本実施形態を説明する。以下、N型チャネルLDMOSを例に説明するが、本発明は、このような半導体装置に限定されるものではなく、例えば、DMOS、LDMOS(Lateral DMOS)、DEMOS(Drain Extended MOS)、EDMOS(Extended Drain MOS)、MOSFET(MOS Field Effect Transistor)等の他の種類の半導体装置においても用いることができる。
第1の実施形態において開口部23は1つであったが、本実施形態においては複数の開口部23を設けるものである。
第1及び第2の実施形態においては、N型ドリフト領域11上のゲート電極8に開口部23が形成されており、すなわち、P型ボディ領域2上のゲート電極8とフィールド酸化膜7上のゲート電極8及びゲート絶縁膜24は完全には分離されていない。それに対して、第3の実施形態においては、N型ドリフト領域11をはさんでP型ボディ領域2上のゲート電極8(第1のゲート電極)及びゲート絶縁膜24(第1のゲート絶縁膜)と、フィールド酸化膜7上のゲート電極8(第2のゲート電極)及びゲート絶縁膜24(第2のゲート絶縁膜)とは完全に分離されている。本実施形態においては、分離されたゲート電極8は配線層10で接続し、同じ電位で用いても良い。また、接続する配線層は他の配線層でも良い。本実施形態では、このような構造にすることにより、第1及び第2の実施形態と比べて、キャリヤが通過するN型ドリフト領域11を広く形成することから、オン抵抗をより低減することができる。
Claims (7)
- 基板と、
前記基板の一部に形成された第2導電型ソース領域と、
前記第2導電型ソース領域と分離されるようにして前記基板の一部に形成された第2導電型ドレイン領域と、
前記第2導電型ソース領域に隣接して、前記第2導電型ソース領域と前記第2導電型ドレイン領域との間の前記基板に形成された第1導電型チャネル領域と、
前記第2導電型ドレイン領域に隣接して、前記第1導電型チャネル領域と前記第2導電型ドレイン領域との間に形成された第2導電型ドリフト領域の第1の部分と、
前記第1導電型チャネル領域と分離されるようにして、前記第2導電型ドリフト領域の第1の部分の表面に埋め込まれた酸化膜と、
ゲート絶縁膜を介して前記基板の表面を前記第1導電型チャネル領域から前記酸化膜の一部までを覆い、且つ、前記第1導電型チャネル領域と前記酸化膜との間に開口部を備えるゲート電極と、
前記開口部下の前記基板に形成された前記第2導電型ドリフト領域の第2の部分と、
を備えることを特徴とする半導体装置。 - 基板と、
前記基板の一部に形成された第2導電型ソース領域と、
前記第2導電型ソース領域と分離されるようにして前記基板の一部に形成された第2導電型ドレイン領域と、
前記第2導電型ソース領域に隣接して、前記第2導電型ソース領域と前記第2導電型ドレイン領域との間の前記基板に形成された第1導電型チャネル領域と、
前記第2導電型ドレイン領域に隣接して、前記第1導電型チャネル領域と前記第2導電型ドレイン領域との間に形成された第2導電型ドリフト領域の第1の部分と、
前記第1導電型チャネル領域と分離されるようにして、前記第2導電型ドリフト領域の第1の部分の表面に埋め込まれた酸化膜と、
第1のゲート絶縁膜を介して前記第1導電型チャネル領域を覆う第1のゲート電極と、
第2のゲート絶縁膜を介して前記酸化膜を覆う第2のゲート電極と、
前記第1のゲート絶縁膜と前記第2のゲート絶縁膜との間の前記基板に形成された前記第2導電型ドリフト領域の第2の部分とを備え、
前記第2導電型ドリフト領域における前記第2の部分の不純物濃度は、前記第2導電型ドリフト領域における前記第1の部分の不純物濃度よりも濃度が大きく、前記第2導電型ドレイン領域の不純物濃度よりも濃度が小さいことを特徴とする半導体装置。 - 前記第2導電型ドリフト領域における前記第2の部分の不純物濃度は、前記第2導電型ドリフト領域における前記第1の部分の不純物濃度よりも濃度が大きく、前記第2導電型ドレイン領域の不純物濃度よりも濃度が小さいことを特徴とする請求項1に記載の半導体装置。
- 前記開口部の前記第2導電型ドレイン領域側の側面が、前記酸化膜の前記第2導電型ソース領域側端の位置と比して前記第2導電型ドレイン領域側に位置していることを特徴とする請求項1に記載の半導体装置。
- 前記開口部の前記第2導電型ドレイン領域側の側面が、前記酸化膜の前記第2導電型ソース領域側端の位置と比して前記第2導電型ソース領域側に位置していることを特徴とする請求項1に記載の半導体装置。
- 前記第1のゲート電極と前記第2のゲート電極とは、配線層により電気的に接続されていることを特徴とする請求項2に記載の半導体装置。
- 基板の一部にその表面に酸化膜が形成された第1の第2導電型ドリフト領域を形成する工程と、
前記基板の一部に第1導電型チャネル領域を形成する工程と、
ゲート絶縁膜を介して前記基板の表面に前記第1導電型チャネル領域から前記酸化膜の一部までを覆うゲート電極を形成する工程と、
前記ゲート電極と前記ゲート絶縁膜とにおける前記第1導電型チャネル領域と前記酸化膜との間に開口部を形成する工程と、
前記ゲート電極と前記ゲート絶縁膜とをマスクとして用いて、前記開口部を介して不純物を添加して、前記第1の第2導電型ドリフト領域に接続する第2の第2導電型ドリフト領域を形成する工程と、
を有することを特徴とする半導体装置の製造方法。
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JP3387782B2 (ja) * | 1997-07-14 | 2003-03-17 | 松下電器産業株式会社 | 半導体装置 |
US7667268B2 (en) * | 2002-08-14 | 2010-02-23 | Advanced Analogic Technologies, Inc. | Isolated transistor |
DE10345347A1 (de) * | 2003-09-19 | 2005-04-14 | Atmel Germany Gmbh | Verfahren zur Herstellung eines DMOS-Transistors mit lateralem Driftregionen-Dotierstoffprofil |
JP2006140447A (ja) * | 2004-10-14 | 2006-06-01 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7405443B1 (en) * | 2005-01-07 | 2008-07-29 | Volterra Semiconductor Corporation | Dual gate lateral double-diffused MOSFET (LDMOS) transistor |
KR100669858B1 (ko) * | 2005-05-13 | 2007-01-16 | 삼성전자주식회사 | 고전압 반도체 장치 및 그 제조 방법 |
JP4601603B2 (ja) * | 2006-12-27 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | パワーmisfet、半導体装置およびdc/dcコンバータ |
-
2011
- 2011-01-26 JP JP2011014270A patent/JP5504187B2/ja not_active Expired - Fee Related
- 2011-08-05 US US13/204,554 patent/US20120187485A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014215206A (ja) * | 2013-04-26 | 2014-11-17 | 三菱電機株式会社 | 半導体圧力センサおよびその製造方法 |
US9395258B2 (en) | 2013-04-26 | 2016-07-19 | Mitsubishi Electric Corporation | Semiconductor pressure sensor and fabrication method thereof |
US10573743B2 (en) | 2018-03-16 | 2020-02-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
Also Published As
Publication number | Publication date |
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JP2012156318A (ja) | 2012-08-16 |
US20120187485A1 (en) | 2012-07-26 |
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