JP4820899B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4820899B2 JP4820899B2 JP2009244117A JP2009244117A JP4820899B2 JP 4820899 B2 JP4820899 B2 JP 4820899B2 JP 2009244117 A JP2009244117 A JP 2009244117A JP 2009244117 A JP2009244117 A JP 2009244117A JP 4820899 B2 JP4820899 B2 JP 4820899B2
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- 239000004065 semiconductor Substances 0.000 title claims description 107
- 239000012535 impurity Substances 0.000 claims description 22
- 239000010410 layer Substances 0.000 description 172
- 108091006146 Channels Proteins 0.000 description 94
- 230000015556 catabolic process Effects 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
しかし、ただソース層とバックゲート層とを交互に配置しただけでは、バックゲート層におけるゲート電極沿いにソース領域がなくなることになり、実効ゲート幅(チャネル幅方向の実効的なゲート長さ)が短くなる。すなわち、実効ゲート幅が短くなることで素子のオン抵抗が増大してしまい、チャネル長方向の長さを短くできても素子のオン抵抗(Ron・A)の低減を実現できない。
図2(a)は図1におけるA−A’断面に対応する模式断面図であり、図2(b)は図1におけるB−B’断面に対応する模式断面図であり、図2(c)は図1におけるC−C’断面に対応する模式断面図である。
本実施形態に係る半導体装置は、ゲートオン時、基板表面に形成されたドレイン領域とソース領域との間を結ぶ横方向に主電流が流れる横型半導体装置である。
Claims (6)
- 第1導電型の一対のドレイン領域と、
前記一対のドレイン領域の間で前記ドレイン領域に対して離間して設けられたソース領域と、
第2導電型の一対のチャネル領域であって、前記一対のドレイン領域のうちの一方のドレイン領域と前記ソース領域との間に設けられた一方のチャネル領域と、前記一対のドレイン領域のうちの他方のドレイン領域と前記ソース領域との間に設けられた他方のチャネル領域とを含む一対のチャネル領域と、
前記一方のチャネル領域及び前記他方のチャネル領域上に設けられた絶縁膜と、
前記絶縁膜上に設けられたゲート電極と、
前記ドレイン領域よりも第1導電型不純物濃度が低い第1導電型の一対の第1の半導体領域であって、前記一方のドレイン領域と前記一方のチャネル領域との間に設けられた一方の第1の半導体領域と、前記他方のドレイン領域と前記他方のチャネル領域との間に設けられた他方の第1の半導体領域とを含む一対の第1の半導体領域と、
前記ドレイン領域よりも第1導電型不純物濃度が低い第1導電型の一対の第2の半導体領域であって、前記一方のチャネル領域と前記ソース領域との間に設けられた一方の第2の半導体領域と、前記他方のチャネル領域と前記ソース領域との間に設けられた他方の第2の半導体領域とを含み、チャネル幅方向に延在して設けられた一対の第2の半導体領域と、
を備え、
前記ソース領域は、前記一対の第2の半導体領域の間にチャネル幅方向に延在して設けられており、
前記ソース領域内に形成され、チャネル長方向の一方側で前記一方の第2の半導体領域に接し、前記チャネル長方向の他方側では前記他方の第2の半導体領域に接せず、前記ソース領域と同じ電極に電気的に接続される第2導電型の第1のバックゲート層と、
前記ソース領域内に形成され、チャネル長方向の他方側で前記他方の第2の半導体領域に接し、前記チャネル長方向の一方側では前記一方の第2の半導体領域に接せず、前記ソース領域と同じ電極に電気的に接続される第2導電型の第2のバックゲート層と、
を有し、
前記一対の第2の半導体領域の第1導電型不純物濃度は、前記ソース領域の第1導電型不純物濃度よりも低いことを特徴とする半導体装置。 - 前記第1のバックゲート層と前記第2のバックゲート層は、チャネル幅方向に間欠的に設けられていることを特徴とする請求項1記載の半導体装置。
- 前記第1のバックゲート層と前記第2のバックゲート層は、チャネル幅方向に交互に設けられていることを特徴とする請求項1または2に記載の半導体装置。
- 前記ゲート電極の側壁に設けられたサイドウォール絶縁膜をさらに備え、
前記サイドウォール絶縁膜の下に、前記第1の半導体領域と前記第2の半導体領域が設けられていることを特徴とする請求項1〜3のいずれか1つに記載の半導体装置。 - 前記第1の半導体領域と前記第2の半導体領域とは、第1導電型不純物濃度が同じであることを特徴とする請求項1〜4のいずれか1つに記載の半導体装置。
- 前記第1の半導体領域の方が、前記第2の半導体領域よりも前記チャネル長方向の長さが長いことを特徴とする請求項1〜5のいずれか1つに記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009244117A JP4820899B2 (ja) | 2009-10-23 | 2009-10-23 | 半導体装置 |
US12/878,979 US8362554B2 (en) | 2009-10-23 | 2010-09-09 | MOSFET semiconductor device with backgate layer and reduced on-resistance |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009244117A JP4820899B2 (ja) | 2009-10-23 | 2009-10-23 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011091231A JP2011091231A (ja) | 2011-05-06 |
JP4820899B2 true JP4820899B2 (ja) | 2011-11-24 |
Family
ID=43897658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2009244117A Expired - Fee Related JP4820899B2 (ja) | 2009-10-23 | 2009-10-23 | 半導体装置 |
Country Status (2)
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US (1) | US8362554B2 (ja) |
JP (1) | JP4820899B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5700649B2 (ja) * | 2011-01-24 | 2015-04-15 | 旭化成エレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5960445B2 (ja) * | 2012-02-23 | 2016-08-02 | ラピスセミコンダクタ株式会社 | 半導体装置 |
JP6184057B2 (ja) * | 2012-04-18 | 2017-08-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6383325B2 (ja) | 2014-06-27 | 2018-08-29 | 株式会社東芝 | 半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001119019A (ja) * | 1999-10-19 | 2001-04-27 | Nec Corp | 半導体装置およびその製造方法 |
JP4545548B2 (ja) * | 2004-10-21 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | 半導体集積回路及び半導体装置 |
JP4907920B2 (ja) | 2005-08-18 | 2012-04-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2007081193A (ja) | 2005-09-15 | 2007-03-29 | Toshiba Corp | Mosfet |
JP2008119019A (ja) * | 2006-11-08 | 2008-05-29 | Matsushita Electric Works Ltd | キッチン設備 |
KR100871550B1 (ko) * | 2006-12-20 | 2008-12-01 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
US7602037B2 (en) * | 2007-03-28 | 2009-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage semiconductor devices and methods for fabricating the same |
-
2009
- 2009-10-23 JP JP2009244117A patent/JP4820899B2/ja not_active Expired - Fee Related
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2010
- 2010-09-09 US US12/878,979 patent/US8362554B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US20110095369A1 (en) | 2011-04-28 |
JP2011091231A (ja) | 2011-05-06 |
US8362554B2 (en) | 2013-01-29 |
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