JP4601603B2 - パワーmisfet、半導体装置およびdc/dcコンバータ - Google Patents
パワーmisfet、半導体装置およびdc/dcコンバータ Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 40
- 238000000034 method Methods 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 36
- 238000002955 isolation Methods 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 9
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 30
- 230000015572 biosynthetic process Effects 0.000 description 14
- 230000000052 comparative effect Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 9
- 238000009826 distribution Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000009191 jumping Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Description
ISPSD‘05pp.367−370 ISPSD‘05pp.339−342
本実施の形態1では、パワーMISFETの例として、半導体基板の一方の主面に沿って、ソース領域と、チャネル領域と、ドリフト領域と、ドレイン領域とが順に配置された横型パワーMOSFETを例として説明する。
図20は、本発明の実施の形態2の横型パワーMOSFET300の構造を示す斜視図である。本実施の形態2の特徴は、ソース層Sとボディーコンタクト層BCとが、ソース層S、ゲート電極Gおよびドレイン層Dが配置される配列方向である第1の方向と交差する第2の方向に沿って交互に配置されている点である。
図21は、本発明の実施の形態3の横型パワーMOSFET400の構造を示す断面図である。本実施の形態3の特徴は、横型パワーMOSFET400のドリフト領域内にあるトレンチ領域16が素子分離用のSTI領域(第1素子分離領域および第2素子分離領域)3に比べて、浅いことである。
図24は、本発明の実施の形態4の横型パワーMOSFET500の断面図を示す。本実施の形態4の特徴は、前記実施の形態1で説明した横型パワーMOSFET100のドリフト領域内にあるトレンチ領域16の直下(トレンチ領域16の主面100aと反対側に位置する面)に、HV−Nwell層4より高濃度のn層21が追加されている点である。
2 p−エピタキシャル層
3 STI領域
4 HV−Nウェル層(ドリフト領域)
5 p−ウェル層
6 n−ウェル層
7 ゲート絶縁膜
8 ポリシリコン
9 p−チャネル層(チャネル領域)
10 n−LDD層
11 p−LDD層
12 サイドウォール
13 n+層
14 p+層
15 シリサイド層
16 トレンチ領域
21 n層
22 p+打ち抜き拡散層
23 n−ドリフト層
24 絶縁膜
25 AL配線
26 LOCOS
27 ゲートのp−チャネル層のはみ出し部分
28 引き出し領域
100、200、300、400、500、700 横型パワーMOSFET
BC ボディーコンタクト層
G ゲート電極(第1導電層)
DG ダミーゲート電極(第2導電層)
D ドレイン層(ドレイン領域)
S ソース層(ソース領域)
Claims (11)
- 少なくとも一つの主面を備える半導体基板を有し、
前記半導体基板の主面には、前記半導体基板の主面に沿ってソース領域と、チャネル領域と、ドリフト領域と、ドレイン領域とが順に配置され、
前記ドリフト領域内には、前記半導体基板の主面から前記半導体基板内部に向かう方向に前記ドリフト領域より浅く絶縁層が形成されたトレンチ領域を備え、
前記半導体基板の主面上には、
前記チャネル領域上に絶縁膜を介して配置されるゲート電極層と、
前記ドリフト領域上及び前記トレンチ領域上に絶縁膜を介して配置されるダミーゲート電極層とを備え、
前記半導体基板の主面における平面上の配置は、
前記ゲート電極層を挟んで互いに反対側に前記ソース領域と前記ドレイン領域とが配置され、かつ、前記ゲート電極層は、前記トレンチ領域と重ならず、
前記ゲート電極層と前記ドレイン領域との間に、前記ダミーゲート電極層が前記ゲート電極層と離間して配置され、かつ、前記ダミーゲート電極層の前記ドレイン領域側の端部は、前記トレンチ領域と重なり、前記ダミーゲート電極層の前記ソース領域側の端部は、前記ドリフト領域と重なり、
前記ダミーゲート電極層は、前記ソース領域と電気的に接続されていることを特徴とするパワーMISFET。 - 請求項1に記載のパワーMISFETにおいて、
前記ゲート電極層とダミーゲート電極層は同一工程で形成されていることを特徴とするパワーMISFET。 - 請求項2に記載のパワーMISFETにおいて、
前記ゲート電極層及びダミーゲート電極層の部材はポリシリコンであることを特徴とするパワーMISFET。 - 請求項1に記載のパワーMISFETにおいて、
前記ゲート電極層および前記ダミーゲート電極層の両側面にはそれぞれサイドウォールを有し、
前記サイドウォールのうち、前記ゲート電極層と前記ダミーゲート電極層間のサイドウォールは接していることを特徴とするパワーMISFET。 - 請求項4に記載のパワーMISFETにおいて、
前記ゲート電極層および前記ダミーゲート電極層の上面と、
前記ドレイン領域の上面と、
前記ソース領域の上面とには、
シリサイド層が形成されていることを特徴とするパワーMISFET。 - 請求項5に記載のパワーMISFETにおいて、
前記シリサイド層は、コバルトシリサイド、またはチタンシリサイドであることを特徴とするパワーMISFET。 - 請求項1に記載のパワーMISFETにおいて、
前記トレンチ領域の底面側には、
前記ドリフト領域と同じ導電型で、前記ドリフト領域よりも高濃度の不純物領域が形成されていることを特徴とするパワーMISFET。 - 少なくとも一つの主面を備える半導体基板を有し、
同一チップの前記半導体基板内に横型パワーMISFET素子と、前記横型パワーMISFET素子を駆動するCMOSドライバ素子とを有し、
前記横型パワーMISFET素子は、
前記半導体基板の主面に、前記半導体基板の主面に沿ってソース領域と、チャネル領域と、ドリフト領域と、ドレイン領域とが順に配置され、
前記ドリフト領域内には、前記半導体基板の主面から前記半導体基板内部に向かう方向に前記ドリフト領域より浅く絶縁層が形成されたトレンチ領域を備え、
前記半導体基板の主面上には、
前記チャネル領域上に絶縁膜を介して配置されるゲート電極層と、
前記ドリフト領域上及び前記トレンチ領域上に絶縁膜を介して配置されるダミーゲート電極層とを備え、
前記半導体基板の主面における平面上の配置は、
前記ゲート電極層を挟んで互いに反対側に前記ソース領域と前記ドレイン領域とが配置され、かつ、前記ゲート電極層は、前記トレンチ領域と重ならず、
前記ゲート電極層と前記ドレイン領域との間に、前記ダミーゲート電極層が前記ゲート電極層と離間して配置され、かつ、前記ダミーゲート電極層の前記ドレイン領域側の端部は、前記トレンチ領域と重なり、前記ダミーゲート電極層の前記ソース領域側の端部は、前記ドリフト領域と重なり、
前記ダミーゲート電極層は、前記ソース領域と電気的に接続されていることを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記CMOSドライバ素子の素子領域と前記横型パワーMISFET素子の素子領域とを分離する第1素子分離領域と、
前記CMOSドライバ素子が備える複数の素子領域を分離する第2素子分離領域とを有し、
前記トレンチ領域の前記主面から内部に向かう方向の深さは、前記第1素子分離領域、及び前記第2素子分離領域の深さよりも浅いことを特徴とする半導体装置。 - ハイサイドスイッチと、
ローサイドスイッチとを有し、
前記ハイサイドスイッチまたは前記ローサイドスイッチの少なくともいずれか一方には、横型パワーMISFETが用いられ、
前記横型パワーMISFETは、
少なくとも一つの主面を備える半導体基板を有し、
前記半導体基板の主面には、前記半導体基板の主面に沿ってソース領域と、チャネル領域と、ドリフト領域と、ドレイン領域とが順に配置され、
前記ドリフト領域内には、前記半導体基板の主面から前記半導体基板内部に向かう方向に前記ドリフト領域より浅く絶縁層が形成されたトレンチ領域を備え、
前記半導体基板の主面上には、
前記チャネル領域上に絶縁膜を介して配置されるゲート電極層と、
前記ドリフト領域上及び前記トレンチ領域上に絶縁膜を介して配置されるダミーゲート電極層とを備え、
前記半導体基板の主面における平面上の配置は、
前記ゲート電極層を挟んで互いに反対側に前記ソース領域と前記ドレイン領域とが配置され、かつ、前記ゲート電極層は、前記トレンチ領域と重ならず、
前記ゲート電極層と前記ドレイン領域との間に、前記ダミーゲート電極層が前記ゲート電極層と離間して配置され、かつ、前記ダミーゲート電極層の前記ドレイン領域側の端部は、前記トレンチ領域と重なり、前記ダミーゲート電極層の前記ソース領域側の端部は、前記ドリフト領域と重なり、
前記ダミーゲート電極層は、前記ソース領域と電気的に接続されていることを特徴とするDC/DCコンバータ。 - 請求項10に記載のDC/DCコンバータにおいて、
前記横型パワーMISFETは、
同一チップの前記半導体基板内に横型パワーMISFET素子と、前記横型パワーMISFET素子を駆動するCMOSドライバ素子を有していることを特徴とするDC/DCコンバータ。
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