CN106298768B - 半导体元件及半导体元件的操作方法 - Google Patents

半导体元件及半导体元件的操作方法 Download PDF

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CN106298768B
CN106298768B CN201510315077.2A CN201510315077A CN106298768B CN 106298768 B CN106298768 B CN 106298768B CN 201510315077 A CN201510315077 A CN 201510315077A CN 106298768 B CN106298768 B CN 106298768B
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semiconductor element
substrate
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CN106298768A (zh
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浦士杰
李明宗
杨承桦
李年中
李文芳
王智充
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及半导体元件的操作方法，该半导体元件包含：基板；深阱区，设置于基板中的一侧；元件区，设置于深阱区中位于基板的该侧；漏极区，设置于深阱区中位于基板的该侧，环绕元件区；栅极结构，设置于基板的该侧上，与深阱区相邻环绕漏极区；阱区，设置于深阱区中位于基板的该侧，环绕栅极结构；源极区，设置于阱区中位于基板的该侧，环绕栅极结构；主体接触区，与源极区分离地设置于阱区中，环绕源极区；以及环型掺杂区，与深阱区分离地设置于基板中的该侧，环绕深阱区。依据操作方法的不同，半导体元件能做为高压侧元件或是整合型靴带式二极管元件。高压侧元件具好的耐压稳定性，以克服现有防护环稳定性不足的缺陷。

Description

半导体元件及半导体元件的操作方法
技术领域
本发明涉及一种半导体元件，特别是涉及一种具有内建靴带式二极管功能的高压侧半导体元件与一种半导体元件的操作方法。
背景技术
随着半导体集成电路产业的急速发展，科技的进步体现在集成电路(IC)的材料应用与设计上，产生体积越来越小且结构越发复杂的市场趋势。一个智能功率集成电路(smart power IC)更可能同时包含多个功率器件与控制电路在一个芯片上，功率器件如高压晶体管或高功率晶体管(high-voltage,high-powered transistors)，而控制电路则如低压晶体管或低功率晶体管(low-voltage,low-power transistors)。因此，在高压侧区(high-side region)设置防护环(high-side guard ring)，以及防护环的效能与稳定性对于目前的IC芯片来说极为重要。
为不影响高压侧区以外的装置，以及安全考虑下，防护环需能有效隔离高压侧区与其他装置，并且具有良好的降压效果与长时间运作的稳定性。据此，发明人以通过长达1000小时的高温反性偏压的可靠性测试(high temperature reverse bias reliabilitytest,HTRB test)为标准进行测试，但经过发明人实验后发现，若HTRB测试以提供700伏特为例，以目前现有的防护环设计来说，连达到500小时的稳定度都无法提供。因此，在产品尺寸受限的前提下，维持防护环效能的同时并改善其稳定性与效能，成为本发明讨论的课题。
发明内容
为解决上述问题，本发明提供一种高压侧半导体元件，包含：基板，具有一侧；深阱区，设置于基板中的该侧；元件区，设置于深阱区中且位于基板的该侧；漏极区，设置于深阱区中且位于基板的该侧，环绕元件区；栅极结构，设置于基板的该侧上，与深阱区相邻且环绕漏极区；阱区，设置于深阱区中且位于基板的该侧，环绕栅极结构；源极区，设置于阱区中且位于基板的该侧，环绕栅极结构；主体接触区，与源极区分离地设置于阱区中，环绕源极区；以及环型掺杂区，与深阱区分离地设置于基板中的该侧，环绕深阱区。
在本发明的优选实施例中，上述的其中漏极区包含漏极轻掺杂区，环绕元件区；以及漏极接触区，设置于漏极轻掺杂区内。
在本发明的优选实施例中，上述的高压侧半导体元件，还包含多个隔离结构，分别设置于元件区与漏极区之间。
在本发明的优选实施例中，上述的高压侧半导体元件，还包含隔离深阱区，设置于该基板内与该深阱区相邻，并且位于该元件区相对于该基板的该侧的一另侧。
在本发明的优选实施例中，上述的高压侧半导体元件，还包含上阱区，设置于深阱区中，并被栅极结构覆盖。
在本发明的优选实施例中，上述的上阱区为环型，环绕漏极区。
在本发明的优选实施例中，上述的上阱区与栅极结构相接触。
在本发明的优选实施例中，上述的上阱区与栅极结构间彼此分离。
在本发明的优选实施例中，上述的源极区包含源极掺杂区61；以及源极接触区，设置于源极掺杂区中。
在本发明的优选实施例中，上述的源极掺杂区与源极接触区为环型，环绕栅极结构。
在本发明的优选实施例中，上述的源极区与主体接触区7之间以隔离结构分离。
在本发明的优选实施例中，上述的主体接触区包含主体接触轻掺杂区；以及主体接触掺杂区，设置于主体接触轻掺杂区中。
在本发明的优选实施例中，上述的主体接触轻掺杂区与主体接触掺杂区为环型，环绕栅极结构4。
在本发明的优选实施例中，上述的环型掺杂区包含环型轻掺杂区；环型掺杂区，设置于环型轻掺杂区中；以及环型接触区，设置于环型掺杂区中。
在本发明的优选实施例中，上述的高压侧半导体元件，还包含外围深阱区，设置于深阱区中，与阱区相邻且环绕该阱区。
本发明还提供一种半导体元件的操作方法，其中该半导体元件包含一具有一侧的基板、一设置于该基板中的该侧的深阱区、一设置于该深阱区中且位于该基板的该侧的元件区、一设置于该深阱区中位于该基板的该侧且环绕该元件区的漏极区、一设置于该基板的该侧上与该深阱区相邻且环绕该漏极区的栅极结构、一设置于该深阱区中位于该基板的该侧且环绕该栅极结构的阱区、一设置于该阱区中位于该基板的该侧且环绕该栅极结构的源极区、一设置于该阱区中与该源极区分离且环绕该源极区的主体接触区，以及一设置于该基板中的该侧与该深阱区分离且环绕该深阱区的环型掺杂区，包含以下步骤：提供该主体接触区与该环型掺杂区一接地电压；提供该源极区与该栅极结构该接地电压或一第一电源电压；提供该漏极区一第二电源电压或使该漏极区呈现一浮接状态。
在本发明的优选实施例中，其中提供至该源极区与该栅极结构是该接地电压，而提供至该漏极区是该第二电源电压。
在本发明的优选实施例中，其中该第二电源电压介于500-800伏特(V)之间。
在本发明的优选实施例中，其中提供至该源极区与该栅极结构是该第一电源电压，而该漏极区呈现该浮接状态。
在本发明的优选实施例中，上述的其中该第一电源电压大于0伏特且小于等于30伏特(V)。
在本发明的优选实施例中，其中当提供至源极区与栅极结构是第一电源电压，而漏极区呈现浮接状态时，漏极区会产生一小于第一电源电压的正电压。
因此，依据本发明提供的上述半导体元件与其操作方法，当元件呈现关闭状态(off-state)时，能做为高压侧元件，提供较高的耐压稳定性，改善现有技术中产生的问题，并且不影响产品尺寸；另一方面，当元件呈现导通状态(on-state)时，能做为内建靴带式二极管功能的半导体元件，达到整合的功效。
附图说明
图1为本发明的基本结构剖面示意图；
图2为图1的结构俯视图；
图3为本发明一实施例所绘制的结构剖面示意图；
图4为图3所绘制的结构俯视图。
符号说明
1：基板 2：深阱区
3：漏极区 4：栅极结构
5：阱区 6：源极区
7：主体接触区 8：环型掺杂区
9：隔离结构 10：隔离深阱区
11：上阱区 12：外围深阱区
31：漏极轻掺杂区 32：漏极接触区
61：源极掺杂区 62：源极接触区
71：主体接触轻掺杂区 72：主体接触掺杂区
81：环型轻掺杂区 82：环型掺杂区
83：环型接触区 S1、S2：基板的一侧
P1：防护环 P2：元件区
具体实施方式
本发明是在提供一种半导体元件，当其做为高压侧元件的应用时，能提供较高的耐压稳定性，达到优选的防护措施，并且不会造成产品尺寸的放大；当连接不同电压时，还可做为靴带式二极管的应用，达到整合的功效。为让本发明的上述和其他目的、特征和优点能更明显易懂，下文以实施例配合所附的附图，做详细说明。
图1为本发明提供的半导体元件的基本结构剖面示意图，本发明提供的半导体元件包含基板1具有第一侧S1与第二侧S2、深阱区2、漏极区3、栅极结构4、阱区5、源极区6、主体接触区7以及环型掺杂区8。各元件的位置关系如图1所示，深阱区2设置于基板1中的第一侧S1；漏极区3设置于深阱区2中且位于基板1的第一侧S1；栅极结构4设置于基板1的第一侧S1上，与深阱区2相邻且环绕中央漏极区3；阱区5设置于深阱区2中，环绕栅极结构4；源极区6设置于阱区5中，环绕栅极结构4；主体接触区7与源极区6分离地设置于阱区5中，环绕源极区6与栅极结构4；而环型掺杂区8与深阱区2分离地设置于基板1中的第一侧S1，环绕深阱区2。各区的掺杂型可以为N或P型掺杂，至于各区使用的掺杂型，则可依据需要做相对应的调整。如当基板1为P型时，深阱区2为N型，阱区5为P型，源极区6与漏极区3为N型，主体接触区7为P型，而环型掺杂区8为P型。此部分由于与现有技术相同，因此不再多做赘述。
在本案的结构概念下，基板1以P型为例说明，当元件做为高压侧元件应用时，元件处于电流封闭的状态(off-state)，位于基板1中间的元件区P2形成高压侧区，而其他区域则形成防护环P1，其俯视图如图2所示。元件区P2可以包含多个元件，元件类型及数量可依需要做调整，防护环P1包含漏极区3、栅极结构4、深阱区5、源极区6、主体接触区7以及环型掺杂区8，用以有效降压。在运作过程中，深阱区2与阱区5之间会产生因PN接面造成压差，而本案中电压源极区6与主体接触区7虽同样位于阱区5中，但两者彼此分离，提供较多的保护与较好的降压效果。同时也由于电压源极区6与主体接触区7彼此分离，在长时间使用后不会因掺杂离子的分布改变而造成互相干扰，引发其他寄生效应或导致元件的故障。
本案提供的半导体结构能承受的电压达800伏特(V)。在进行HTRB测试时，发明人提供元件区P2(高压侧区)700伏特(V)的电压，并将基板1(主体接触区7与环型掺杂区8)、源极区6与栅极结构4接地，本发明提供的结构能通过1000小时的HTRB测试。
发明人进一步发现，由于本案中源极区6与主体接触区7彼此分离，因此可以分别提供不同的电压。当主体接触区7与环型掺杂区8接地，并且提供一小于等于30V的正电压于源极区6与栅极结构4，同时使漏极区3处于浮接状态(floating)，可以打开通道，逆向导通该元件。此时元件处于导通状态(on-state)，以提升漏极区3的电压，使漏极区3产生一低于提供至源极区6的电压的正电压，达到靴带式二极管(bootstrap diode，或称自举电路)的功效。目前的半导体芯片都是外接靴带式二极管，而本发明提供的结构不仅能解决现有技术中高压侧元件所遇到的耐压性与稳定性问题，更能同时达到将靴带式二极管整合于元件中的功效。
图3为依据本发明的一实施例所绘制的剖面结构示意图，除包含同图1的基本结构外，同时因应实际应用增加了一些细部结构。为简化说明，相同于图1中的结构，将沿用相同元件标号。
基板1具有第一侧S1与第二侧S2，深阱区2设置于基板1中的第一侧S1，元件区P2设置于深阱区2中且位于基板1的第一侧S1，漏极区3同样设置于深阱区2中且位于基板1的第一侧S1，并环绕元件区P2。在此实施例中，元件区P2可以包含不同的所需元件，由于可以依状况作调整，因此不做赘述。漏极区3包含环绕元件区P2的漏极轻掺杂区31，与漏极接触区32，设置于漏极轻掺杂区31内且环绕元件区P2。元件区P2与漏极区3之间以隔离结构9隔离。栅极结构4设置于基板1的第一侧S1上，与深阱区2相邻且环绕漏极区3。阱区5则设置于深阱区2中位于基板1的第一侧S1，环绕栅极结构4。此实施例中，栅极结构4包含隔离结构9、间隙壁、栅极介电层、高介电常数层、栅电极等，由于此部分栅极结构4的细部元件可能依据制作工艺不同而有些许差异，但可依实际需求做调整，因此不做赘述。
同样如图3所示，源极区6设置于阱区5中位于基板1的第一侧S1，且环绕栅极结构4。在此实施例中，源极区6包含源极掺杂区61以及设置于源极掺杂区61中的源极接触区62，其中，源极掺杂区61与源极接触区62均为环型，环绕栅极结构4。主体接触区7与源极区6以隔离结构9分离，设置于阱区5中，环绕源极区6与栅极结构4。主体接触区7还可以包含主体接触轻掺杂区71，以及设置于主体接触轻掺杂区71中的主体接触掺杂区72。其中主体接触轻掺杂区71与主体接触掺杂区72均为环型，环绕该栅极结构4。环型掺杂区8与深阱区2分离地设置于基板1中的第一侧S1，环绕深阱区2，在本实施例中两者以隔离结构9分离。环型掺杂区8包含环型轻掺杂区81、设置于该环型轻掺杂区81中的环型掺杂区82、以及设置于该环型掺杂区82中的环型接触区83。环型轻掺杂区81、环型掺杂区82与环型接触区83均为环型，环绕深阱区2。
此实施例还包含隔离深阱区10、上阱区11与外围深阱区12。隔离深阱区10设置于基板1内与深阱区2相邻，位于相对于基板1的第一侧S1的第二侧S2，其横向覆盖范围对应于元件区P2。当元件区P2形成高压侧区时，可以有效防止高电压侧区的元件在操作时发生电压垂直穿透(vertical punch-through)。上阱区11为环型，设置于深阱区2中环绕元件区P2，并被栅极结构4覆盖。上阱区的掺杂型不同于深阱区2，其设置能提供类似电容的功用，提升半导体元件的降压效果。在此实施例中，上阱区11与栅极结构4彼此分离，但在其他实施例中可与栅极结构4相接触(未绘示于图中)。外围深阱区12设置于深阱区2中，与阱区5相邻且环绕阱区5，其掺杂型与深阱区2相同，不同于阱区5。外围深阱区12的存在可以有效防止电压的横向穿透(horizontal punch-through)。
图4所示为依据上述实施例所绘制的结构俯视图，防护环P1包含漏极区3、栅极结构4、阱区5、源极区6、主体接触区7与环型掺杂区8。本发明实施例中，基板1为P型，深阱区2为N型，阱区5为P型，源极区6与漏极区3为N型，主体接触区7为P型，环型掺杂区8为P型，隔离深阱区10为N型，上阱区11为P型，外围深阱区12为N型。掺杂浓度上，主体接触区7的浓度范围约介于1×1013～1×1015原子每立方厘米(dopant atoms per cm3)，其中主体接触轻掺杂区71约为1×1013dopant atoms per cm3，主体接触掺杂区72约为1×1015dopant atoms percm3；源极区6的浓度范围约介于1×1013～1×1015dopant atoms per cm3，其中源极掺杂区61约为1×1013dopant atoms per cm3，源极接触区62约为1×1015dopant atoms per cm3；漏极区3的浓度范围约介于1×1013～1×1015dopant atoms per cm3，其中漏极轻掺杂区31约为1×1013dopant atoms per cm3，漏极接触区32约为1×1015dopant atoms per cm3；外围深阱区12的掺杂浓度约为1×1012dopant atoms per cm3；阱区5的掺杂浓度约为1×1013dopant atoms per cm3；深阱区2的掺杂浓度约为1×1012dopant atoms per cm3；上阱区11的掺杂浓度约为1×1012dopant atoms per cm3；并且掺杂浓度上，环型接触区83大于环型掺杂区82大于环型轻掺杂区81。
上述实施例的操作方法同前的说明，更明确的说，电压会提供于元件区P2、漏极接触区32、源极接触区62、主体接触掺杂区72、环型接触区83。经测试后，能通过提供700伏特电压，长达1000小时的HTRB测试时。
依据本发明提供的上述半导体元件与其操作方法，当元件呈现关闭状态(off-state)时，能做为高压侧元件，提供较高的耐压稳定性；当元件呈现导通状态(on-state)时，能做为内建靴带式二极管功能的半导体元件，达到整合的功效。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明。任何该领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰。因此本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (22)

1.一种半导体元件，包含：
基板，具有一侧；
深阱区，设置于该基板中的该侧；
元件区，设置于该深阱区中且位于该基板的该侧；
漏极区，设置于该深阱区中且位于该基板的该侧，环绕该元件区；
栅极结构，设置于该基板的该侧上，与该深阱区相邻且环绕该漏极区；
阱区，设置于该深阱区中且位于该基板的该侧，环绕该栅极结构；
源极区，设置于该阱区中且位于该基板的该侧，环绕该栅极结构；
主体接触区，与该源极区分离地设置于该阱区中，环绕该源极区；以及
环型掺杂区，与该深阱区分离地设置于该基板中的该侧，环绕该深阱区。
2.如权利要求1所述的半导体元件，其中该漏极区包含：
漏极轻掺杂区，环绕该元件区；以及
漏极接触区，设置于该漏极轻掺杂区内。
3.如权利要求1所述的半导体元件，还包含：
多个隔离结构，分别设置于该元件区与该漏极区之间。
4.如权利要求1所述的半导体元件，还包含：
隔离深阱区，设置于该基板内与该深阱区相邻，并且位于该元件区相对于该基板的该侧的一另侧。
5.如权利要求1所述的半导体元件，还包含：
上阱区，设置于该深阱区中，并被该栅极结构覆盖。
6.如权利要求5所述的半导体元件，其中该上阱区为环型，环绕该漏极区。
7.如权利要求5所述的半导体元件，其中该上阱区与该栅极结构相接触。
8.如权利要求5所述的半导体元件，其中该上阱区与该栅极结构彼此分离。
9.如权利要求1所述的半导体元件，其中该源极区包含：
源极掺杂区；以及
源极接触区，设置于该源极掺杂区中。
10.如权利要求9所述的半导体元件，其中该源极掺杂区与该源极接触区为环型，环绕该栅极结构。
11.如权利要求1所述的半导体元件，其中该源极区与该主体接触区之间以一隔离结构分离。
12.如权利要求1所述的半导体元件，其中该主体接触区包含：
主体接触轻掺杂区；以及
主体接触掺杂区，设置于该主体接触轻掺杂区中。
13.如权利要求12所述的半导体元件，其中该主体接触轻掺杂区与该主体接触掺杂区为环型，环绕该栅极结构。
14.如权利要求1所述的半导体元件，其中该环型掺杂区包含：
环型轻掺杂区；
环型掺杂区，设置于该环型轻掺杂区中；以及
环型接触区，设置于该环型掺杂区中。
15.如权利要求1所述的半导体元件，还包含：
外围深阱区，设置于该深阱区中，与该阱区相邻且环绕该阱区。
16.如权利要求1所述的半导体元件，其中该半导体元件是一高压侧元件。
17.一种半导体元件的操作方法，其中该半导体元件包含具有一侧的基板、设置于该基板中的该侧的深阱区、设置于该深阱区中且位于该基板的该侧的元件区、设置于该深阱区中位于该基板的该侧且环绕该元件区的漏极区、设置于该基板的该侧上与该深阱区相邻且环绕该漏极区的栅极结构、设置于该深阱区中位于该基板的该侧且环绕该栅极结构的阱区、设置于该阱区中位于该基板的该侧且环绕该栅极结构的源极区、设置于该阱区中与该源极区分离且环绕该源极区的主体接触区，以及设置于该基板中的该侧与该深阱区分离且环绕该深阱区的环型掺杂区，包含以下步骤：
提供该主体接触区与该环型掺杂区一接地电压；
提供该源极区与该栅极结构该接地电压或一第一电源电压；以及
提供该漏极区一第二电源电压或使该漏极区呈现一浮接状态。
18.如权利要求17所述的半导体元件的操作方法，其中提供至该源极区与该栅极结构是该接地电压，而提供至该漏极区是该第二电源电压。
19.如权利要求18所述的半导体元件的操作方法，其中该第二电源电压介于500-800伏特(V)之间。
20.如权利要求17所述的半导体元件的操作方法，其中提供至该源极区与该栅极结构是该第一电源电压，而该漏极区呈现该浮接状态。
21.如权利要求20所述的半导体元件的操作方法，其中该第一电源电压大于0伏特且小于等于30伏特(V)。
22.如权利要求21所述的半导体元件的操作方法，其中该漏极区产生一小于该第一电源电压的正电压。
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