CN105304631B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN105304631B
CN105304631B CN201410376872.8A CN201410376872A CN105304631B CN 105304631 B CN105304631 B CN 105304631B CN 201410376872 A CN201410376872 A CN 201410376872A CN 105304631 B CN105304631 B CN 105304631B
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semiconductor device
doped region
buried layer
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CN105304631A (zh
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张家伟
陈柏安
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Nuvoton Technology Corp
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Abstract

本发明实施例提供了一种半导体装置，该半导体装置包括：P型基板；N型区，接触该P型基板；N+型掺杂区，位于该N型区中；第一P+型掺杂区，位于该N型区中；第二P+型掺杂区，位于该N型区中；P型埋层，位于该N型区下方的该P型基板中并与该N型区接触；以及N型掺杂区，位于该P型埋层与该N型区接触的接触面下方的该P型基板中。

Description

半导体装置
技术领域
本发明提出一种有关于半导体装置，且特别有关于可避免闩锁效应(latch-up)的半导体装置。
背景技术
闩锁(latch-up)效应常见于互补型金属氧化物半导体(Complementary MetalOxide Semiconductor，CMOS)装置中，主要形成原因在于互补型金属氧化物半导体的N型金属氧化物半导体(N-type Metal Oxide Semiconductor，NMOS)与P型金属氧化物半导体(P-type Metal Oxide Semiconductor，PMOS)之间的寄生硅控整流(Silicon ControlledRectifier，SCR)元件被触发。一旦寄生SCR元件被触发，则会产生非预期的大电流，影响半导体装置的正常运作，甚至进一步造成芯片承受过大电流而烧毁。
图1A所示为现有CMOS装置10的示意图。CMOS装置10包括P型基板100、形成于P型基板100中的P型井区102以及N型井区104、形成于P型井区102中的P+型掺杂区110和N+型掺杂区111以及形成于N型井区104中的P+型掺杂区112和N+型掺杂区113。如图1A所示，CMOS装置10装置中存在有一对寄生双极性接面晶体管(Bipolar Junction Transistor，BJT)，即寄生PNP型双极性接面晶体管Q1和寄生NPN型双极性接面晶体管Q2。寄生双极性接面晶体管Q1和Q2、N型井区104的电阻RNW以及P型井区102的电阻RPW构成图1B所示的寄生硅控整流元件140。当寄生硅控整流元件140被触发时，寄生NPN型双极性接面晶体管Q2导通，且寄生NPN型双极性接面晶体管Q2导通后所产生的基极电流会流经寄生PNP型双极性接面晶体管Q1的集电极端，使得Q1的集电极电压上升至超过导通电压，因此导通寄生PNP型双极性接面晶体管Q1，而寄生PNP型双极性接面晶体管Q1导通后所产生的基极电流又会流至寄生NPN型双极性接面晶体管Q2，进而产生更大的电流，此种正反馈的现象造成电流不断增加，最后导致半导体装置的损伤。
以下以功率电路(power circuit)为例说明CMOS装置中的寄生硅控整流元件如何被触发。图2A所示为现有功率电路的电路图。功率电路包括功率PMOS晶体管P1、静电放电(Electrostatic Discharge，ESD)NMOS晶体管N1、电阻R以及输出端VOUT。图2B所示为现有功率电路在短路测试下的电路图，如图2B所示，在短路测试(Short Circuit Test，SCT)中，输出端VOUT连接至接地端，产生负偏压，而此负偏压落在寄生NPN型双极性接面晶体管Q2的发射极端，如图2C所示，使得寄生NPN型双极性接面晶体管Q2导通，产生电流INMOS，并使得寄生PNP型双极性接面晶体管Q1随之导通，因此产生闩锁电流，造成功率电路元件损伤。
综上所述，需要发展可以避免闩锁的半导体装置。
发明内容
本发明一实施例提供一种半导体装置，包括：一P型基板；一N型区，接触该P型基板；一N+型掺杂区，位于该N型区中；一第一P+型掺杂区，位于该N型区中；一第二P+型掺杂区，位于该N型区中；一P型埋层，位于该N型区下方的该P型基板中并与该N型区接触；以及一N型掺杂区，位于该P型埋层与该N型区接触之接触面下方的该P型基板中。
本发明另一实施例提供一种半导体装置，包括：一P型基板；一N型金属氧化物半导体装置；以及一P型金属氧化物半导体装置，包括：一第一N型区，接触该P型基板；一第一N+型掺杂区，位于该第一N型区中；一第一P+型掺杂区，位于该第一N型区中；一第二P+型掺杂区，位于该第一N型区中；一第一栅极结构，位于该第一P+型掺杂区与该第二P+型掺杂区之间的该第一N型区上；一P型埋层，位于该第一N型区下方的该P型基板中并与该第一N型区接触；以及一N型掺杂区，位于该P型埋层与该第一N型区接触的接触面下方的该P型基板中。
附图说明
图1A所示为现有CMOS装置10的示意图。
图1B所示为现有CMOS装置中的寄生SCR元件的电路图。
图2A所示为现有功率电路的电路图。
图2B所示为现有功率电路在短路测试下的电路图。
图2C所示为现有功率电路的寄生SCR元件在短路测试下的电路图。
图3所示为根据本发明一实施例的半导体装置的示意图。
图4所示为根据本发明一实施例的半导体装置的示意图。
图5所示为根据本发明一实施例的半导体装置的示意图。
图6所示为根据本发明一实施例的半导体装置的示意图。
图7所示为根据本发明一实施例的半导体装置的示意图。
附图符号说明：
10～互补型金属氧化物半导体装置；
30、40、50～半导体装置；
100、300～P型基板；
102～P型井区；
104～N型井区；
110、112～P+型掺杂区；
111、113～N+型掺杂区；
140～寄生硅控整流元件；
310～N型掺杂区；
320～P型埋层；
330、337～外延层；
331、333、335～高电压N型井区；
332、334～高电压P型井区；
338～P型基体区；
339～P型重掺杂漏极区；
341、342、343、344、345、346～N+型掺杂区；
351、352、353、354、355～P+型掺杂区；
361、362、363、364、365、366、367、368、369～隔离结构；
371、372、373～栅极结构；
GS1、GS2、GS3～防护环装置；
I_PMOS～隔离式P型金属氧化物半导体装置；
INMOS～电流；
N1～N型金属氧化物半导体晶体管；
NMOS～N型金属氧化物半导体装置；
P1～P型金属氧化物半导体晶体管；
PA1、PA2～路径；
Q1、Q2～寄生双极性接面晶体管；
R、RNW、RPW～电阻；
VDD、VSS～电压；
VOUT～输出端。
具体实施方式
以下说明为本发明的实施例。其目的是要举例说明本发明一般性的原则，不应视为本发明的限制，本发明的范围当以申请专利范围所界定者为准。
值得注意的是，以下所揭露的内容可提供多个用以实践本发明的不同特点的实施例或范例。以下所述的特殊的元件范例与安排仅用以简单扼要地阐述本发明的精神，并非用以限定本发明的范围。此外，以下说明书可能在多个范例中重复使用相同的元件符号或文字。然而，重复使用的目的仅为了提供简化并清楚的说明，并非用以限定多个以下所讨论的实施例以及/或配置之间的关系。此外，以下说明书所述的一个特征连接至、耦接至以及/或形成于另一特征之上等的描述，实际可包含多个不同的实施例，包括所述特征直接接触，或者包含其它额外的特征形成于所述特征之间等等，使得所述特征并非直接接触。
图3所示为根据本发明一实施例的半导体装置30的示意图，半导体装置30包括P型基板300以及隔离式P型金属氧化物半导体(P-type Metal Oxide Semiconductor，PMOS)装置I_PMOS。隔离式P型金属氧化物半导体装置I_PMOS包括N型掺杂区310、P型埋层320、外延层(epitaxial layer)330、高电压N型井区335、P型重掺杂漏极区(P-type Heavily DopedDrain，PHDD)339、N+型掺杂区346、P+型掺杂区354和355、隔离结构365和366以及栅极结构372。在制作工艺方面，首先N型掺杂区310形成于P型基板300中，P型埋层320形成于N型掺杂区310中，接着外延层330形成于P型埋层320上，外延层330可为N型或P型外延层，然后在外延层330中形成高电压N型井区335等特征。高电压N型井区335位于外延层330中，N+型掺杂区346、P+型掺杂区354和P型重掺杂漏极区339位于高电压N型井区335中，P+型掺杂区355位于P型重掺杂漏极区339中，其中P+型掺杂区354为隔离式PMOS装置I_PMOS的源极区，P+型掺杂区355为隔离式PMOS装置I_PMOS的漏极区，N+型掺杂区346为隔离式PMOS装置I_PMOS的基极区。隔离结构365位于N+型掺杂区346以及P+型掺杂区354之间的高电压N型井区335表面，而隔离结构366位于P型重掺杂漏极区339表面并紧邻P+型掺杂区355。栅极结构372位于P+型掺杂区354以及P+型掺杂区355之间并覆盖部分高电压N型井区335以及部分隔离结构366。P型埋层320位于高电压N型井区335下方的N型掺杂区310中并与高电压N型井区335接触，P型埋层320与N型掺杂区310接触的一面的面积大于P型埋层320与高电压N型井区335接触的一面的面积，如图3所示。在一实施例中，N型掺杂区310为一N型埋层，而在另一实施例中，N型掺杂区310为一深N型井区(deep N-type well)。隔离式PMOS装置I_PMOS具有使高电压N型井区335的下表面不直接接触P型基板300的P型埋层320和N型掺杂区310，因此在此说明书中称为隔离式PMOS装置。
图3的隔离式PMOS装置I_PMOS为一隔离式高电压PMOS(High Voltage PMOS，HVPMOS)装置，而本发明另一实施例可提供一隔离式低电压PMOS(Low Voltage PMOS，LVPMOS)装置，隔离式LVPMOS装置与隔离式HVPMOS装置的差别在于隔离式LVPMOS装置没有隔离结构366以及P型重掺杂漏极区339，且栅极结构372位于P+型掺杂区354以及P+型掺杂区355之间并仅覆盖部分高电压N型井区335以导通一通道。
图4所示为根据本发明一实施例的半导体装置40的示意图。半导体装置40为一互补式金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)装置，包括P型基板300、N型金属氧化物半导体(N-type Metal Oxide Semiconductor，NMOS)装置NMOS以及隔离式PMOS装置I_PMOS。在一实施例中，NMOS装置NMOS为普通CMOS装置的NMOS装置，在另一实施例中，NMOS装置NMOS为一横向扩散N型金属氧化物半导体(Laterally DiffusedN-type Metal Oxide Semiconductor，LDNMOS)装置。在NMOS装置NMOS为LDNMOS装置的实施例中，NMOS装置NMOS包括高电压N型井区331、P型基体区338、P+型掺杂区351、N+型掺杂区341、342、343和344、隔离结构361和362以及栅极结构371和373。高电压N型井区331位于外延层330中，P型基体区338位于高电压N型井区331中。P+型掺杂区351位于P型基体区338中，N+型掺杂区342位于P型基体区338中并紧邻P+型掺杂区351的一侧，N+型掺杂区343位于P型基体区338中并紧邻P+型掺杂区351与N+型掺杂区342相邻的一侧的对向侧。N+型掺杂区341和344位于高电压N型井区331中且分别位于P型基体区338的两侧。其中，P+型掺杂区351为NMOS装置NMOS的基极区(bulk area)，N+型掺杂区342和343为NMOS装置NMOS的源极区，而N+型掺杂区341和344为NMOS装置NMOS的漏极区。隔离结构361位于P型基体区338与N+型掺杂区341之间的高电压N型井区331表面，而隔离结构362位于P型基体区338与N+型掺杂区344之间的高电压N型井区331表面。栅极结构371位于N+型掺杂区343与N+型掺杂区344之间并覆盖部分P型基体区338以及部分隔离结构362。栅极结构373位于N+型掺杂区341与N+型掺杂区342之间并覆盖部分P型基体区338以及部分隔离结构361。隔离式PMOS装置I_PMOS与图3一样因此不再复述。
图5所示为根据本发明一实施例的半导体装置50的示意图。半导体装置50包括基底300、NMOS装置NMOS、隔离式PMOS装置I_PMOS以及防护环(guard ring)装置GS1、GS2和GS3。NMOS装置NMOS可为普通CMOS装置的NMOS装置或是LDNMOS装置，在NMOS装置NMOS为LDNMOS装置的实施例中，NMOS装置NMOS包括高电压N型井区331、P型基体区338、P+型掺杂区351、N+型掺杂区341、342、343和344、隔离结构361和362以及栅极结构371和373。高电压N型井区331形成于外延层330(未图示)中，外延层330可为N型或P型外延层，P型基体区338位于高电压N型井区331中。P+型掺杂区351位于P型基体区338中，N+型掺杂区342位于P型基体区338中并紧邻P+型掺杂区351的一侧，N+型掺杂区343位于P型基体区338中并紧邻P+型掺杂区351与N+型掺杂区342相邻的一侧的对向侧。N+型掺杂区341和344位于高电压N型井区331中且分别位于P型基体区338的两侧。其中，P+型掺杂区351为NMOS装置NMOS的基极区，N+型掺杂区342和343为NMOS装置NMOS的源极区，而N+型掺杂区341和344为NMOS装置NMOS的漏极区。隔离结构361位于P型基体区338与N+型掺杂区341之间的高电压N型井区331表面，而隔离结构362位于P型基体区338与N+型掺杂区344之间的高电压N型井区331表面。栅极结构371位于N+型掺杂区343与N+型掺杂区344之间并覆盖部分P型基体区338以及部分隔离结构362，栅极结构373位于N+型掺杂区341与N+型掺杂区342之间并覆盖部分P型基体区338以及部分隔离结构361。
隔离式PMOS装置I_PMOS包括N型掺杂区310、P型埋层320、高电压N型井区335、P型重掺杂漏极区339、N+型掺杂区346、P+型掺杂区354和355、隔离结构365和366以及栅极结构372。高电压N型井区335形成于外延层330(未图示)中，N+型掺杂区346以及P+型掺杂区354位于高电压N型井区335中，P型重掺杂漏极区339位于高电压N型井区335中，且P+型掺杂区355位于P型重掺杂漏极区339中，其中P+型掺杂区354为隔离式PMOS装置I_PMOS的源极区，P+型掺杂区355为隔离式PMOS装置I_PMOS的漏极区，N+型掺杂区346为隔离式PMOS装置I_PMOS的基极区。隔离结构365位于N+型掺杂区346以及P+型掺杂区354之间的高电压N型井区335表面，而隔离结构366位于P+型掺杂区354以及P+型掺杂区355之间的高电压N型井区339表面。栅极结构372位于P+型掺杂区354以及P+型掺杂区355之间并覆盖部分高电压N型井区335以及部分隔离结构366。P型埋层320位于高电压N型井区335下方的N型掺杂区310中并与高电压P型井334以及高电压N型井区335接触，P型埋层320与N型掺杂区310接触的一面的面积大于P型埋层320与高电压N型井区335接触的一面的面积。在一实施例中，N型掺杂区310为一N型埋层，而在另一实施例中，N型掺杂区310为一深N型井区(deep N-type well)。
在制作工艺方面，首先N型掺杂区310形成于P型基板300中，P型埋层320形成于N型掺杂区310中，接着外延层330形成于P型埋层320上，外延层330可为N型或P型外延层，然后在外延层330中形成高电压N型井区331、333和335以及高电压P型井区332和334。
如图5所示，防护环装置GS1位于外延层330中并围绕高电压N型井区335，防护环装置GS1包括位于外延层330(未绘示)中并围绕高电压N型井区335的高电压P型井区334以及位于高电压P型井334区中的P+型掺杂区353，其中高电压P型井区334与P型埋层320接触，例如图5所示，高电压P型井区334的内环部分皆与P型埋层320接触。防护环装置GS2位于外延层330中并围绕防护环装置GS1，防护环装置GS2包括位于外延层330中并围绕高电压P型井区334的高电压N型井区333以及位于高电压N型井区333中的N+型掺杂区345，其中高电压N型井区333与N型掺杂区310接触，例如图5所示，高电压N型井区333的下表面皆与N型掺杂区310接触。防护环装置GS3位于外延层330中并围绕NMOS装置NMOS，防护环装置GS3包括位于外延层330中并围绕高电压N型井区331的高电压P型井区332以及位于高电压P型井区332中的P+型掺杂区352。隔离装置363位于P+型掺杂区352与N+型掺杂区345之间的高电压P型井区332和高电压N型井区333表面并覆盖部分高电压P型井区332以及部分高电压N型井区333。隔离装置369位于N+型掺杂区345与P+型掺杂区353之间的高电压N型井区333和高电压P型井区334表面并覆盖部分高电压N型井区333以及部分高电压P型井区334。隔离装置364位于P+型掺杂区353与N+型掺杂区346之间的高电压P型井区334和高电压N型井区335表面并覆盖部分高电压P型井区334以及部分高电压N型井区335。隔离装置367位于P+型掺杂区355与P+型掺杂区353之间的高电压N型井区335和高电压P型井区334表面并覆盖部分高电压N型井区335以及部分高电压P型井区334。
如上所述，图5的隔离式PMOS装置I_PMOS为一隔离式HVPMOS装置，但本发明并不局限于此。举例而言，本发明另一实施例可提供一隔离式LVPMOS装置，隔离式LVPMOS装置与隔离式HVPMOS装置的差别在于隔离式LVPMOS装置没有隔离结构366以及P型重掺杂漏极区339，且栅极结构372位于P+型掺杂区354以及P+型掺杂区355之间并仅覆盖部分高电压N型井区335以导通一通道。
图6所示为根据本发明一实施例的半导体装置60的示意图。半导体装置60包括基底300、NMOS装置NMOS1、隔离式PMOS装置I_PMOS1以及防护环装置GS1、GS2和GS3。图6的半导体装置60与图5的半导体装置50的差异在于高电压N型井区331形成于N型外延层337中时其下表面并未接触基板300，高电压N型井区333形成于N型外延层337中时其下表面并未接触N型掺杂区310，且高电压N型井区335形成于N型外延层337中时其下表面并未接触P型埋层320。在制作工艺方面，首先N型掺杂区310形成于P型基板300中，P型埋层320形成于N型掺杂区310中，接着N型外延层337形成于P型埋层320上，然后在N型外延层337中形成高电压N型井区331、333和335以及高电压P型井区332和334，其中高电压N型井区331、333和335的深度小于N型外延层337的厚度，而高电压P型井区332和334的深度等于N型外延层337的厚度使得高电压P型井区332接触基板300而高电压P型井区334接触N型掺杂区310和P型埋层320。由于高电压N型井区331、333和335是由同一道制作工艺形成于N型外延层337中，因此高电压N型井区331、333和335下方的N型外延层337厚度皆相同。半导体装置60的其余部分皆与半导体装置50类似，因此不再复述。
图7所示为根据本发明一实施例的半导体装置70的示意图。半导体装置70包括基底300、NMOS装置NMOS2、隔离式PMOS装置I_PMOS2以及防护环装置GS1、GS2和GS3。图7的半导体装置70与图5的半导体装置50的差异在于半导体装置70没有高电压N型井区331、333和335。在制作工艺方面，首先N型掺杂区310形成于P型基板300中，P型埋层320形成于N型掺杂区310中，接着N型外延层337形成于P型埋层320上，然后在N型外延层337中形成高电压P型井区332和334，其中高电压P型井区332和334的深度等于N型外延层337的厚度使得高电压P型井区332接触基板300而高电压P型井区334接触N型掺杂区310和P型埋层320。由高电压P型井区332和334所划分出来的外延层337各个区域可发挥与图5的高电压N型井区331、333和335相似的功效。半导体装置70的其余部分皆与半导体装置50类似，因此不再复述。
在图5的实施例的另一变化实施例中，可省略外延层330而直接在基板300中形成高电压N型井区331、333和335以及高电压P型井区332和334。
在上述实施例中，各隔离结构可为场氧化层(FOX)结构或浅沟渠隔离(STI)结构。须注意的是，在上述实施例中虽以不同标号表示各隔离结构，但各隔离结构并不限定为分离的隔离结构而可为一相连隔离结构的一部分。例如一环状隔离结构可包括隔离结构364以及隔离结构367，此环状隔离结构位于高电压N型井区335与高电压P型井区334交界处的外延层330上并覆盖部分高电压N型井区335以及部分高电压P型井区334。
在上述实施例中，如图3～图7所示，N型掺杂区310位于P型埋层320与高电压N型井区335或N型外延层337接触的接触面下方的P型基板300中，且P型埋层320的上表面与P型基板300以及N型掺杂区310的上表面切齐，但本发明并不局限于此。举例而言，在一实施例中，P型埋层320会向上扩散而使得P型埋层320的一部分突出于P型基板300以及N型掺杂区310的表面之外，也就是说，P型埋层320的一部分位于N型掺杂区310中而P型埋层320的其他部分不位于N型掺杂区310中。
如上列所述，本发明的一实施例是在PMOS装置下方配置了P型埋层和N型掺杂区以形成隔离式HVPMOS装置。由于若在NMOS装置侧增加上述制作工艺可能造成NMOS装置的参数改变，例如阈值电压Vt、饱和电流IdSAT、漏极-源极击穿电压BVDss和导通电阻Ron等，因此本发明的一实施例在PMOS装置侧增加上述制作工艺相较于在NMOS装置侧增加上述制作工艺可避免增加调整工艺参数的时间与成本，也可避免降低静电放电能力。除此之外，如图5所示，对于水平路径PA1而言，由防护环GS1、GS2和GS3的设置可以消除水平SCR路径，而对于垂直路径PA2而言，由在PMOS装置下方增加P型埋层320和N型掺杂区310可以消除垂直SCR路径，因此，不论水平路径上或垂直路径上皆可消除SCR路径，达成避免闩锁的半导体装置。
以上所述为实施例的概述特征。所属技术领域中的技术人员应可以轻而易举地利用本发明为基础设计或调整以实行相同的目的和/或达成此处介绍的实施例的相同优点。所属技术领域中的技术人员也应了解相同的配置不应背离本发明的精神与范围，在不背离本发明的精神与范围下他们可做出各种改变、取代和交替。说明性的方法仅表示示范性的步骤，但这些步骤并不一定要以所表示的顺序执行。可另外加入、取代、改变顺序和/或消除步骤以视情况而作调整，并与所揭露的实施例精神和范围一致。

Claims (18)

1.一种半导体装置，其特征在于，该半导体装置包括：
一P型基板；
一N型区，接触该P型基板；
一N+型掺杂区，位于该N型区中；
一第一P+型掺杂区，位于该N型区中；
一第二P+型掺杂区，位于该N型区中；
一P型埋层，位于该N型区下方的该P型基板中并与该N型区接触；
一N型掺杂区，位于该P型埋层与该N型区接触的接触面下方的该P型基板中；以及
一栅极结构，位于该第一P+型掺杂区与该第二P+型掺杂区之间的该N型区上；
其中，该P型埋层与该N型掺杂区接触的一面的面积大于该P型埋层与该N型区接触的一面的面积。
2.如权利要求1所述的半导体装置，其特征在于，该P型埋层的一部分位于该N型掺杂区中，该P型埋层的其他部分不位于该N型掺杂区中。
3.如权利要求1所述的半导体装置，其特征在于，该N型掺杂区为一N型埋层或一深N型井区。
4.如权利要求1所述的半导体装置，其特征在于，该半导体装置还包括：
一外延层，形成于该P型埋层上；
其中该N型区为一高电压N型井区且位于该外延层中。
5.如权利要求1所述的半导体装置，其特征在于，该N型区包括：
一N型外延层，形成于该P型埋层上；以及
一高电压N型井区，位于该N型外延层中，该高电压N型井区不接触该P型埋层；
其中，该第一P+型掺杂区、第二P+型掺杂区以及N+型掺杂区均是形成在高电压N型井区中。
6.如权利要求1所述的半导体装置，其特征在于，该N型区为一N型外延层或一高电压N型井区。
7.如权利要求1所述的半导体装置，其特征在于，该半导体装置还包括：
一第一隔离结构，位于该N+型掺杂区与该第一P+型掺杂区之间的该N型区表面。
8.如权利要求1所述的半导体装置，其特征在于，该半导体装置还包括：
一P型重掺杂漏极区，位于该N型区中，其中该第二P+型掺杂区位于该P型重掺杂漏极区中；以及
一第二隔离结构，位于该P型重掺杂漏极区的表面并紧邻该第二P+型掺杂区，其中该栅极结构的一部分覆盖该第二隔离结构。
9.一种半导体装置，其特征在于，该半导体装置包括：
一P型基板；
一N型金属氧化物半导体装置；以及
一P型金属氧化物半导体装置，包括：
一第一N型区，接触该P型基板；
一第一N+型掺杂区，位于该第一N型区中；
一第一P+型掺杂区，位于该第一N型区中；
一第二P+型掺杂区，位于该第一N型区中；
一第一栅极结构，位于该第一P+型掺杂区与该第二P+型掺杂区之间的该第一N型区上；
一P型埋层，位于该第一N型区下方的该P型基板中并与该第一N型区接触；以及
一N型掺杂区，位于该P型埋层与该第一N型区接触的接触面下方的该P型基板中；
其中，该P型埋层与该N型掺杂区接触的一面的面积大于该P型埋层与该第一N型区接触的一面的面积。
10.如权利要求9所述的半导体装置，其特征在于，该N型掺杂区为一N型埋层或一深N型井区。
11.如权利要求9所述的半导体装置，其特征在于，该P型金属氧化物半导体装置还包括：
一第一隔离结构，位于该第一N+型掺杂区与该第一P+型掺杂区之间的该第一N型区表面。
12.如权利要求9项所述的半导体装置，其特征在于，该P型金属氧化物半导体装置还包括：
一P型重掺杂漏极区，位于该第一N型区中，其中该第二P+型掺杂区位于该P型重掺杂漏极区中；以及
一第二隔离结构，位于该P型重掺杂漏极区的表面并紧邻该第二P+型掺杂区，其中该第一栅极结构的一部分覆盖该第二隔离结构。
13.如权利要求9所述的半导体装置，其特征在于，该N型金属氧化物半导体装置为一横向扩散N型金属氧化物半导体装置。
14.如权利要求9所述的半导体装置，其特征在于，该N型金属氧化物半导体装置包括：
一第二N型区，接触该P型基板；
一P型基体区，位于该第二N型区中；
一第三P+型掺杂区，位于该P型基体区中；
一第二N+型掺杂区，位于该P型基体区中并紧邻该第三P+型掺杂区的一侧；
一第三N+型掺杂区，位于该P型基体区中并紧邻该第三P+型掺杂区的另一侧；
一第四N+型掺杂区，位于该第二N型区中；
一第五N+型掺杂区，位于该第二N型区中；以及
一第二栅极结构，位于该第三N+型掺杂区与该第四N+型掺杂区之间的该第二N型区上，并覆盖部分该P型基体区。
15.如权利要求14所述的半导体装置，其特征在于，该N型金属氧化物半导体装置还包括：
一第三隔离结构，位于该P型基体区与该第五N+型掺杂区之间的该第二N型区表面；以及
一第四隔离结构，位于该P型基体区与该第四N+型掺杂区之间的该第二N型区表面，其中该第二栅极结构覆盖部分该第四隔离结构。
16.如权利要求9所述的半导体装置，其特征在于，该半导体装置包括：
一第一防护环装置，接触该P型基板并围绕该第一N型区；
一第二防护环装置，接触该P型基板并围绕该第一防护环装置；以及
一第三防护环装置，接触该P型基板并围绕该N型金属氧化物半导体装置。
17.如权利要求16所述的半导体装置，其特征在于，该P型埋层与一第一高电压P型井区接触。
18.如权利要求16所述的半导体装置，其特征在于，该N型掺杂区与一第三N型区接触。
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