CN108847423B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN108847423B
CN108847423B CN201810538418.6A CN201810538418A CN108847423B CN 108847423 B CN108847423 B CN 108847423B CN 201810538418 A CN201810538418 A CN 201810538418A CN 108847423 B CN108847423 B CN 108847423B
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region
well region
oxide layer
substrate
doping type
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CN108847423A (zh
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王猛
杜益成
喻慧
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Hangzhou Silergy Semiconductor Technology Ltd
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Hangzhou Silergy Semiconductor Technology Ltd
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Priority to CN201810538418.6A priority Critical patent/CN108847423B/zh
Publication of CN108847423A publication Critical patent/CN108847423A/zh
Priority to TW108106302A priority patent/TWI787470B/zh
Priority to US16/416,420 priority patent/US11942540B2/en
Priority to US16/417,813 priority patent/US11031497B2/en
Priority to US17/308,205 priority patent/US11581433B2/en
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Publication of CN108847423B publication Critical patent/CN108847423B/zh
Priority to US18/095,641 priority patent/US11967644B2/en
Priority to US18/581,728 priority patent/US20240194782A1/en
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Abstract

本申请公开了一种半导体器件及其制造方法，该制造方法包括：在第一掺杂类型的衬底中形成具有与第一掺杂类型相反的第二掺杂类型的第一阱区，第一阱区围绕衬底的第一区域；在第一区域中形成具有第二掺杂类型的源区与漏区；以及在衬底中形成具有第二掺杂类型的埋层，埋层位于第一区域的下方，与第一阱区相连；其中，埋层与第一阱区共同包围第一区域。该半导体器件及其制造方法的有益效果是，可以省去制作结深较大的阱区的步骤，实现了LDMOS工艺与CMOS等其他工艺结合的目的，还可以同时提升器件的击穿电压BV和导通电阻Rdson的性能。

Description

半导体器件及其制造方法
技术领域
本公开涉及半导体器件制造领域，更具体地，涉及一种半导体器件及其制造方法。
背景技术
功率开关可以是半导体器件，包括金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)和绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,IGBT)等。横向扩散金属氧化物半导体(LaterallyDiffused Metal Oxide Semiconductor,LDMOS)被广泛地用在开关型调节器中。
图1示出了现有技术中的LDMOS结构示意图。
如图1所示，掺杂类型为N型的阱区102制作在衬底101中，体区109与漂移区110均位于阱区102中，源区115形成在体区109中，漏区116形成在漂移区110中。由于漂移区110的存在，漏极116可以承受高电压。因此，LDMOS晶体管具有大驱动电流、低导通电阻和高击穿电压的优点，广泛地用于开关型调节器。
然而，现有技术中的阱区102通常需要较大的结深，因此，阱区102需要单独完成制作，不能与CMOS等其他工艺结合。
此外，由于为了降低LDMOS的导通电阻Rdson，漂移区110的掺杂浓度不能过低，而为了增加LDMOS的击穿电压BV，漂移区110的掺杂浓度又不能过高，这使得现有的LDMOS器件的击穿电压BV和导通电阻Rdson的性能不能均得到最大的提升。
发明内容
有鉴于此，本公开提供了一种半导体器件及其制造方法，可以省去制作结深较大的阱区的步骤，实现了LDMOS工艺与CMOS等其他工艺结合的目的，还可以同时提升器件的击穿电压BV和导通电阻Rdson的性能。
根据本公开的一方面，提供了一种半导体器件的制造方法，包括：在第一掺杂类型的衬底中形成具有与第一掺杂类型相反的第二掺杂类型的第一阱区，所述第一阱区围绕所述衬底的第一区域；在所述第一区域中形成具有第二掺杂类型的源区与漏区；以及在所述衬底中形成具有第二掺杂类型的埋层，所述埋层位于所述第一区域的下方，与所述第一阱区相连；其中，所述埋层与所述第一阱区共同包围所述第一区域。
优选地，在形成所述漏区的步骤之前，还包括在所述第一区域中形成具有第二掺杂类型的漂移区，其中，所述漏区位于所述漂移区中。
优选地，在形成所述源区的步骤之前，还包括在所述第一区域中形成具有第一掺杂类型的体区，其中，所述源区位于所述漂移区中。
优选地，在形成所述漂移区的步骤之前，还包括在所述第一区域中形成具有第一掺杂类型的第一深阱区，其中，所述漂移区和所述体区位于所述第一深阱区中。
优选地，其中，所述第一深阱区的掺杂浓度峰值位于所述漂移区的下方。
优选地，在形成所述漏区的步骤之前，还包括在所述衬底上形成栅极结构，其中，至少部分所述第一深阱区位于所述源区与所述漏区之间的所述栅极结构的下方。
优选地，形成所述栅极结构的步骤包括：在所述第一区域上形成高压漏氧化层；在所述衬底上形成栅氧化层，所述高压漏氧化层与所述栅氧化层相连；以及在所述高压漏氧化层与所述栅氧化层上形成栅极导体，所述栅极导体位于所述源区与所述漏区之间。
优选地，形成所述栅极结构的步骤还包括在所述栅极导体两端的侧壁上形成侧墙。
优选地，在形成所述体区的步骤之后，还包括在所述体区中形成具有第一掺杂类型的体区掺杂区，所述体区掺杂区与所述源区相连。
优选地，所述第一掺杂类型为选自N型和P型之一，所述第二掺杂类型为N型和P型的另一种。
优选地，还包括在所述衬底上形成NMOS结构、PMOS结构以及PAMOS结构中的一种或者组合。
优选地，所述NMOS结构、所述PMOS结构以及所述PAMOS结构中的至少一个具有形成于所述衬底中的第二掺杂类型的第二阱区，所述第一阱区和所述第二阱区同步形成。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底，其为第一掺杂类型；第一阱区，位于所述衬底中，并围绕所述衬底的第一区域，所述第一阱区为与第一掺杂类型相反的第二掺杂类型；源区与漏区，均位于所述第一区域中，所述源区与所述漏区为第二掺杂类型；以及埋层，位于所述衬底中，并位于所述第一区域的下方，与所述第一阱区相连，所述埋层为第二掺杂类型；其中，所述埋层与所述第一阱区共同包围所述第一区域。
优选地，还包括漂移区，位于所述第一区域中，所述漂移区为第二掺杂类型，其中，所述漏区位于所述漂移区中。
优选地，还包括体区，位于所述第一区域中，所述体区为第一掺杂类型，其中，所述源区位于所述漂移区中。
优选地，还包括第一深阱区，位于所述第一区域中，所述第一深阱区为第一掺杂类型，其中，所述漂移区和所述体区位于所述第一深阱区中。
优选地，所述第一深阱区的掺杂浓度峰值位于所述漂移区的下方。
优选地，还包括栅极结构，位于所述衬底上，其中，至少部分所述第一深阱区位于所述源区与所述漏区之间的所述栅极结构的下方。
优选地，所述栅极结构包括：高压漏氧化层，位于所述第一区域上；栅氧化层，位于在所述衬底上，与所述高压漏氧化层相连；以及栅极导体，位于所述高压漏氧化层与所述栅氧化层上，所述栅极导体位于所述源区与所述漏区之间。
优选地，所述栅极结构还包括侧墙，位于所述栅极导体两端的侧壁上。
优选地，还包括体区掺杂区，位于所述体区中与所述源区相连，所述体区掺杂区为第一掺杂类型。
优选地，所述第一阱区和所述埋层构成具有第一掺杂类型的腔体，所述腔体嵌在所述衬底中。
优选地，所述第一掺杂类型为选自N型和P型之一，所述第二掺杂类型为N型和P型的另一种。
优选地，还包括位于所述衬底上的NMOS结构、PMOS结构以及PAMOS结构中的一种或者组合。
根据本公开实施例的半导体器件的结构及其制造方法，通过在将源漏区制作在衬底的第一区域中，并在衬底中形成共同包围第一区域的第一阱区与埋层，本公开的第一阱区与埋层取代了现有技术中结深较大的阱区，从而达到了第一阱区与CMOS等其他器件的阱区共同形成的目的，实现了工艺上的结合。
根据本公开实施例的半导体器件的结构及其制造方法，通过在衬底中形成掺杂类型与漂移区不同的第一深阱区，调整第一深阱区的掺杂浓度分布，将第一深阱区的掺杂浓度峰值集中分布在漂移区下方，折中优化了半导体器件的低压侧结构的击穿电压BV与导通电阻Rdson。
根据本公开实施例的半导体器件的结构及其制造方法，通过调节漂移区的掺杂浓度，进一步折中优化了击穿电压BV与导通电阻Rdson。
根据本公开实施例的半导体器件的结构及其制造方法，仅通过在衬底的第一区域下方形成与第一阱区相连的埋层，构成了包围第一区域的腔体，从而形成了半导体器件的高压侧结构，此外，利用第一阱区将埋层与衬底上表面连通，将半导体器件的高压侧结构于低压侧结构隔开，在不影响半导体器件的导通电阻Rdson与击穿电压BV的前提下，保证了高压侧结构的正常工作。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单介绍，显而易见地，下面的描述中的附图仅涉及本公开的一些实施例，而非对本公开的限制。
图1示出了现有技术中的LDMOS结构示意图。
图2A示出了本公开第一实施例的半导体器件的结构示意图。
图2B示出了本公开第一实施例的半导体器件的制造方法流程示意图。
图3A至图3I示出了图2B中各步骤的半导体器件的结构示意图。
图4示出了本公开第二实施例的半导体器件的结构示意图。
图5A至图5I示出了图4中本公开第二实施例的半导体器件在制造时各步骤的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整的描述。显然所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
图2A示出了本公开第一实施例的半导体器件的结构示意图。
如图2A所示，本公开第一实施例的半导体器件包括：高压侧结构与低压侧结构，高压侧结构与低压侧结构共用衬底100与栅氧化层420，其中，高压侧结构包括：衬底100、第一阱区210、第一深阱区221、埋层230、第一体区311、第一漂移区312、第一高压漏氧化层411、栅氧化层420、第一栅极导体431、第一侧墙441、第一体区掺杂区511、第一源区512、第一漏区513以及第一轻掺杂漏区(未示出)。低压侧结构包括：衬底100、第二深阱区222、第二体区321、第二漂移区322、栅氧化层420、第二高压漏氧化层412、第二栅极导体432、第二侧墙442、第二体区掺杂区521、第二源区522、第二漏区523以及第二轻掺杂漏(未示出)。其中，衬底100、第一深阱区221、第二深阱区222、第一体区311、第二体区321、第一体区掺杂区511以及第二体区掺杂区521为第一掺杂类型，第一阱区210、埋层230、第一漂移区312、第二漂移区322、第一源区512、第一漏区513、第二源区522以及第二漏区523为第二掺杂类型，第一掺杂类型与第二掺杂类型相反。第一掺杂类型为选自N型和P型之一，第二掺杂类型为N型和P型的另一种。
在本实施例中，衬底100的掺杂类型为P型掺杂。
第一阱区210位于衬底100中，并围绕位衬底100中的第一区域10，第一阱区210的一端与埋层230相连，另一端延伸至衬底100表面。阱区210的掺杂类型为N型掺杂，掺杂物包括磷。
埋层230位于衬底100中，并位于第一区域10下方且不与第一深阱区221接触。埋层230的掺杂类型为N型掺杂，掺杂物包括磷。其中，埋层230与第一阱区210共同包围第一区域10，形成一个N型掺杂的腔体结构，嵌入在衬底100中。
第一深阱区221与第二深阱区222位于衬底100中，其中，第一深阱区221位于第一区域10中。第一深阱区221与第二深阱区222的掺杂类型为P型掺杂，掺杂物包括硼。
第一体区311与第一漂移区312位于第一深阱区221中，且至少部分第一深阱区221位于第一体区311与第一漂移区312之间，第二体区321与第二漂移区322位于第二深阱区222中，且至少部分第二深阱区222位于第二体区321与第二漂移区322之间。第一体区311与第二体区321的掺杂类型为P型掺杂，掺杂物包括硼。第一漂移区312与第二漂移区322的掺杂类型为N型掺杂，掺杂物包括磷。
第一体区掺杂区511与第一源区512相连并位于第一体区311中，第一漏区513并位第一漂移区312中，第二体区掺杂区521与第二源区522相连并位于第二体区321中，第二漏区523并位第二漂移区322中，第一轻掺杂漏区与第二轻掺杂漏分别位于第一漏区513与第二漏区523处。第一体区掺杂区511与第二体区掺杂区521的掺杂类型为P型掺杂，第一源区512、第一漏区513第二源区522、第二漏区523第一轻掺杂漏区以及第二轻掺杂漏的掺杂类型为N型掺杂。其中，第一轻掺杂漏区与第二轻掺杂漏的掺杂浓度小于第一漏区513与第二漏区523的掺杂浓度。
栅氧化层420位于衬底100上，第一高压漏氧化层411位于第一漂移区312上与栅氧化层420相连，第一栅极导体431位于高压漏氧化层411与栅氧化层420上，第一栅极导体431的一端延伸至第一源区512与第一体区掺杂区511相连一侧的相对一侧的上方，另一端延伸至第一漂移区312上方，第一侧墙441位于第一栅极导体431两端的侧壁上。其中，至少部分第一深阱区221位于第一源区512与第一漏区513之间的栅极结构的下方，进一步地，至少部分第一深阱区221位于第一体区311与第一漂移区312之间的栅氧化层420下方。第二高压漏氧化层412位于第二漂移区322上与栅氧化层420相连，第二栅极导体432位于高压漏氧化层412与栅氧化层420上，第二栅极导体432的一端延伸至第二源区522与第二体区掺杂区521相连一侧的相对一侧的上方，另一端延伸至第二漂移区322上方，第二侧墙442位于第二栅极导体432两端的侧壁上。其中，至少部分第一深阱区221位于第一源区512与第一漏区513之间的栅极结构的下方，进一步地，至少部分第一深阱区221位于第一体区311与第一漂移区312之间的栅氧化层420下方。第一栅极导体431与第二栅极导体432的材料包括多晶硅。
在本实施例的半导体器件中，高压侧结构与低压侧结构的不同之处在于，高压侧结构比低压侧结构多一层埋层230，即高压侧结构的第一阱区210与埋层230共同包围第一区域10，就可以构成高压侧结构，引入N型掺杂的埋层230可以在不影响器件的击穿电压BV与导通电阻Rdson的前提下，保证高压侧结构的正常工作。此外，埋层230的引入可以基于之前的BCD工艺架构并用很小的额外成本来进一步优化器件的击穿电压BV与导通电阻Rdson。具体地，通过在半导体器件中增加P型的第一深阱区221与第二深阱区222，可以使第一深阱区221与第二深阱区222的浓度峰值分布集中在第一漂移区312与第二漂移区322下方，从而可以对低压侧结构的击穿电压BV与导通电阻Rdson进行折中优化。进一步地，通过调节第一深阱区221与第二深阱区222的浓度分布，可以在第一漂移区312于第二漂移区322下方提供充足的P型掺杂浓度，从而提升半导体器件的击穿电压BV，进一步地，还可以提升第一漂移区312于第二漂移区322的掺杂浓度，对半导体器件的击穿电压BV与导通电阻Rdson再一次进行折中优化。
图2B示出了本公开第一实施例的半导体器件的制造方法流程示意图，图3A至图3I示出了图2B中各步骤的半导体器件的结构示意图。下面将结合图2B至图3I对本公开第一实施例的半导体器件的制造方法进行具体说明。
在步骤S01中，在衬底中形成N阱区/P阱区。具体地，如图3A所示，通过离子注入的方式在衬底100中形成第一阱区210。第一阱区210围绕衬底100的第一区域10，第一阱区210还用于接出在后续步骤中形成的埋层。其中，衬底100的掺杂类型为P型掺杂。第一阱区210的掺杂类型为N型掺杂，掺杂物包括磷。在一些其他实施例中，第一阱区210的掺杂类型为P型掺杂。
在步骤S02中，在衬底中形成深P阱区。具体地，如图3B所示，通过离子注入的方式在衬底100中形成第一深阱区221与第二深阱区222，其中，第一深阱区221位于第一区域10中，通过调节第一深阱区221与第二深阱区222的掺杂浓度来提升本实施例半导体器件的击穿电压BV。其中，第一深阱区221与第二深阱区222的掺杂类型为P型掺杂，掺杂物包括硼。
在步骤S03中，在衬底上形成场氧化层。具体地，利用硅局部氧化隔离(LocalOxidation of Silicon，LOCOS)技术在衬底上形成场氧化层。
在步骤S04中，在深P阱区中形成漂移区。具体地，如图3C所示，通过离子注入的方式分别在第一深阱区221与第二深阱区222中形成第一漂移区321与第二漂移区322，通过调节第一漂移区321与第二漂移区322的掺杂浓度来实现本实施例半导体器件击穿电压BV与导通电阻Rdson的折中优化。其中，第一漂移区321与第二漂移区322的掺杂类型为N型掺杂，掺杂物包括磷。
在步骤S05中，在衬底上生成高压漏氧化层。具体地，如图3D所示，用掩模版限定第一高压漏极区域与第二高压漏极区域，并通过LOCOS技术在高压漏极区域形成第一高压漏氧化层411与第二高压漏氧化层412。
在步骤S06中，在衬底中形成埋层。具体地，如图3E所示，通过离子注入的方式在衬底100中的第一区域10形成埋层230，埋层230位于第一深阱区221下方且不与第一深阱区221接触。第一阱区210环绕第一深阱区221，第一阱区210的一端与埋层230相连，另一端延伸至衬底100表面。埋层230的掺杂类型为N型掺杂，掺杂物包括磷。
在步骤S07中，在衬底上形成栅氧化层。具体地，如图3F所示，在衬底100上形成栅氧化层420，栅氧化层420分别与第一高压漏氧化层411与第二高压漏氧化层412相连。
在步骤S08中，在栅氧化层与高压漏氧化层上形成多晶硅栅。具体地，如图3G所示，在栅氧化层420以及与之相连的第一高压漏氧化层411上形成第一栅极导体431，在栅氧化层420以及与之相连的第二高压漏氧化层412上形成第二栅极导体432，其中，第一栅极导体431与第二栅极导体432的材料包括多晶硅栅。
在步骤S09中，在深P阱区中形成体区。具体地，如图3H所示，通过离子注入的方式分别在第一深阱区221中形成第一体区311、在第二深阱区222中形成第二体区321，使得至少部分第一深阱区221位于第一体区311与第一漂移区312之间，至少部分第二深阱区222位于第二体区321与第二漂移区322之间，在第一体区311与第二体区321的掺杂浓度决定了本实施例半导体器件的阈值。其中，第一体区311与第二体区321的掺杂类型为P型掺杂，掺杂物包括硼。
在步骤S010中，在体区中形成轻掺杂漏区。具体的，如图3H所示，利用第一高压漏氧化层411与第一栅极导体431作为硬掩模并通过离子注入的方式在本实施例半导体器件的漏区处形成轻掺杂漏区。其中，轻掺杂漏区的的掺杂类型为N型掺杂。
在步骤S011中，在多晶硅栅侧壁形成侧墙。具体的，如图3I所示，在第一栅极导体431的侧壁形成第一侧墙441，在第二栅极导体432的侧壁形成第二侧墙442。
在步骤S012中，分别在体区与漂移区中形成源区与漏区。具体的，如图3I所示，利用第一高压漏氧化层411、第一栅极导体431以及第一侧墙441作为硬掩模并通过离子注入的方式分别在第一体区311形成相连的第一体区掺杂区511与一第源区512，并在第一漂移区312处形成在处形成第一漏区513。利用第二高压漏氧化层412、第二栅极导体432以及第二侧墙442作为硬掩模并通过离子注入的方式分别在第二体区321形成相连的第二体区掺杂区521与二第源区522，并在第二漂移区322处形成在处形成第二漏区523。
图4示出了本公开第二实施例的半导体器件的结构示意图。
本公开第二实施例的半导体器件包括：N型LDMOS、NMOS、PMOS以及PAMOS。在本实施例中，衬底100的掺杂类型为P型掺杂。
NLDMOS部分结构与第一实施例基本相同，此处不再赘述，不同之处在于，在第一阱区210中形成隔离区501。
NMOS包括：衬底100、第一N阱区223(第二阱区)、第一P阱区330、栅氧化层420、第三栅极导体433、第三体区掺杂区531、第三源区532以及第三漏区533。
第一N阱区223位于衬底100中，第一P阱区330位于第一N阱区223中，第三体区掺杂区531、第三源区532以及第三漏区533位于第一P阱区330中，栅氧化层420位于衬底100上，第三栅极导体433位于第三源区532与第三漏区533之间的栅氧化层420上。
PMOS包括：衬底100、第二N阱区224(第二阱区)、栅氧化层420、第四栅极导体434、第四体区掺杂区541、第四源区542以及第四漏区543。
第二N阱区224位于衬底100中，第四体区掺杂区541、第四源区542以及第四漏区543位于第二N阱区224中，栅氧化层420位于衬底100上，第四栅极导体434位于第四源区542与第四漏区543之间的栅氧化层420上。
PAMOS包括：衬底100、第三N阱区225(第二阱区)、第二P阱区350、第三高压漏氧化层415、栅氧化层420、第五栅极导体435、第五体区掺杂区551、第五源区552以及第五漏区553。
第三N阱区225位于衬底100中，第二P阱区350位于第三N阱区225中，第五体区掺杂区551与第五源区552位于第三N阱区225中，第五漏区553第二P阱区350中。栅氧化层420位于衬底100上，第三高压漏氧化层415位于第二P阱区350上并与栅氧化层420相连，第五栅极导体435位于第三高压漏氧化层415与栅氧化层420上，第三高压漏氧化层415的一端延伸至第五源区552上方，另一端延伸至第二P阱区350上方，其中，至少部分第三N阱区225位于第五源区552与第五漏区553之间的栅极结构的下方。
在本实施例中，第一阱区210的结深与第一N阱区223、第二N阱区224以及第三N阱区225的结深大致相同，因此可以在一道工序中共同形成。
图5A至图5H示出了图4中本公开第二实施例的半导体器件在制造时各步骤的结构示意图。
如图5A所示，通过离子注入的方式在衬底100中形成第一阱区210、第一N阱区223、第二N阱区224以及第三N阱区225，通过离子注入的方式在第一N阱区223中形成第一P阱区330、在第三N阱区225中形成第二P阱区350。第一阱区210围绕衬底100的第一区域10，第一阱区210还用于接出在后续步骤中形成的埋层。其中，衬底100的掺杂类型为P型掺杂。第一阱区210的掺杂类型为N型掺杂，掺杂物包括磷。在一些其他实施例中，第一阱区210的掺杂类型为P型掺杂。
如图5B所示，通过离子注入的方式在衬底100中形成第一深阱区221与第二深阱区222，其中，第一深阱区221位于第一区域10中，通过调节第一深阱区221与第二深阱区222的掺杂浓度来提升本实施例半导体器件的击穿电压BV。其中，第一深阱区221与第二深阱区222的掺杂类型为P型掺杂，掺杂物包括硼。之后，在衬底100上形成场氧化层(未示出)。具体地，利用LOCOS技术在衬底100上形成场氧化层。
如图5C所示，通过离子注入的方式分别在第一深阱区221与第二深阱区222中形成第一漂移区321与第二漂移区322，通过调节第一漂移区321与第二漂移区322的掺杂浓度来实现本实施例半导体器件击穿电压BV与导通电阻Rdson的折中优化。其中，第一漂移区321与第二漂移区322的掺杂类型为N型掺杂，掺杂物包括磷。
如图5D所示，用掩模版限定第一高压漏极区域、第二高压漏极区域以及第三高压漏极区域，并通过LOCOS技术在高压漏极区域形成第一高压漏氧化层411、第二高压漏氧化层412以及第三高压漏氧化层415。
如图5E所示，通过离子注入的方式在衬底100中形成埋层230，埋层230位于第一深阱区221下方且不与第一深阱区221接触。第一阱区210环绕第一深阱区221，第一阱区210的一端与埋层230相连，另一端延伸至衬底100表面。埋层230的掺杂类型为N型掺杂，掺杂物包括磷。
如图5F所示，在衬底100上形成栅氧化层420，栅氧化层420分别与第一高压漏氧化层411、第二高压漏氧化层412以及第三高压漏氧化层415相连。
如图5G所示，在栅氧化层420以及与之相连的第一高压漏氧化层411上形成第一栅极导体431，在栅氧化层420以及与之相连的第二高压漏氧化层412上形成第二栅极导体432，在第一P阱区330上方的栅氧化层420上第三栅极导体433，在第二N阱区224上方的栅氧化层420上第四栅极导体434，在栅氧化层420以及与之相连的第三高压漏氧化层451上形成第五栅极导体435，其中，第一栅极导体431、第二栅极导体432、第三栅极导体433、第四栅极导体434以及第五栅极导体435的材料包括多晶硅栅。
如图5H所示，通过离子注入的方式分别在第一深阱区221中形成第一体区311、在第二深阱区222中形成第二体区321，使得至少部分第一深阱区221位于第一体区311与第一漂移区312之间，至少部分第二深阱区222位于第二体区321与第二漂移区322之间，在第一体区311与第二体区321的掺杂浓度决定了本实施例半导体器件的阈值。其中，第一体区311与第二体区321的掺杂类型为P型掺杂，掺杂物包括硼。
如图5H所示，利用第一高压漏氧化层411与第一栅极导体431作为硬掩模并通过离子注入的方式在本实施例半导体器件的漏区处形成轻掺杂漏区。其中，轻掺杂漏区的的掺杂类型为N型掺杂。
如图5I所示，在第一栅极导体431的侧壁形成第一侧墙441，在第二栅极导体432的侧壁形成第二侧墙442。
如图5I所示，利用第一高压漏氧化层411、第一栅极导体431以及第一侧墙441作为硬掩模并通过离子注入的方式分别在第一体区311形成相连的第一体区掺杂区511与一第源区512，并在第一漂移区312处形成在处形成第一漏区513，还在第一阱区210中形成隔离区501。利用第二高压漏氧化层412、第二栅极导体432以及第二侧墙442作为硬掩模并通过离子注入的方式分别在第二体区321形成相连的第二体区掺杂区521与二第源区522，并在第二漂移区322处形成在处形成第二漏区523。利用第三栅极导体532为硬掩模在第一P阱区330中形成第三体区掺杂区531、第三源区532以及第三漏区533。利用第四栅极导体542为硬掩模在第二N阱区224中形成第四体区掺杂区541、第四源区542以及第四漏区543。
利用第五高压漏氧化层415、第五栅极导体451作为硬掩模并通过离子注入的方式分别在第三N阱区225中形成第五体区掺杂区551与第五源区552，并在第二P阱区中形成在处形成第五漏区513。
根据本公开第一与第二实施例的半导体器件的结构及其制造方法，通过在将源漏区制作在衬底的第一区域中，并在衬底中形成共同包围第一区域的第一阱区与埋层，本公开的第一阱区与埋层取代了现有技术中结深较大的阱区，从而达到了第一阱区与CMOS等其他器件的阱区共同形成的目的，实现了工艺上的结合。
根据本公开第一与第二实施例的半导体器件的结构及其制造方法，通过在衬底中形成掺杂类型与漂移区不同的第一深阱区，调整第一深阱区的掺杂浓度分布，将第一深阱区的掺杂浓度峰值集中分布在漂移区下方，折中优化了半导体器件的低压侧结构的击穿电压BV与导通电阻Rdson。
根据本公开第一与第二实施例的半导体器件的结构及其制造方法，通过调节漂移区的掺杂浓度，进一步折中优化了击穿电压BV与导通电阻Rdson。
根据本公开第一与第二实施例的半导体器件的结构及其制造方法，仅通过在衬底的第一区域下方形成与第一阱区相连的埋层，构成了包围第一区域的腔体，从而形成了半导体器件的高压侧结构，即高压侧结构仅比低压侧结构多出一层埋层，此外，利用第一阱区将埋层与衬底上表面连通，将半导体器件的高压侧结构于低压侧结构隔开，在不影响半导体器件的导通电阻Rdson与击穿电压BV的前提下，保证了高压侧结构的正常工作。
以上所述仅为本公开的优选实施例，并不用于限制本公开，对于本领域技术人员而言，本公开可以有各种改动和变化。凡在本公开的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (22)

1.一种半导体器件的制造方法，半导体器件包括高压侧结构与低压侧结构，其中，形成高压侧结构的方法包括：
在第一掺杂类型的衬底中形成具有与第一掺杂类型相反的第二掺杂类型的第一阱区，所述第一阱区围绕所述衬底的第一区域；
在所述第一区域中形成具有第一掺杂类型的第一深阱区；
在所述第一深阱区中形成具有第二掺杂类型的漂移区；
在所述衬底中形成具有第二掺杂类型的埋层，所述埋层位于所述第一区域的下方，所述埋层与所述第一阱区相连，且所述埋层不与所述第一深阱区接触，所述埋层与所述第一阱区共同包围所述第一区域，所述第一阱区将所述埋层与所述衬底上表面连通，将半导体器件的高压侧结构与低压侧结构隔开；
在所述第一深阱区中形成具有第一掺杂类型的体区；
分别在所述体区和所述漂移区中形成具有第二掺杂类型的源区和漏区。
2.根据权利要求1所述的制造方法，所述方法还包括：在形成所述漂移区之前且在形成所述第一深阱区之后，在所述衬底上形成场氧化层。
3.根据权利要求2所述的制造方法，其中，所述方法还包括：在形成所述漂移区之后且在形成所述埋层之前，在所述第一区域上形成漏氧化层。
4.根据权利要求3所述的制造方法，其中，所述方法还包括：在形成所述体区之前且在形成所述埋层之后，在所述衬底上形成栅氧化层，所述漏氧化层与所述栅氧化层相连。
5.根据权利要求4所述的制造方法，其中，所述方法还包括：在形成所述栅氧化层之后，在所述漏氧化层与所述栅氧化层上形成栅极导体，所述栅极导体位于所述源区与所述漏区之间。
6.根据权利要求5所述的制造方法，其中，所述方法还包括：在形成所述源区和漏区之前且在形成所述体区之后，在所述体区中形成具有第一掺杂类型的体区掺杂区，所述体区掺杂区与所述源区相连。
7.根据权利要求6所述的制造方法，其中，所述方法还包括：在形成所述体区掺杂区之后，在所述栅极导体两端的侧壁上形成侧墙。
8.根据权利要求7所述的制造方法，其中，所述高压侧结构与所述低压侧结构共用衬底与栅氧化层。
9.根据权利要求1-8任一所述的制造方法，其中，所述第一掺杂类型为选自N型和P型之一，所述第二掺杂类型为N型和P型的另一种。
10.根据权利要求9所述的制造方法，还包括在所述衬底上形成NMOS结构、PMOS结构以及至少包括第二掺杂类型的第二阱区的MOS结构中的一种或者组合；其中，所述MOS结构还包括：第二P阱区、第三高压漏氧化层、栅氧化层、第五栅极导体、第五体区掺杂区、第五源区以及第五漏区；
所述第二阱区位于所述衬底中，所述第二P阱区、所述第五体区掺杂区、第五源区均位于所述第二阱区中，第五漏区位于所述第二P阱区中；
所述栅氧化层位于所述衬底上，所述第三高压漏氧化层位于所述第二P阱区上并与所述栅氧化层相连，所述第五栅极导体位于所述第三高压漏氧化层与所述栅氧化层上。
11.根据权利要求10所述的制造方法，其中，所述NMOS结构、所述PMOS结构以及所述至少包括第二掺杂类型的第二阱区的MOS结构中的至少一个具有形成于所述衬底中的第二掺杂类型的第二阱区，
所述第一阱区和所述第二阱区同步形成。
12.一种半导体器件，包括高压侧结构与低压侧结构，所述高压侧结构包括：
衬底，其为第一掺杂类型；
第一阱区，位于所述衬底中，并围绕所述衬底的第一区域，所述第一阱区为与第一掺杂类型相反的第二掺杂类型；
第一深阱区，位于所述第一区域中，具有第一掺杂类型；
漂移区，位于所述第一深阱区中，所述漂移区为第二掺杂类型；
埋层，位于所述衬底中，并位于所述第一区域的下方，与所述第一阱区相连，所述埋层为第二掺杂类型；且埋层不与第一深阱区接触，所述埋层与所述第一阱区共同包围所述第一区域，所述第一阱区将埋层与衬底上表面连通，将半导体器件的高压侧结构与低压侧结构隔开；
体区，位于所述第一深阱区中，具有第一掺杂类型；
源区与漏区，分别位于所述体区与所述漂移区中，所述源区与所述漏区均为第二掺杂类型。
13.根据权利要求12所述的半导体器件，其中，所述第一深阱区的掺杂浓度峰值位于所述漂移区下方。
14.根据权利要求12所述的半导体器件，其中，还包括漏氧化层，所述漏氧化层位于所述第一区域中。
15.根据权利要求14所述的半导体器件，其中，还包括栅氧化层，所述栅氧化层位于所述衬底上，所述漏氧化层与所述栅氧化层相连。
16.根据权利要求15所述的半导体器件，其中，还包括栅极导体，所述栅极导体至少覆盖所述漏氧化层与所述栅氧化层的连接处，并位于所述源区与所述漏区之间。
17.根据权利要求16所述的半导体器件，其中，还包括体区掺杂区，所述体区掺杂区位于所述体区中，具有第一掺杂类型。
18.根据权利要求17所述的半导体器件，其中，还包括侧墙，所述侧墙位于所述栅极导体的两端。
19.根据权利要求18所述的半导体器件，其中，所述高压侧结构与所述低压侧结构共用衬底与栅氧化层。
20.根据权利要求12所述的半导体器件，其中，所述第一阱区和所述埋层构成具有第一掺杂类型的腔体，所述腔体嵌在所述衬底中。
21.根据权利要求12-20任一所述的半导体器件，其中，所述第一掺杂类型为选自N型和P型之一，所述第二掺杂类型为N型和P型的另一种。
22.根据权利要求21所述的半导体器件，还包括位于所述衬底上的NMOS结构、PMOS结构以及至少包括第二掺杂类型的第二阱区的MOS结构中的一种或者组合；
其中，所述MOS结构还包括：第二P阱区、第三高压漏氧化层、栅氧化层、第五栅极导体、第五体区掺杂区、第五源区以及第五漏区；
所述第二阱区位于所述衬底中，所述第二P阱区、所述第五体区掺杂区、第五源区均位于所述第二阱区中，第五漏区位于所述第二P阱区中；
所述栅氧化层位于所述衬底上，所述第三高压漏氧化层位于所述第二P阱区上并与所述栅氧化层相连，所述第五栅极导体位于所述第三高压漏氧化层与所述栅氧化层上。
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