TWI596740B - 整合齊納二極體及場效應電晶體的半導體元件及其製備方法 - Google Patents

整合齊納二極體及場效應電晶體的半導體元件及其製備方法 Download PDF

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TWI596740B
TWI596740B TW105105076A TW105105076A TWI596740B TW I596740 B TWI596740 B TW I596740B TW 105105076 A TW105105076 A TW 105105076A TW 105105076 A TW105105076 A TW 105105076A TW I596740 B TWI596740 B TW I596740B
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field effect
effect transistor
semiconductor device
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秀明土子
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萬國半導體股份有限公司
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Description

整合齊納二極體及場效應電晶體的半導體元件及其製備方法
本發明主要涉及半導體元件，更確切地說，是關於整合齊納二極體及半導體功率元件的半導體元件及其製備方法。
第4圖表示啟動電路，用於在整流交流信號中檢測上電和掉電。該電路包括一個常開型電晶體(例如JFET)，串聯到齊納二極體ZD1上。齊納二極體允許電流正向流動，與傳統二極體的方式相同，但是當電壓高於特定值(即所謂的齊納電壓時)也允許電流反向流動。
第4圖所示的啟動電路用於檢測漏極處的輸入電壓，而產生檢測信號。在該電壓探測器中，齊納二極體ZD1具有一個陰極，其連接到接收輸入電壓的端，結型場效應電晶體(JFET)的漏極作為輸入端連接到齊納二極體ZD1的陽極，源極作為輸出端，柵極作為控制端，電阻器Rgs連接在JFET的源極和柵極之間，開關M2連接在JFET的柵極和接地端之間，並且由來自JFET控制塊的控制信號控制。當開關M2斷開時，電壓探測器不會探測輸入端的輸入電壓。當開關M2接通時， 如果探測端的輸入電壓高於齊納二極體ZD1的擊穿電壓的話，JFET工作，產生電流ID，穿過JFET，從漏極流向源極。由於開關接通，JFET的柵極接地，因此電流ID將流經電阻器Rgs，以增大JFET的源柵電壓，即JFET的柵源電壓降低。JFET的柵源電壓VGS將等於JFET的夾斷電壓，因此電阻器Rgs上的電壓降將等於夾斷電壓。
當開關M2接通時，如果輸入電壓低於齊納二極體的擊穿電壓，那麼將沒有電流ID流經JFET，並且由於JFET的柵極接地，因此JFET的源極和柵極處於相同的電勢，也就是說電阻器Rgs上的電壓降為零。由於JFET的漏電流幾乎為零，因此當探測輸入電壓Vin時，電壓探測器幾乎沒有功率損耗。
如上所述，依據電阻器Rgs上的電壓降，電壓探測器可以決定輸入電壓Vin高於或低於齊納二極體ZD1的擊穿電壓，以致於探測信號可以來自電阻器Rgs上的電壓降。如果JFET使用開關M2接地，那麼JFET的源極電壓可以直接用作探測信號。在該電壓探測器中，齊納二極體ZD1的擊穿電壓用作探測的參考電壓，可藉由選擇或調節齊納二極體ZD1的擊穿電壓，或者增加串聯更多的齊納二極體來改變參考電壓。
正是在這樣的背景下，提出了本發明的技術方案以及實施例。
本發明的目的在於提出一種整合齊納二極體及場效應電晶體的半導體元件，以改善現有技術中的一個或多個問題。
本發明的一個方面在於提出一種半導體元件，包括：一個 或多個齊納二極體；一個場效應電晶體，具有一個漏極，漏極與一個或多個齊納二極體串聯；其中一個或多個齊納二極體和場效應電晶體，是在相同的P-型半導體基板中藉由多個摻雜區製成的，並且被一個穿通阻擋區隔開；以及一個第一N-型區，形成在一個或多個齊納二極體下方。
較佳地，其中半導體基板包括一個形成在P-型基板上的P-型外延層。
較佳地，其中一個或多個齊納二極體包括一個形成在P-型外延層中的N-型區，以及一個形成在N-型區附近且位於P-型外延層中的P-型區。
較佳地，其中形成在一個或多個齊納二極體下方的第一N-型區，是一個形成在P-型基板和P-型外延層之間的N-型掩埋層。
較佳地，其中一個或多個二極體包括一個形成在基板中的N-型區，以及一個形成在N-型區附近且位於基板層中的P-型區。
較佳地，其進一步包括一個形成在一個或多個齊納二極體和場效應電晶體之間的第一N-型區上方的半導體基板中的隔離結構。
較佳地，其中隔離結構包括一個N-型阱和一個形成在N-型阱上方的高壓N-阱，其中高壓N-阱比N-型阱具有更重的N-型摻雜。
較佳地，其中一個或多個齊納二極體包括相互串聯的第一齊納二極體和第二齊納二極體。
較佳地，其中每個第一齊納二極體和第二齊納二極體均包括一個形成在P-型外延層中的N-型區，以及一個形成在N-型區附近且位於P-型外延層中的P-型區。
較佳地，其進一步包括第一隔離結構，形成在第一齊納二 極體、第二齊納二極體與場效應電晶體之間的第一N-型區上方的半導體基板中，以及第二隔離結構，形成在第一齊納二極體與第二齊納二極體之間的第一N-型區上方的半導體基板中。
較佳地，其中多個摻雜區包括多個中心區域，一個或多個齊納二極體的陰極位於多個中心區域的中心處。
較佳地，其中多個摻雜區包括一個最外面的區域，該最外面的區域為場效應電晶體的源極。
較佳地，其中場效應電晶體為耗盡型電晶體。
較佳地，其中場效應電晶體為結型場效應電晶體。
較佳地，其進一步包括第二N-型區，形成在場效應電晶體下方的基板中，其中第一N-型區和第二N-型區被穿通阻擋區隔開。
本發明的另一個方面在於提出一種用於製備半導體元件的方法，包括：製備一個場效應電晶體，其具有一個漏極，該漏極與一個或多個齊納二極體串聯；一個或多個齊納二極體和場效應電晶體，是在相同的P-型半導體基板中藉由多個摻雜區製成的，並且被一個穿通阻擋區隔開；製備一個形成在一個或多個齊納二極體下方的第一N-型區。
較佳地，其進一步包括製備一個形成在場效應電晶體下方基板中的第二N-型區，其中第一N-型區和第二N-型區被穿通阻擋區隔開。
閱讀以下詳細說明的實施例並參照各種圖式，本發明的這些特點和優勢對於本領域的技術人員來說，無疑將顯而易見。
100‧‧‧元件
102‧‧‧基板
104‧‧‧外延層
106、137、187‧‧‧N-型掩埋層、NBL
108、108A、112、112A‧‧‧N-型阱
109、109A‧‧‧高壓N-型阱、HVNW
110、110A‧‧‧齊納二極體
114、114A‧‧‧N+區、陰極
122、122A、132‧‧‧P-型阱
124、124A‧‧‧P+區、陽極
126‧‧‧P-型本體區
126A‧‧‧P-型阱區
130‧‧‧電晶體
134‧‧‧柵極、多晶矽層
135‧‧‧耗盡層、耗盡型注入層
136‧‧‧摻雜區、重摻雜N+區
138、184‧‧‧高壓N-型阱、HVNW
150‧‧‧結型區
152‧‧‧穿通阻擋區
160、170‧‧‧金屬場板
161‧‧‧金屬結構
180‧‧‧電晶體、JFET
181‧‧‧柵極
182‧‧‧源極
183‧‧‧頂部柵極
185‧‧‧N-通道
186‧‧‧摻雜區、漏極接頭
第1A圖表示依據本發明的一個實施例，為含有耗盡型金屬氧化物場效應電晶體(MOSFET)和齊納二極體的元件的示意圖。
第1B圖表示依據本發明的一個實施例，將齊納二極體與耗盡型金屬氧化物場效應電晶體(MOSFET)整合在一起的元件的部分剖面圖。
第1C圖表示依據本發明的另一個實施例，為含有結型場效應電晶體(JFET)和齊納二極體的元件的示意圖。
第1D圖表示依據本發明的另一個實施例，將齊納二極體與結型場效應電晶體整合在一起的元件的部分剖面圖。
第2A圖表示依據本發明的又一個實施例，為含有電晶體和齊納二極體的元件的示意圖。
第2B圖表示依據本發明的又一個實施例，將齊納二極體與電晶體整合在一起的元件的部分剖面圖。
第3A圖至第3C圖為圖1所示元件的俯視圖。
第4圖表示一種傳統的啟動電路。
在以下詳細說明中，參照圖式，表示本發明可以實施的典型實施例。就這一點而言，根據圖中所示方向，使用“頂部”、“底部”、“正面”、“背面”、“向前”、“向後”等方向術語。由於本發明實施例的零部件，可以位於各種不同方向上，因此所用的方向術語僅用於解釋說明，不用於局限。應明確，無需偏離本發明的範圍，就能實現其他實施例，做出結構或邏輯上的變化。因此，以下詳細說明不用於局限， 本發明的範圍應由申請專利範圍限定。
簡介
近年來，在一個單獨晶片上多種功能的組合，智慧功率技術已獲得越來越多的重視。啟用微型系統設計，包括功率電晶體的診斷和保護功能，從而提高了功率驅動器用於不同應用的耐用性和可靠性。
本發明的各個方面涉及具有耗盡型電晶體與一個或多個齊納二極體整合在一個單獨晶片上的元件，例如用於啟動電路。
元件結構
除非另有說明，否則圖式是不按比例的。
第4圖所示類型的傳統啟動電路使用多個零部件。依據本發明的各個方面，齊納二極體和耗盡型MOSFET或FJET可以整合在一個晶片上。
第1A圖表示依據本發明的一個實施例，含有帶電晶體的齊納二極體元件的示意圖。元件100包括一個齊納二極體110和一個常開型場效應電晶體130，提供相對於輸入電壓(例如漏極電壓)的穩定電流。如第1A圖所示，齊納二極體110的陽極連接到電晶體130的漏極。電晶體130可以是耗盡型電晶體，也就是常開型元件，可以藉由柵極電勢增大或降低漏極電流。藉由柵極和源極電勢中的任意一個或兩者兼具，切斷漏極電流。作為示例，但不作為局限，電晶體130可以選擇結型柵極場效應電晶體(JFET)。齊納二極體110的齊納電壓用於控制輸入到電晶體130的電壓。當輸入電壓低於齊納二極體110的擊穿電壓時，電晶體130失效，沒有電流流經它。當輸入電壓高於擊穿電壓時，電晶體130傳導電流。雖然第1A圖只顯示了一個齊納二極體110連接 到電晶體130上，但是要注意的是可以串聯兩個或多個齊納二極體，如第2A圖所示，以便增大齊納電壓，作為耗盡電壓或啟動電壓，以便接通所連的電晶體130。
第1B圖表示依據本發明的一個實施例，在一個單獨晶片上，將齊納二極體與電晶體整合在一起的元件的部分剖面圖。元件100包括一個第一導電類型的基板102(例如P基板)。基板102可以摻雜P-型摻雜物，例如硼。在P-型基板102上方，製備一個第一導電類型的(可選)外延層104(例如P型外延層)。在一個示例中，外延層104可以藉由本領域中眾所周知的外延生長方法製備。基板102和外延層104為輕摻雜。在一些實施例中，它們的摻雜濃度範圍為1014/cm3至1016/cm3左右。外延層104的厚度範圍為2微米至10微米左右。
齊納二極體110和耗盡型電晶體130形成在P-型基板102上方的P-型外延層104中。相對於齊納二極體110來說，N-型阱112和P-型阱122可以在P-型外延層104中。N+區114作為二極體的陰極，包圍著N-型阱112中。P+區124作為二極體的陽極，包圍著P-型阱122的P-型本體區126中。這些區域都可以藉由本領域中眾所周知的離子注入方法製成。N-型阱112和P-型阱122的摻雜濃度，決定了齊納二極體110的開啟電壓。N+區114的重摻雜程度高於N-型阱112。N-型阱112和P-型阱122之間的微小裂縫(例如零點幾微米至幾微米)會使擊穿電壓增大。在一些實施例中，N+區114的摻雜濃度範圍為1019/cm3至1021/cm3左右，N-型阱112的摻雜濃度約為1016/cm3至1018/cm3左右。另外，P+區124的重摻雜程度高於P-型本體區126和P-型阱122。P+區幾乎飽和。在一些實施例中，P+區124的摻雜濃度範圍為1019/cm3至1020/cm3左右。P-型本體區126和P-型阱122的摻雜濃度約為1016/cm3至1018/cm3左右。
相對於電晶體130來說，P-型阱132作為電晶體130的本體，位於P-型外延層104中。P+本體傳感和N+源極區形成在本體132中。P+本體傳感的摻雜濃度範圍為1019/cm3至1020/cm3左右，N+源極的摻雜濃度範圍為1019/cm3至1021/cm3左右。P-型阱132的重摻雜程度高於P-型基板102。多晶矽層作為電晶體130的柵極134，位於P-型外延層104的頂面上方。柵極134藉由柵極絕緣層(例如氧化物)與外延層104電絕緣。另外，該元件包括場氧化物(圖中沒有表示出)，例如按照慣例，對於柵極和N+/P+注入區來說在有源區上方。為了表示清楚和簡便，已略去場氧化物的區域。然而，含有場氧化物的元件在本發明的範圍內。
高壓N-型阱(HVNW)138位於P-型外延層104中，提供漏極延伸區。輕摻雜的HVNW 138的摻雜濃度範圍為1015/cm3至1017/cm3左右。耗盡型注入層135位於柵極下方以及部分P-型阱132和HVNW 138上方。耗盡層135使MOSFET電晶體130成為一個常開型元件。藉由控制相對於本體電勢的柵極或源極電勢，可以關閉導通狀態。重摻雜N+區136包圍著HVNW 138中，作為電晶體130的漏極。
另外，含有穿通阻擋區152的結型區150位於齊納二極體110和電晶體130之間。穿通阻擋區主要是基板102和外延層104的區域，該區域的P-型重摻雜程度小於P-型阱122和P+區124、126。在結型區150的邊緣處，提供隔離結構。可以藉由調節穿通阻擋區152的寬度來改變元件的穿通電壓。穿通電壓最好大於齊納二極體110的開啟電壓。如果穿通電壓“低於”齊納擊穿電壓，齊納二極體110會在擊穿前將電流傳導至電晶體130。這會使齊納不起作用。
依據本發明的各個方面，為了將齊納二極體110和電晶體 130整合在同一個基板元件中，包括配置一個隔離結構，作為齊納二極體的陽極和基板102之間的穿通阻擋區。隔離結構包括N-型掩埋層(NBL)106、在NBL 106上方的N-型阱108，以及在N-型阱108上方的高壓N-型阱(HVNW)109。HVNW 109的摻雜濃度範圍為1015/cm3至1017/cm3左右。NBL 106形成在P-型基板102和P-型外延層104之間。NBL 106終止了從P-型阱122或P-型本體區126到P-型基板102的穿通。如第1B圖所示，NBL 106形成在二極體區域和結型區150的邊緣中，以弛豫電場。類似的N-型阱108和(可選)NBL 137形成在摻雜區136下方，作為電晶體130的漏極。如果電晶體130邊緣的電場不是必須弛豫的話，那麼可以省去NBL 137。
對於極高壓(例如大於500V)元件來說，NBL 137有助於弛豫場，但是較低壓的元件則不需要。
此外，元件100包括第一和第二金屬場板160和170，用於電連接和遮罩。按照慣例，金屬場板160、170可以藉由一個或多個絕緣層(例如氧化層)與不需要相互電接觸的以及元件的其餘部分電絕緣。
第1C圖和第1D圖表示一個示例，其中齊納二極體110與JFET 180整合在相同的基板上。在第1D圖所示的示例中，JFET 180為N-通道JFET。然而，本發明的各個方面並不局限於這種配置，第1D圖中的齊納二極體110具有與第1B圖所示的齊納二極體110相同的基板。JFET 180包括底部柵極181、源極182、浮動頂部柵極183以及作為延伸漏極184的高壓N-阱(HVNW)。底部柵極181包括一個P+區，位於元件外邊緣處的P-型阱內。底部柵極181電連接到地電壓，如第1C圖所示。源極182形成在外延層104中，從底部柵極181和頂部柵極183之間的N-阱內的N+區開始。源極182電連接到頂部金屬場板170作為 源極電極和場板的那部分。頂部柵極183包括一個P+區，位於次重摻雜的P-型阱內，次重摻雜的P-型阱形成在作為頂部柵極電極的那部分金屬場板160下方的HVNW 184中。柵極電壓可以藉由電連接(圖中沒有表示出)載入至頂部柵極183。當柵極電壓載入至頂部柵極時，N-通道185形成在頂部柵極183下方的HVNW 184中。可使用與第1B圖所示類似的結構，使JFET 180與齊納二極體隔離。
類似的N-型阱108和(可選的)NBL 187形成在作為JFET 180漏極接頭的摻雜區186下方。如果電晶體180邊緣處的電場不是必須弛豫的話，可以省去NBL 187。漏極接頭186可以藉由一部分底部金屬場板160，連接到齊納二極體110的陽極124。
如上所述，第2B圖表示依據本發明的一個實施例，將兩個齊納二極體110、110A與電晶體整合在一起的一部分元件。與第1B圖類似。第1B圖和第2B圖的共同元件用相同或類似的參考數字表示。除了齊納二極體110之外，第2B圖所示元件包括帶有耗盡型電晶體130的第二個齊鈉二極體110A。由於帶有第1B圖所示的元件，齊納二極體110、110A和電晶體130形成在P-型基板102上方的P-型外延層104中。相對於第1A圖來說，可以按照上述方式，配置齊納二極體110。與之類似，第二個齊納二極體110A包括形成在P-型外延層104中的N-型阱112A和P-型阱122A。N+區114A作為齊鈉二極體110A的陰極，P+區124A作為齊鈉二極體110A的陽極，N+區114A和P+區124A包圍在P-型阱122A中的P-型阱區126A中。這些區域可以藉由本領域中眾所周知的離子注入方法製成，相對於第1A圖中相應的區域來說，摻雜濃度在上述範圍內。齊納二極體110的陽極124可以連接到第二個齊納二極體110的陰極114A，例如金屬結構161可以是與金屬場板160相同金屬層的一部分。齊鈉二極體110、110A可以藉由具有N-型掩埋層 (NBL)106的隔離結構隔開，在二極體和獨立的隔離結構下方，含有N-型區108、108A，在NBL 106上方，以及HVNW 109、109A，在N-型阱上方。由於第1B圖所示元件，NBL 106形成在P-型基板102和P-型外延層104之間。N-型阱108A和HVNW 109A形成在兩個齊鈉二極體110、110A之間，另一個N-型阱108和HVNW 109形成在第二個齊鈉二極體110A和電晶體130之間。
要注意的是，可以類似地修改第1D圖所示的元件，按照與第2B圖所示的方式，引入兩個齊納二極體。
第3A圖至第3C圖表示依據本發明的一個方面，為第1B圖所示元件的俯視圖。第3A圖為第1B圖所示元件的俯視圖，表示P-型外延層104和柵極134中的結構。第3B圖為第1B圖所示元件的俯視圖，表示金屬場板160和170。第3C圖為第1B圖所示元件的俯視圖，表示NBL 106和P-外延層104。從這些附圖中可見，第1B圖中的元件在齊納二極體110的陰極114周圍迴圈對稱，陰極114連接到漏極電勢。元件的其他區域形成在同心環中，陰極114位於中心處。第1C圖和第2B圖所示元件類似地圓形對稱。雖然此處表示的是圓形對稱元件，本領域的技術人員將會使用其他類型的對稱。
上述類型的元件可以藉由耗盡型元件或結型場效應電晶體(JFET)製備，含有與一個或多個齊納二極體串聯的漏極，藉由製備多個所示類型的摻雜區，在相同的P-型半導體基板中被穿通阻擋區域隔開。關鍵步驟是在一個或多個齊納二極體下方的基板中製備第一N-型掩埋層106，以及在耗盡型元件或JFET電晶體130下方的基板中製備(可選的)第二N-型掩埋層137，第一和第二N-型區被穿通阻擋區152隔開。根據所用的摻雜技術，各種摻雜區可以任意合適的順序製備。例如，使 用高能離子注入，在一個或多個齊納二極體110、110A下方製備N-型掩埋區106、137。還可選擇，在它們上方製備摻雜區之前，製備N-型掩埋區106、137。在這種情況下，N-型掩埋區可以直接位於P-型基板102中，可以省去外延層104。在這種配置中，上述形成在外延層104中的摻雜區可以直接形成在基板102中。還可選擇，在製備外延層104之前，藉由額外的傳統方法注入，在基板102中製備N-型區。然後可以藉由加熱方法，使摻雜物垂直擴散到外延層中。
雖然上述示例是關於形成在P-型基板上的元件，但是本發明的各個方面也包括P-型和N-型轉換後的配置。
因此，本發明的範圍不應局限於以上說明，而應由申請專利範圍及其全部等效內容決定。本方法中所述步驟的順序並不用於局限進行相關步驟的特定順序的要求。任何可選元件(無論首選與否)，都可與其他任何可選元件(無論首選與否)組合。在申請專利範圍中，除非特別聲明，否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個專案的數量。除非在指定的申請專利範圍中用“意思是”特別指出，否則所附的申請專利範圍應認為是包括意義及功能的限制。雖然特定的方法步驟可能以一定順序出現在申請專利範圍中，但是除非申請專利範圍中指明一定的順序，否則無需按特定順序進行步驟。
100‧‧‧元件
102‧‧‧基板
104‧‧‧外延層
106、137‧‧‧N-型掩埋層
108、112‧‧‧N-型阱
109‧‧‧高壓N-型阱
110‧‧‧齊納二極體
114‧‧‧陰極
122、132‧‧‧P-型阱
124‧‧‧陽極
126‧‧‧P-型本體區
130‧‧‧電晶體
134‧‧‧柵極
135‧‧‧耗盡層
136‧‧‧摻雜區
138‧‧‧高壓N-型阱
150‧‧‧結型區
152‧‧‧穿通阻擋區
160、170‧‧‧金屬場板

Claims (31)

  1. 一種半導體元件，其包括：一個或多個齊納二極體；以及一個場效應電晶體，具有一個漏極，該漏極與一個或多個該齊納二極體串聯；其中一個或多個該齊納二極體和該場效應電晶體，是在相同的P-型半導體基板中藉由多個摻雜區製成的，並且被一個穿通阻擋區隔開；以及一個第一N-型區，形成在一個或多個該齊納二極體下方，以終止從齊納二極體的P-型阱區或P-型本體區向P-型半導體基板的穿通；其中，一個或多個該齊納二極體包括一個形成在該半導體基板中的N-型區，以及一個形成在N-型區附近且位於該半導體基板中的P-型區。
  2. 如申請專利範圍第1項所述之半導體元件，其中該P-型半導體基板包括一個形成在P-型基板上的P-型外延層。
  3. 如申請專利範圍第2項所述之半導體元件，其中一個或多個該齊納二極體包括一個形成在該P-型外延層中的N-型區，以及一個形成在N-型區附近且位於該P-型外延層中的P-型區。
  4. 如申請專利範圍第2項所述之半導體元件，其中形成在一個或多個該齊納二極體下方的該第一N-型區，是一個形成在該P-型基板和該P-型外延層之間的N-型掩埋層。
  5. 如申請專利範圍第1項所述之半導體元件，其中該場效應 電晶體為耗盡型電晶體。
  6. 如申請專利範圍第1項所述之半導體元件，其中該場效應電晶體為結型場效應電晶體。
  7. 如申請專利範圍第1項所述之半導體元件，其進一步包括一個第二N-型區，形成在該場效應電晶體下方的該P-型半導體基板中，其中該第一N-型區和該第二N-型區被該穿通阻擋區隔開。
  8. 一種半導體元件，其包括：一個或多個齊納二極體；以及一個場效應電晶體，具有一個漏極，該漏極與一個或多個該齊納二極體串聯；其中一個或多個該齊納二極體和該場效應電晶體，是在相同的P-型半導體基板中藉由多個摻雜區製成的，並且被一個穿通阻擋區隔開；一個第一N-型區，形成在一個或多個該齊納二極體下方，以終止從齊納二極體的P-型阱區或P-型本體區向P-型半導體基板的穿通；以及一個隔離結構，形成在一個或多個該齊納二極體和該場效應電晶體之間的該第一N-型區上方的該半導體基板中；其中該隔離結構包括一個N-型阱和一個形成在N-型阱上方的高壓N-阱，其中高壓N-阱比N-型阱具有更重的N-型摻雜。
  9. 如申請專利範圍第8項所述之半導體元件，其中該P-型半導體基板包括一個形成在P-型基板上的P-型外延層。
  10. 如申請專利範圍第9項所述之半導體元件，其中一個或多個該齊納二極體包括一個形成在該P-型外延層中的N-型區，以及一個形成在N-型區附近且位於該P-型外延層中的P-型區。
  11. 如申請專利範圍第9項所述之半導體元件，其中形成在一個或多個該齊納二極體下方的該第一N-型區，是一個形成在該P-型基板和該P-型外延層之間的N-型掩埋層。
  12. 如申請專利範圍第8項所述之半導體元件，其中該場效應電晶體為耗盡型電晶體。
  13. 如申請專利範圍第8項所述之半導體元件，其中該場效應電晶體為結型場效應電晶體。
  14. 如申請專利範圍第8項所述之半導體元件，其進一步包括一個第二N-型區，形成在該場效應電晶體下方的該P-型半導體基板中，其中該第一N-型區和該第二N-型區被該穿通阻擋區隔開。
  15. 一種半導體元件，其包括：一個或多個齊納二極體；以及一個場效應電晶體，具有一個漏極，該漏極與一個或多個該齊納二極體串聯；其中一個或多個該齊納二極體和該場效應電晶體，是在相同的P-型半導體基板中藉由多個摻雜區製成的，並且被一個穿通阻擋區隔開；以及 一個第一N-型區，形成在一個或多個該齊納二極體下方，以終止從齊納二極體的P-型阱區或P-型本體區向P-型半導體基板的穿通；其中一個或多個該齊納二極體包括相互串聯的第一齊納二極體和第二齊納二極體。
  16. 如申請專利範圍第15項所述之半導體元件，其中每一個該第一齊納二極體和該第二齊納二極體均包括一個形成在該P-型外延層中的N-型區，以及一個形成在N-型區附近且位於該P-外延層中的P-型區。
  17. 如申請專利範圍第15項所述之半導體元件，其進一步包括一個第一隔離結構，形成在該第一齊納二極體、該第二齊納二極體與該場效應電晶體之間的該第一N-型區上方的該P-型半導體基板中，以及一個第二隔離結構，形成在該第一齊納二極體與該第二齊納二極體之間的該第一N-型區上方的該P-型半導體基板中。
  18. 如申請專利範圍第15項所述之半導體元件，其中該P-型半導體基板包括一個形成在P-型基板上的P-型外延層。
  19. 如申請專利範圍第18項所述之半導體元件，其中一個或多個該齊納二極體包括一個形成在該P-型外延層中的N-型區，以及一個形成在N-型區附近且位於該P-型外延層中的P-型區。
  20. 如申請專利範圍第18項所述之半導體元件，其中形成在一個或多個該齊納二極體下方的該第一N-型區，是一個形成在該P-型基板和該P-型外延層之間的N-型掩埋層。
  21. 如申請專利範圍第15項所述之半導體元件，其中該場效應電晶體為耗盡型電晶體。
  22. 如申請專利範圍第15項所述之半導體元件，其中該場效應電晶體為結型場效應電晶體。
  23. 如申請專利範圍第15項所述之半導體元件，其進一步包括一個第二N-型區，形成在該場效應電晶體下方的該P-型半導體基板中，其中該第一N-型區和該第二N-型區被該穿通阻擋區隔開。
  24. 一種半導體元件，其包括：一個或多個齊納二極體；以及一個場效應電晶體，具有一個漏極，該漏極與一個或多個該齊納二極體串聯；其中一個或多個該齊納二極體和該場效應電晶體，是在相同的P-型半導體基板中藉由多個摻雜區製成的，並且被一個穿通阻擋區隔開；以及一個第一N-型區，形成在一個或多個該齊納二極體下方，以終止從齊納二極體的P-型阱區或P-型本體區向P-型半導體基板的穿通；其中多個該摻雜區包括多個中心區域，一個或多個該齊納二極體的陰極位於多個該中心區域的中心處。
  25. 如申請專利範圍第24項所述之半導體元件，其中多個該摻雜區包括一個最外面的區域，該最外面的區域為該場效應電晶體的源極。
  26. 如申請專利範圍第24項所述之半導體元件，其中該場效應 電晶體為耗盡型電晶體。
  27. 如申請專利範圍第24項所述之半導體元件，其中該場效應電晶體為結型場效應電晶體。
  28. 如申請專利範圍第24項所述之半導體元件，其進一步包括一個第二N-型區，形成在該場效應電晶體下方的該P-型半導體基板中，其中該第一N-型區和該第二N-型區被該穿通阻擋區隔開。
  29. 如申請專利範圍第24項所述之半導體元件，其中該P-型半導體基板包括一個形成在P-型基板上的P-型外延層。
  30. 如申請專利範圍第29項所述之半導體元件，其中一個或多個該齊納二極體包括一個形成在該P-型外延層中的N-型區，以及一個形成在N-型區附近且位於該P-型外延層中的P-型區。
  31. 如申請專利範圍第29項所述之半導體元件，其中形成在一個或多個該齊納二極體下方的該第一N-型區，是一個形成在該P-型基板和該P-型外延層之間的N-型掩埋層。
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