SE518797C2 - Effekt-LDMOS-transistor innefattande ett flertal parallellkopplade transistorsegment med olika tröskelspänningar - Google Patents

Effekt-LDMOS-transistor innefattande ett flertal parallellkopplade transistorsegment med olika tröskelspänningar

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Publication number
SE518797C2
SE518797C2 SE0002714A SE0002714A SE518797C2 SE 518797 C2 SE518797 C2 SE 518797C2 SE 0002714 A SE0002714 A SE 0002714A SE 0002714 A SE0002714 A SE 0002714A SE 518797 C2 SE518797 C2 SE 518797C2
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Sweden
Prior art keywords
transistor segments
transistor
segments
group
different
Prior art date
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SE0002714A
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English (en)
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SE0002714L (sv
SE0002714D0 (sv
Inventor
Thomas Moller
Nils Af Ekenstam
Jan Johansson
Timothy Ballard
Gary Lopez
Michael Peternel
Original Assignee
Ericsson Telefon Ab L M
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Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE0002714A priority Critical patent/SE518797C2/sv
Publication of SE0002714D0 publication Critical patent/SE0002714D0/sv
Priority to TW089122546A priority patent/TW486822B/zh
Priority to AU2001271188A priority patent/AU2001271188A1/en
Priority to PCT/SE2001/001596 priority patent/WO2002007223A1/en
Priority to CNB018129250A priority patent/CN1291496C/zh
Priority to EP01950162A priority patent/EP1310000A1/en
Priority to US09/906,697 priority patent/US6818951B2/en
Publication of SE0002714L publication Critical patent/SE0002714L/sv
Publication of SE518797C2 publication Critical patent/SE518797C2/sv

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    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
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    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole

Description

20 25 30 518 797 Detta är inte längre sant vid låga uteffektsnivåer (s. k. backed-off-tillstånd). I dylika fall ger kollektorvilströmmen ett väsentligt och till och med dominerande bidrag till den totala kollektorströmförbrukningen.
I en LDMOS-transistor förbättras linj ariteten väsentligt när uteffekten minskas, vilket är förklaringen till att backed-off-arbetsmoden är av speciellt intresse.
Linjär prestanda är också en stark funktion av styrets förspänning.
Det finns ett optimalt värde på kollektorvilströmmen som ger bäst linjär prestanda vid en given uteffektnivå. Att ytterligare sänka kollektorvilströmmen för att förbättra verkningsgraden kommer att försämra linjariteten.
REDoGöRELsE FÖR UPPFINNINGEN Ändamålet med uppfinningen består i att förbättra verkningsgrad och linj aritet hos en effekt-LDMOS-transistor under backed-off-driftförhållanden med bibehållen toppeffektkapacitet, vilken effekt-LDMOS-transistor innefattar ett flertal parallellkopplade transistorsegment.
Detta emås i enlighet med uppfinningen genom att minst en grupp av dessa transistorsegment har en annan tröskelspänning än övri ga transistorsegment.
Tröskelspänningen är således varierad (”graded”) över transistom.
Härigenom kommer mer och mer av transistorn, d.v.s. i själva verket fler och fler transistorsegment, att aktiveras när inspänningen på dess styre ökar, vilket möjliggör förbättrad verkningsgrad och/eller linj aritet under backed-off-driftförhållanden med bibehållen toppeffektkapacitet. 10 15 20 25 30 518 797 FIGURBESKRIVNING Uppfinningen beskrivs närmare nedan under hänvisning till bifogade ritning på vilken F ig. 1 är en tvårsnittsvy av två transistorsegment hos en effekt-LDMOS- transistor enligt uppfinningen.
BESKRIVNING AV UPPFINNINGEN Fig. 1 är en tvärsnittvy av två angränsande transistorsegment hos en effekt-LDMOS- transistor enligt uppfinningen.
Det är emellertid underförstått att uppfinningen inte är begränsad till endast LDMOS-transistorer.
På i och for sig känt sätt är transistom uppbyggd i ett kiselsubstrat 1 av pli-typ med ett epitaxiellt skikt 2 av pïtyp på sin ena sida och ett emittermetallskikt (ej visat) på sin andra sida.
Emitterområden 4 av n+-typ och kollektorområden, vilka vart och ett innefattar ett kollektorkontaktorriråde 3 av n+-typ som är omgivet av driftoniråden 5 av nltyp på båda sidorna, är anordnade i pïskiktet 2. Ett kollektonnetallfinger D år anordnat ovanpå kollektorkontaktområdet 3 av n+-typ.
Styreflngrar G är inbäddade i dielektriska skikt 7 på kollektonnetallfingrets D båda sidor ovanpå plskiktet 2. En p-fieka 6 år lateralt diffunderad under varje styrefinger 7 från dess emittersida.
Djupdiffunderade pïområden 8 gör det möjligt för ström att passera från emitterområdena 4 av nïtyp till pïsubstratet 1 med minimalt spänningsfall med hjälp av spänningsklampar 9, d.v.s. metalliska kontakter, som kortsluter emitterområdena 4 av n+-typ och pïområdena 8. 10 15 20 25 30 518 797 4 Som anförts i beskrivningsinledningen är det vanligtvis önskvärt att transistorsegmentens tröskelspänning är likforinig över hela transistom så att ström delas lika mellan transistorsegmenten och maximal verkningsgrad uppnås när transistom arbetar med full effekt.
Såsom också anförts ovan är verkningsgrad och linjaritet inte optimerade när transistorn arbetar under s. k. backed-off-forhållanden, d.v.s. under sin l dB kompressionspunkt, när tröskelspänningen hos transistorsegmenten är likformig över hela transistom.
Enligt uppfinningen justeras tröskelspänningen hos transistorsegmenten gradvis över hela transistom. I praktiken kommer grupper av transistorsegment att ha olika tröskelspänningar. Dessa grupper behöver inte vara belägna på en och samma bricka utan kan vara belägna på olika hopkopplade brickor Under drift kommer den konstanta förspänningen på styret hos transistom enligt uppfinningen att justeras för att göra det möjligt for en kollektorvilström att flyta genom endast den del av transistorn som har den lägsta tröskelspänningen.
Allteftersom inspänningen ökar kommer mer och mer av transistom, d.v.s. fler och fler transistorsegment, att aktiveras vilket möjliggör förbättrad verkningsgrad och linj aritet under backed-off-driftförhållanden med bibehållen toppeffektkapacitet.
Tröskelspänningen hos ett LDMOS-transistorsegment bestäms av styreoxidens tjocklek, koncentrationen av bor under styret samt valet av styrefingermaterial.
Det finns ett flertal sätt att åstadkomma varierade tröskelspänningar i en transistor.
Det mest praktiska sättet att åstadkomma varierade tröskelspänningar är att variera p-fickans dopning. 10 15 20 25 30 518 797 Normalt används ett maskskikt för att definiera områden där implanteringen i p- fickan introduceras i kislet och borimplanteringen sedan görs efterföljd av en värmeindrivningscykel.
För att åstadkomma varierade tröskelspänningar är det också möjligt att använda multipla p-fickeimplanteringsmasker och -använda olika p-fickeimplanteringsdoser eller implanteringsenergier eller implanteringslutningsvinklar för olika transistorsegment och fortfarande följa upp med en vanlig värmeindrivningscykel, -använda samma p-fickeimplanteringsdos varje gång men olika sekventiclla indrivningscykler eller -använda en kombination av dessa metoder.
Andra sätt att åstadkomma varierade tröskelspänningar i transistorn är att -variera mängden av lateral f-emitterdiffilsion mellan transistorsegmenten genom att använda samma metoder som beskrivits ovan, -introducera varierande mängder tröskeljusteringsimplantat innan styret formeras, -använda styrefingrar av polykisel med olika dopning mellan transistorsegmenten eller till och med använda olika styrematerial eller -variera styreoxidtjockleken mellan transistorsegment.
Beroende på den använda processen torde fler möjligheter enkelt vara uppenbara för fackmannen.
Om två eller flera separata transistorbrickor med olika tröskelspänningar monteras parallellt i samma kapsel gäller fortfarande den grundläggande principen. 10 518 797 Exempel: Genom att justera exemplevis p-fickeimplanteringens lutningsvinkel justerades tröskelspänningen för en LDMOS-transistor som arbetar i 1,8-2,0 GHz-området på sådant sätt att transistorns ena halva hade en tröskelspänning som var ungefär 0,3 V lägre än den andra halvans tröskelspänning.
Som en följd därav förbättrades tvåtonsinterrnodulationsdistortionen (IMD), som är ett vanligt mått på linjär prestanda, med ungefär 3 dB vid en uteffektsnivå 17 dB under dess 1 dB-kompressionspunkt jämfört med fallet med likformig tröskelspänning.

Claims (10)

10 15 20 25 518 797 PATENTKRAV
1. Anordning för att förbättra linj aritet och/eller verkningsgrad hos en effekt- LDMOS-transistor som innefattar ett flertal parallellkopplade transistorsegment, känntecknad av att minst en grupp av nämnda transistorsegment har en annan tröskelspänning än övriga transistorsegment.
2. Anordningen enligt kravet 1, kännetecknad av att transistorsegmenten hos nämnda minst en grupp har en p-fickedopning som skiljer sig från övriga transistorsegment.
3. Anordningen enligt kravet 2, kännetecknad av att transistorsegmenten hos nämnda minst en grupp är dopade med en annan p-fickeimplanteringsdos än övriga transistorsegment.
4. Anordningen enligt kravet 2, kännetecknad av att samtliga transistorsegment är dopade med samma implanteringsdos men en annan Sekventiell indrivningscykel användes för transistorsegmenten hos nämnda minst en grupp än för övriga transistorsegment.
5. Anordningen enligt kravet 2, kännetecknad av att transistorsegmenten hos nämnda minst en grupp är dopade med en annan p-fickeimplanteringsenergi än övriga transistorsegrnent.
6. Anordningen enligt kravet 2, kännetecknad av att transistorsegmenten hos nämnda minst en grupp är dopade med en annan implanteringslutningsvinkel än övriga transistorsegment. 10 15 518 797 8
7. Anordningen enligt kravet l, kännetecknad av att transistorsegmenten hos nämnda minst en grupp har en styreoxid vars tjocklek är en annan än tj ockleken hos styreoxiden hos övriga transistorsegment.
8. Anordningen enligt kravet 1, kännetecknad av att transistorsegmenten hos nämnda minst en grupp har en annan lateral nïemitterdiffusiou mellan transistorsegmenten än övriga transistorsegment.
9. Anordningen enligt kravet 1, kännetecknad av att transistorsegmenten hos nämnda minst en grupp har ett annat styrematerial än övriga transistorsegment.
10. Anordningen enligt något av kraven 1 - 9, kännetecknad av att nämnda minst en grupp av nämnda transistorsegment är placerad på en annan bricka än övriga transistorsegment.
SE0002714A 2000-07-19 2000-07-19 Effekt-LDMOS-transistor innefattande ett flertal parallellkopplade transistorsegment med olika tröskelspänningar SE518797C2 (sv)

Priority Applications (7)

Application Number Priority Date Filing Date Title
SE0002714A SE518797C2 (sv) 2000-07-19 2000-07-19 Effekt-LDMOS-transistor innefattande ett flertal parallellkopplade transistorsegment med olika tröskelspänningar
TW089122546A TW486822B (en) 2000-07-19 2000-10-26 An arrangement in a power MOSFET
AU2001271188A AU2001271188A1 (en) 2000-07-19 2001-07-09 A power mos transistor comprising a plurality of transistor segments with different threshold voltages
PCT/SE2001/001596 WO2002007223A1 (en) 2000-07-19 2001-07-09 A power mos transistor comprising a plurality of transistor segments with different threshold voltages
CNB018129250A CN1291496C (zh) 2000-07-19 2001-07-09 功率金属氧化物半导体场效晶体管中的配置
EP01950162A EP1310000A1 (en) 2000-07-19 2001-07-09 A power mos transistor comprising a plurality of transistor segments with different threshold voltages
US09/906,697 US6818951B2 (en) 2000-07-19 2001-07-18 Arrangement in a power mosfet

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SE0002714L (sv) 2002-01-20
CN1443371A (zh) 2003-09-17
SE0002714D0 (sv) 2000-07-19
WO2002007223A1 (en) 2002-01-24
EP1310000A1 (en) 2003-05-14
US6818951B2 (en) 2004-11-16
CN1291496C (zh) 2006-12-20
AU2001271188A1 (en) 2002-01-30
US20020047140A1 (en) 2002-04-25
TW486822B (en) 2002-05-11

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