CN107785411B - 集成有结型场效应晶体管的器件及其制造方法 - Google Patents

集成有结型场效应晶体管的器件及其制造方法 Download PDF

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CN107785411B
CN107785411B CN201610794437.6A CN201610794437A CN107785411B CN 107785411 B CN107785411 B CN 107785411B CN 201610794437 A CN201610794437 A CN 201610794437A CN 107785411 B CN107785411 B CN 107785411B
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jfet
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CN107785411A (zh
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顾炎
程诗康
张森
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CSMC Technologies Fab2 Co Ltd
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Priority to US16/329,550 priority patent/US10872823B2/en
Priority to JP2019511843A priority patent/JP6986553B2/ja
Priority to PCT/CN2017/099841 priority patent/WO2018041192A1/zh
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Abstract

本发明涉及一种集成有结型场效应晶体管的器件及其制造方法，所述器件包括：第一阱，为第二导电类型且形成于所述第一导电类型区内；第二阱，为第二导电类型且形成于所述第一导电类型区内，离子浓度大于所述第一阱的离子浓度；JFET源极，为第一导电类型；JFET源极的金属电极，形成于所述JFET源极上且与所述JFET源极接触；第二导电类型埋层，形成于所述JFET源极和第二阱下方。本发明利用了P型埋层与第二阱形成的横向沟道，使沟道浓度更加均匀，通过版图设计出较长的横向沟道，其夹断电压也会更加稳定。

Description

集成有结型场效应晶体管的器件及其制造方法
技术领域
本发明涉及半导体制造技术，特别是涉及一种集成有结型场效应晶体管的器件，还涉及一种集成有结型场效应晶体管的器件的制造方法。
背景技术
在高压工艺平台上集成高压结型场效应晶体管(Junction Field-EffectTransistor，JFET)为如今智能功率集成电路领域的一种先进开发与构想，它可以大大提升纵向功率器件的开态性能，以及显著的减小芯片面积，符合当今智能功率器件制造的主流趋势。
传统结构的高压集成JFET有较简单的工艺可以实现，但其夹断电压的不稳定的特性限制了其在智能功率集成领域的大规模应用。
发明内容
基于此，有必要针对传统的JFET夹断电压不稳定的问题，提供一种集成有结型场效应晶体管的器件。
一种集成有结型场效应晶体管的器件，所述器件包括JFET区、功率器件区、设于所述器件背面的第一导电类型的漏极，和设于所述漏极朝向所述器件正面的面上的第一导电类型区，所述JFET区和功率器件区共享所述漏极和第一导电类型区；所述JFET区还包括：第一阱，为第二导电类型且形成于所述第一导电类型区内；第二阱，为第二导电类型且形成于所述第一导电类型区内，离子浓度大于所述第一阱的离子浓度；JFET源极，为第一导电类型；JFET源极的金属电极，形成于所述JFET源极上且与所述JFET源极接触；第二导电类型埋层，形成于所述JFET源极和第二阱下方；所述第一导电类型和第二导电类型为相反的导电类型。
在其中一个实施例中，所述JFET区和功率器件区交界处形成有一所述第一阱，作为JFET区和功率器件区的隔离阱。
在其中一个实施例中，所述JFET区还包括JFET金属栅极和JFET栅极欧姆接触，所述JFET金属栅极形成于所述JFET栅极欧姆接触上且与所述JFET栅极欧姆接触相接触，所述JFET栅极欧姆接触形成于所述JFET区的第一阱、第二阱和所述隔离阱内，各所述JFET栅极欧姆接触通过所述JFET金属栅极等电位地连接在一起。
在其中一个实施例中，所述第二导电类型埋层至少与一所述第一阱相接触。
在其中一个实施例中，所述JFET源极形成于所述第二阱和与所述第二阱相邻的第一阱之间。
在其中一个实施例中，所述器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
在其中一个实施例中，所述功率器件区包括栅极，第二阱，设于所述第二阱内的第一导电类型的VDMOS源极，以及设于所述第二阱内、所述VDMOS源极下方的非钳位感性开关区；所述非钳位感性开关区为第二导电类型且离子浓度大于所述第二阱的离子浓度。
在其中一个实施例中，所述栅极的下方两侧各有一个第二阱，所述VDMOS源极形成于两个所述第二阱内，且所述VDMOS源极在两个所述第二阱的每一个内都分为两块，所述器件还包括形成于两块VDMOS源极之间的第二导电类型的欧姆接触区。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
还有必要提供一种集成有结型场效应晶体管的器件的制造方法。
一种集成有结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，所述方法包括：提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；所述第一导电类型和第二导电类型为相反的导电类型；在所述JFET区的所述第一导电类型区内形成第二导电类型埋层；向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；先后生长场氧层和栅氧层，并在所述第一导电类型区表面形成多晶硅层；向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱；注入第一导电类型的离子，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极；光刻并刻蚀接触孔，淀积金属层，填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
在其中一个实施例中，所述在所述第一导电类型区内形成第一阱的步骤，包括在所述JFET区和功率器件区交界处形成第一阱，作为JFET区和功率器件区的隔离。
在其中一个实施例中，所述第一导电类型区包括第一外延层和第二外延层；所述在所述JFET区的第一导电类型区内形成第二导电类型埋层的步骤，是对第一外延层进行光刻、第二导电类型离子注入和推阱形成第二导电类型埋层；所述向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱的步骤之前，还包括在所述第一外延层表面形成第二外延层的步骤；所述第二导电类型埋层至少与一所述第一阱相接触。
在其中一个实施例中，所述向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱的步骤之后、所述注入第一导电类型的离子的步骤之前，还包括形成注入阻挡层的步骤，以及向所述、第二阱中注入第二导电类型的离子以形成非钳位感性开关区的步骤，且注入能量大于所述注入第一导电类型的离子的步骤的注入能量。
在其中一个实施例中，所述在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤之后，所述光刻并刻蚀接触孔的步骤之前，还包括注入第二导电类型的离子，在所述JFET区第一阱和第二阱中形成JFET栅极欧姆接触、在所述功率器件区的第二阱中形成欧姆接触区的步骤。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型，所述功率器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
上述集成有结型场效应晶体管的器件及其制造方法，利用了P型埋层与第二阱形成的横向沟道，使沟道浓度更加均匀，通过版图设计出较长的横向沟道，其夹断电压也会更加稳定。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一种传统的高压集成JFET的剖面结构示意图；
图2是一实施例中集成有结型场效应晶体管的器件的剖面结构示意图；
图3是一实施例中集成有结型场效应晶体管的器件的制造方法的流程图；
图4a～4d是图3所述的制造方法在制造过程中的器件剖面结构示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
一种传统的集成高压耗尽型结型场效应晶体管(Junction Field-EffectTransistor，JFET)的垂直双扩散金属氧化物半导体场效应晶体管(Vertical Double-diffused MOSFET，VDMOS)的结构如图1所示。包括栅极101、源极102、高压P阱103、体接触104、N型外延层105以及N+接触106。
当VDMOS处于开启阶段时，电流从底部漏端流过JFET，从source2流出。当source2上加逐渐变大的电压Vg2，同时栅gate上也加同样的电压Vg1，当Vg2>夹断电压Voff时，JFET的耗尽层阻断了电流，即发生了夹断。此时Vg1>Vth，VDMOS开启，完成了一个开启过程。JFET在此吸收了DMOS在米勒平台时的突变电流，让启动更为平缓，电流可以成近似线性变换，所以JFET在启动过程中对器件稳定性提升有着很显著作用。功率器件在其工艺平台上集成寄生JFET则更具有优势。
集成寄生JFET，其最主要特性是整体击穿电压的稳定性和夹断电压的稳定性，最为理想的是，集成后器件的击穿电压保持不变，击穿点最好保持在功率VDMOS的击穿点。传统的集成结构VDMOS与JFET交接处仅用了衬底进行隔离，仅可以拉长衬底外延的横向距离来保证耗尽时的余量，这样会增加整个管芯的面积。同时，由于外延层规范有所偏差，工艺上略有变动就会出现击穿点转移，击穿点会从体内的cell区转移至JFET区或是交接处，大大降低了击穿的稳定性，还会发生击穿电压蠕变的现象。传统结构一般用自对准P型注入的衬底作为P型夹断衬底，由于VDMOS的元胞(cell)的P型衬底其纵向结深很浅，一般只有3～5微米，因此JFET的纵向沟道很短，人为无法去调整纵向沟道长度，所以夹断电压很不稳定。通过仿真可得知当漏端电压从50V到100V变化时，夹断电压Voff会从11V变大至20V，而在实际应用中需要Voff稳定，因此该传统结构难以满足实际需求。
图2是一实施例中集成有结型场效应晶体管的器件的剖面结构示意图，在本实施例中，定义N型为第一导电类型，P型为第二导电类型，器件为VDMOS。如图2中所示，将器件按结构分为JFET区和VDMOS区，JFET区和VDMOS区共享设于器件背面(即图2中朝下的面)的N型的漏极201，和设于漏极201正面(即图2中朝上的面)的N型区(包括第一N型区202和第二N型区204)。在本实施例中，漏极201为N+漏极，N型区为N-外延层。为便于形成P型埋层203，N型区分两次外延分别形成第一N型区202和第二N型区204，可以理解的，在其他实施例中在确保形成所需的P型埋层203的前提下，N型区也可以为单层结构。外延层厚度和浓度的变化会改变夹断电压大小，浓度越小，外延厚度越薄(考虑到反扩和P阱的结深，第一N型区202和第二N型区204总的外延厚度一般要大于4微米，典型的厚度为4微米～7微米)，夹断效果越好。
在本实施例中，JFET区包括：
第一阱205，为P-阱且形成于N型区内。
第二阱207，为高压P阱且形成于N型区内，离子浓度大于第一阱205的离子浓度。作为器件的N型接触，形成导电沟道。
JFET源极212，N+的JFET源极212作为JFET的源极接触。
JFET源极的金属电极，形成于JFET源极212上且与JFET源极212接触。
P型埋层203，形成于JFET源极212和第二阱207下方。
上述集成有结型场效应晶体管的器件，利用了P型埋层203与第二阱207形成的横向沟道，使沟道浓度更加均匀，通过版图设计出较长的横向沟道，其夹断电压也会更加稳定。
在图2所示实施例中，JFET区和VDMOS区交界处也形成有一个第一阱205，作为JFET区和VDMOS区的隔离。利用P-的第一阱205辅助耗尽隔离，通过较深的P-阱隔离，可以完全阻断电流的流通路径，防止JFET和VDMOS间的漏电，且在器件反偏耐压时可以辅助下方的N-外延层(即第一N型区202)参与耗尽，提升局部区域的击穿电压来固化击穿点作用。同时，该第一阱205作为结终端扩展技术中终端的耗尽结构，能够有效缩短高压VDMOS的芯片面积。另外由于该结终端扩展的结工艺存在，P-阱结深大大超过了传统技术中VDMOS的P型衬底的结深，从而有了较长的纵向电流沟道。相较于传统结构，器件的夹断电压稳定性会提高较多，同时夹断电压也会显著降低。
在图2所示的实施例中，JFET区还包括JFET金属栅极213和JFET栅极欧姆接触214。JFET金属栅极213形成于JFET栅极欧姆接触214上且与JFET栅极欧姆接触214相接触。各JFET栅极欧姆接触214分别形成于JFET区的第一阱205和第二阱207内，各JFET栅极欧姆接触214通过JFET金属栅极213等电位地连接在一起。
在其中一个实施例中，P型埋层203至少与一第一阱205相接触，在图2所示实施例中第二阱207的下方两侧各有一个P型埋层203，这两个P型埋层203分别与一个第一阱205相接触。通过深阱扩散形成的第一阱205与P型埋层203相连，可以将P型埋层203的电位引出，避免了P型埋层203的浮空，使其夹断电压在随漏极电压变化时更加稳定。
在图2所示的实施例中，JFET源极212形成于第二阱207和第一阱205(与第二阱207相邻的一个第一阱205)之间。
在图2所示实施例中，VDMOS区包括栅极206、第二阱207、设于第二阱207内的N+的VDMOS源极209、以及设于VDMOS源极209下方的P++型的非钳位感性开关(UnclampedInductive Switching,UIS)区208。非钳位感性开关区208的离子浓度大于第二阱207的离子浓度。在图2所示实施例中，JFET区也形成有非钳位感性开关区208，具体是设于第二阱207内的JFET栅极欧姆接触214的下方，且在本实施例中为第二阱207内，在其他实施例中也可以是第二阱207外、第一阱205内。非钳位感性开关区208可以减小寄生NPN三极管的基极电阻，增大器件的雪崩耐量。
在图2所示实施例中，栅极206的下方两侧各有一个第二阱207，VDMOS源极209形成于这两个第二阱207内，且VDMOS源极209在这两个第二阱207的每一个内都分为两块。器件还包括形成于两块VDMOS源极209之间的P+型的欧姆接触区210。
图3是一实施例中集成有结型场效应晶体管的器件的制造方法的流程图，以下以器件是VDMOS，第一导电类型是N型，第二导电类型是P型为例，介绍集成有结型场效应晶体管的器件的制造方法：
S510，提供第一导电类型的衬底，衬底上形成有第一导电类型区。
在本实施例中，是在N+衬底上外延形成N型区，衬底后续将会作为器件的漏极201。
S520，在JFET区的第一导电类型区内形成第二导电类型埋层。
在本实施例中，第一导电类型区包括第一外延层(即第一N型层202)和第二外延层(即第二N型层204)。步骤S520是对第一外延层进行光刻、P型离子注入和推阱形成P型埋层203，图4a是P型埋层203形成后器件的剖面结构示意图。P型埋层203形成后在第一外延层表面形成第二外延层。P型埋层203至少与一第一阱205相接触。
S530，注入第二导电类型的离子并推阱，在第一导电类型区内形成第一阱。
在本实施例中，是向N型区中注入P型离子并推阱，在N型区内形成第一阱205。
S540，生长场氧层和栅氧层，并形成多晶硅层。
生长厚的场氧层然后生长栅氧层，并在N型区表面形成多晶硅层604。
S550，向第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱。
在本实施例中，是以场氧层和多晶硅层604为掩膜向N型区注入P型离子，推阱形成多个第二阱207。图4b是步骤S550完成后器件的剖面结构示意图。
参见图4c，在本实施例中，执行步骤S560之前还包括向第二阱207中注入P型离子的步骤，以在JFET区和功率器件区的第二阱207内形成非钳位感性开关区208。为了防止向第二阱207中注入的P型离子对沟道区造成不利影响，本实施例中在注入P型离子形成非钳位感性开关区208的步骤之前，还包括形成注入阻挡层的步骤。在本实施例中形成注入阻挡层是通过再形成一层氧化层，由于注入P型离子形成非钳位感性开关区208的注入窗口处的氧化层较薄，因此高能注入的P型离子可以穿过氧化层形成非钳位感性开关区208。而其他位置处的氧化层形成于场氧层、多晶硅层604等结构上，因此整个注入阻挡层的厚度较厚，P型离子难以穿过注入阻挡层进入N型区内。
S560，注入第一导电类型的离子，在JFET区形成JFET源极、在功率器件区形成功率器件源极。
参见图4d，在本实施例中，是用光刻工艺以光刻胶为掩膜注入N型离子，在JFET区的第二阱207内形成JFET源极，在功率器件区的第二阱207内形成VDMOS源极209。其中VDMOS源极209形成于栅极两侧的各一个第二阱207内，且在每个第二阱207内都分成两块，中间留出给后续步骤形成的欧姆接触区210的位置。
在本实施例中，步骤S560完成后，还包括在第一阱205、第二阱207中形成栅极欧姆接触214和欧姆接触区210的步骤。具体是在JFET区的第一阱205和第二阱207中形成JFET栅极欧姆接触214，在功率器件区的第二阱207中形成欧姆接触区210。
S570，光刻并刻蚀接触孔，淀积金属层，填入接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
填入接触孔的金属与JFET栅极欧姆接触214相接触形成JFET金属栅极213，与JFET源极212相接触形成JFET源极的金属电极。淀积金属层后在器件表面形成钝化层，完成后器件的剖面如图2所示。
综合上述优势，上述集成有结型场效应晶体管的器件在传统技术的基础上提升了夹断电压的稳定性，固化了击穿点，加强了UIS能力，工艺上完全匹配，并且实现了夹断电压大小的可调性。
在其中一个实施例中，步骤S520包括在JFET区和功率器件区交界处形成一个第一阱205作为JFET区和功率器件区的隔离。
在其中一个实施例中，步骤S530的第一阱205的注入浓度为1.5E13cm-2～2.2E13cm-2，第一阱205的阱深为8.5微米～13.5微米。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

1.一种集成有结型场效应晶体管的器件，所述器件包括JFET区、功率器件区、设于所述器件背面的第一导电类型的漏极，和设于所述漏极朝向所述器件正面的面上的第一导电类型区，所述JFET区和功率器件区共享所述漏极和第一导电类型区；其特征在于，所述JFET区还包括：
第一阱，为第二导电类型且形成于所述第一导电类型区内；
第二阱，为第二导电类型且形成于所述第一导电类型区内、所述第一阱之外，离子浓度大于所述第一阱的离子浓度；
JFET源极，为第一导电类型；
JFET源极的金属电极，形成于所述JFET源极上且与所述JFET源极接触；
第二导电类型埋层，形成于所述JFET源极和第二阱下方；
所述第一导电类型和第二导电类型为相反的导电类型。
2.根据权利要求1所述的集成有结型场效应晶体管的器件，其特征在于，所述JFET区和功率器件区交界处形成有一所述第一阱，作为JFET区和功率器件区的隔离阱。
3.根据权利要求2所述的集成有结型场效应晶体管的器件，其特征在于，所述JFET区还包括JFET金属栅极和JFET栅极欧姆接触，所述JFET金属栅极形成于所述JFET栅极欧姆接触上且与所述JFET栅极欧姆接触相接触，所述JFET栅极欧姆接触形成于所述JFET区的第一阱、第二阱和所述隔离阱内，各所述JFET栅极欧姆接触通过所述JFET金属栅极等电位地连接在一起。
4.根据权利要求3所述的集成有结型场效应晶体管的器件，其特征在于，所述第二导电类型埋层至少与一所述第一阱相接触。
5.根据权利要求1所述的集成有结型场效应晶体管的器件，其特征在于，所述JFET源极形成于所述第二阱和与所述第二阱相邻的第一阱之间。
6.根据权利要求1所述的集成有结型场效应晶体管的器件，其特征在于，所述器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
7.根据权利要求6所述的集成有结型场效应晶体管的器件，其特征在于，所述功率器件区包括栅极，功率器件区第二阱，设于所述功率器件区第二阱内的第一导电类型的VDMOS源极，以及设于所述功率器件区第二阱内、所述VDMOS源极下方的非钳位感性开关区；所述非钳位感性开关区为第二导电类型，且非钳位感性开关区的离子浓度大于所述功率器件区第二阱的离子浓度。
8.根据权利要求7所述的集成有结型场效应晶体管的器件，其特征在于，所述栅极的下方两侧各有一个所述功率器件区第二阱，所述VDMOS源极形成于两个所述功率器件区第二阱内，且所述VDMOS源极在两个所述功率器件区第二阱的每一个内都分为两块，所述器件还包括形成于两块VDMOS源极之间的第二导电类型的欧姆接触区。
9.根据权利要求1-8中任意一项所述的集成有结型场效应晶体管的器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。
10.一种集成有结型场效应晶体管的器件的制造方法，所述器件包括JFET区和功率器件区，其特征在于，所述方法包括：
提供第一导电类型的衬底，所述衬底上形成有第一导电类型区；
在所述JFET区的所述第一导电类型区内形成第二导电类型埋层；
所述第一导电类型和第二导电类型为相反的导电类型；
向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱；
先后生长场氧层和栅氧层，并在所述第一导电类型区表面形成多晶硅层；
向所述第一导电类型区注入第二导电类型的离子并推阱形成多个位于所述第一阱之外的第二阱；
注入第一导电类型的离子，在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极；
光刻并刻蚀接触孔，淀积金属层，填入所述接触孔内，分别形成JFET源极的金属电极、JFET金属栅极及功率器件源极的金属接触。
11.根据权利要求10所述的方法，其特征在于，所述在所述第一导电类型区内形成第一阱的步骤，包括在所述JFET区和功率器件区交界处形成第一阱，作为JFET区和功率器件区的隔离。
12.根据权利要求10所述的方法，其特征在于，所述第一导电类型区包括第一外延层和第二外延层；所述在所述JFET区的第一导电类型区内形成第二导电类型埋层的步骤，是对第一外延层进行光刻、第二导电类型离子注入和推阱形成第二导电类型埋层；所述向第一导电类型区中注入第二导电类型的离子并推阱，在所述第一导电类型区内形成第一阱的步骤之前，还包括在所述第一外延层表面形成第二外延层的步骤；所述第二导电类型埋层至少与一所述第一阱相接触。
13.根据权利要求10所述的方法，其特征在于，所述向所述第一导电类型区注入第二导电类型的离子并推阱形成多个第二阱的步骤之后、所述注入第一导电类型的离子的步骤之前，还包括形成注入阻挡层的步骤，以及向所述第二阱中注入第二导电类型的离子以形成非钳位感性开关区的步骤，且非钳位感性开关区的注入能量大于所述注入第一导电类型的离子的步骤的注入能量。
14.根据权利要求10所述的方法，其特征在于，所述在所述JFET区形成JFET源极、在所述功率器件区形成功率器件源极的步骤之后，所述光刻并刻蚀接触孔的步骤之前，还包括注入第二导电类型的离子，在所述JFET区第一阱和第二阱中形成JFET栅极欧姆接触、在所述功率器件区的第二阱中形成欧姆接触区的步骤。
15.根据权利要求10-14中任一项所述的方法，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述器件是垂直双扩散金属氧化物半导体场效应晶体管VDMOS。
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