WO2016058277A1 - 一种浅沟槽半超结vdmos器件及其制造方法 - Google Patents

一种浅沟槽半超结vdmos器件及其制造方法 Download PDF

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WO2016058277A1
WO2016058277A1 PCT/CN2014/095928 CN2014095928W WO2016058277A1 WO 2016058277 A1 WO2016058277 A1 WO 2016058277A1 CN 2014095928 W CN2014095928 W CN 2014095928W WO 2016058277 A1 WO2016058277 A1 WO 2016058277A1
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epitaxial layer
resistivity
resistive
conductivity type
layer
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PCT/CN2014/095928
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English (en)
French (fr)
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周宏伟
孙晓儒
阮孟波
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无锡华润华晶微电子有限公司
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Priority to US15/323,106 priority Critical patent/US20170288047A1/en
Publication of WO2016058277A1 publication Critical patent/WO2016058277A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • the present invention relates to the field of semiconductor devices and their manufacturing processes, and more particularly to a shallow trench semi-superjunction VDMOS device and a method of fabricating the same.
  • a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device is a power semiconductor device having advantages of both a bipolar transistor and a general MOS device. Compared with bipolar transistors, it has fast switching speed, low switching loss, high input impedance, low driving power, good frequency characteristics, high translinearity, no secondary breakdown of bipolar power devices, and safety. The work area is large. Therefore, VDMOS devices are ideal power semiconductor devices for both switching and linear applications.
  • VDMOS devices An important indicator for VDMOS devices is the on-resistance. With the development of VDMOS devices, their structure has been continuously improved to reduce the on-resistance as much as possible, thereby improving the ability to conduct current.
  • FIG. 1 The structure of the existing VDMOS device is shown in FIG. 1 , taking an N-type VDMOS device as an example, including:
  • a substrate comprising a body layer 101 and an epitaxial layer 102 over the body layer, the body layer 101 comprising a drain region, wherein the body layer 101 and the epitaxial layer 102 are N-type doped;
  • first body region 103 and a second body region 104 located within the epitaxial layer 102, the first body region 103 and The doping region 104 has the same doping state and is P-type doped;
  • the first source region 105 located in the first body region 103 is located in the second source region 106 in the second body region 104.
  • the doping states of the first source region 105 and the second source region 106 are the same, and are N-type. Doping.
  • the conventional structure of VDMOS with the increase of breakdown voltage, because the epitaxial layer has a low doping concentration and a relatively large thickness, resulting in a large on-resistance, which is known as the "silicon limit" ("Si Limit” "), the on-resistance increases as the withstand voltage becomes 2.5. That is, the on-resistance rapidly increases as the withstand voltage increases; at the same time, its forward conduction resistance is high, resulting in a large chip area. It can be seen that the conventional VDMOS device has a defect of high on-resistance.
  • the present invention provides a shallow trench semi-superjunction VDMOS device and a method of fabricating the same, which solves the technical problems of excessive forward conduction resistance and weak current conduction capability per unit area of a conventional VDMOS device.
  • a shallow trench semi-superjunction VDMOS device comprising:
  • first resistive epitaxial layer over the first conductivity type substrate, and the first conductivity type substrate is of the same conductivity type as the first resistivity epitaxial layer;
  • Two third resistive epitaxial layers extending from an upper surface of the second resistive epitaxial layer to a bottom of the second resistive epitaxial layer, two third resistive epitaxial layers are spaced apart; and the third resistive epitaxial layer
  • the conductivity type is opposite to the conductivity type of the second resistivity epitaxial layer
  • a fourth resistive epitaxial layer over the second resistive epitaxial layer, and a conductivity type of the fourth resistive epitaxial layer is the same as a conductivity type of the second resistive epitaxial layer;
  • first source region and a second source region of a first conductivity type located above the two well regions, and source metal layers at surfaces of the first source region and the second source region;
  • a drain metal layer under the first conductive type substrate a gate region between the first source region and the second source region and above the fourth resistivity epitaxial layer, and a gate region a gate metal layer on the upper surface of the polar region.
  • the first resistivity epitaxial layer has a resistivity of 5-20 ohm.cm; the second resistivity epitaxial layer has a resistivity of 2-10 ohm.cm; and the third resistor in the trench
  • the resistivity of the epitaxial layer is 2-10 ohm.cm; and the resistivity of the fourth resistive epitaxial layer is 2-10 ohm.cm.
  • the upper surface of the second resistivity epitaxial layer is in the same plane as the upper surface of the third resistivity epitaxial layer.
  • a method for fabricating a shallow trench semi-superjunction VDMOS device comprising:
  • a gate region is formed between the first source region and the second source region and above the fourth resistivity epitaxial layer.
  • the first resistivity epitaxial layer has a resistivity of 5-20 ohm.cm; the second resistivity epitaxial layer has a resistivity of 2-10 ohm.cm; and the third resistor in the trench
  • the resistivity of the epitaxial layer is 2-10 ohm.cm; and the resistivity of the fourth resistive epitaxial layer is 2-10 ohm.cm.
  • the groove has a width of between 0 and 10 um and a depth of between 0 and 30 um.
  • the third resistivity epitaxial layer formed in the trench is subjected to mechanical polishing or chemical etching beyond the upper surface portion of the second resistivity epitaxial layer to make the upper surface of the second resistivity epitaxial layer and the third resistivity
  • the upper surface of the epitaxial layer is on the same plane.
  • the well region is formed by: using a photoresist as a barrier layer on the fourth resistive epitaxial layer, implanting impurity ions of the same conductivity type as the trenches above the trench, and thermally annealing The well region is formed afterwards.
  • the present invention relates to the field of semiconductor technology, and in particular to a shallow trench semi-superjunction VDMOS device and a method of fabricating the same.
  • the present invention introduces a shallow trench region in a conventional VDMOS structure, which is filled with an epitaxial layer of a certain conductivity type of appropriate resistivity, and is subjected to chemical mechanical polishing (CMP) or chemical etching to leave the epitaxial layer Inside the groove.
  • CMP chemical mechanical polishing
  • the regrowth has an extension of the opposite conductivity type as described above a layer, and then using a photoresist as a barrier layer, implanting impurity ions of the same conductivity type as the epitaxial layer over the epitaxial layer in the trench, and forming a well region after thermal annealing, after a certain thermal process, the well region and The epitaxial layers in the trenches are connected to make the original conventional structure VDMOS a semi-super junction structure.
  • the shallow trench is filled with an epitaxial layer of a certain conductivity type, and is connected with a well region having the same conductivity type above it to form a pillar.
  • the depth of the pillar is much shallower than that of the conventional super junction device structure.
  • FIG. 1 is a schematic structural view of a VDMOS tube in the prior art
  • FIG. 2 is a schematic structural diagram of a shallow trench semi-superjunction VDMOS device according to an embodiment of the present invention
  • FIG. 3 is a flow chart of a method for fabricating an N-type shallow trench semi-superjunction VDMOS device according to an embodiment of the present invention
  • 3A-3F are cross-sectional views of a shallow trench semi-superjunction VDMOS device in various steps of a method for fabricating a VDMOS device according to an embodiment of the present invention.
  • the on-resistance of a conventional VDMOS is limited by the silicon limit as the withstand voltage increases, that is, the on-resistance increases rapidly with the withstand voltage, and in order to prevent the breakdown of the resistance region, the device The lateral dimension cannot be made too small, which in turn causes the device cell to occupy a large area, resulting in low utilization of the substrate surface.
  • the on-resistance is reduced, the manufacturing process is complicated and cannot be used in a wide range.
  • VDMOS devices are N-type VDMOS devices.
  • the present invention will be explained by taking a strip cell structure of an N-type shallow trench semi-superjunction VDMOS device and a fabrication method thereof as a specific embodiment. It should be noted that the present invention is not limited to the strip cell structure of the N-type shallow trench semi-superjunction VDMOS device and the fabrication method thereof, and the present invention is equally applicable to the strip cell structure of other types of VDMOS devices.
  • an embodiment of the present invention provides a shallow trench semi-super-junction VDMOS device, and the structure thereof is as shown in FIG. 2, including:
  • An N second resistivity epitaxial layer 303 having a resistivity of about 2-10 ohm ⁇ cm above the N-type first resistive epitaxial layer;
  • Two P-type third resistive epitaxial layers 304 extending from the upper surface of the N-type second resistive epitaxial layer 303 to the bottom of the second resistive epitaxial layer, and two third resistive epitaxial layers are spaced apart;
  • N-type fourth resistive epitaxial layer 305 is formed over the N-type second resistive epitaxial layer 303, and then a photoresist is used as a barrier layer, and is implanted from the surface of the fourth resistive epitaxial layer 305, and the third Two P-type well regions 306 connected by a resistivity epitaxial layer 304;
  • the VDMOS device in this embodiment further includes: a drain metal layer 311 under the first conductive type substrate 301; and a first source having a first conductivity type above the two P-type well regions 306. a region 313 and a second source region 313, and source metal layers 307 on the surfaces of the first source region 313 and the second source region 313; located between the first source region 313 and the second source region 313, and A gate region 308 over the fourth resistive epitaxial layer and a gate metal layer 310 on an upper surface of the gate region.
  • the above is an N-type VDMOS device as an example to illustrate the specific structure and doping type of the present invention.
  • the structure of the VDMOS device disclosed in the present invention is also applicable to a P-type VDMOS device, that is,
  • the first conductivity type may be an N type
  • the second conductivity type is a P type
  • the first conductivity type may be a P type
  • the second conductivity type may be an N type.
  • the P-type resistivity epitaxial layer 304 is connected with the P-well above it to form a P-pillar, the depth of the P-pillar and the conventional super junction device. Compared with the structure, it is much shallower, so we call it a semi-super-junction.
  • the device structure of the semi-super-junction can improve the electric field strength per unit area, that is, the withstand voltage capability is enhanced, so that epitaxial doping with lower resistance can be used, and the on-resistance is greatly reduced.
  • VDMOS N-type shallow trench semi-superjunction VDMOS of this embodiment
  • BV is the breakdown voltage of the device
  • Rsp is the on-resistance per unit area
  • Vth Is the threshold voltage
  • the N-type shallow trench semi-superjunction VDMOS device provided by the embodiment of the invention greatly reduces the forward conduction resistance compared to the conventional DMOS.
  • Semi-superjunction device characteristics are between the traditional superjunction and the traditional planar high voltage DMOS, although the unit The on-resistance of the area is larger than the on-resistance of the super junction, but it is still significantly lower than the conventional planar device by 30-40%, and the characteristics of the body diode are also closer to those of the conventional DMOS, which is better than Superb has an advantage.
  • the JFET region between the P pillars can achieve the same breakdown voltage with a lower N-type resistivity material (compared to the conventional planar DMOS). Therefore, the resistance per unit area will be significantly lower than that of the conventional planar DMOS.
  • FIG. 3 is a flow chart of a manufacturing method of the shallow trench semi-superjunction VDMOS device; FIG. 3A to FIG. 3F are cross-sectional views of the steps of the method, In this embodiment, only the N-type shallow trench semi-superjunction VDMOS device is taken as an example, and the flow chart and the cross-sectional views of the steps are described.
  • Step 1 providing an N-type substrate 301;
  • the single crystal silicon wafer is heavily doped with N-type ions to form an N-type semiconductor substrate, and the N-type ions are phosphorus or arsenic.
  • Step 2 generating an N-type first resistive epitaxial layer 302 over the N-type substrate;
  • Step 3 generating an N-type second resistivity epitaxial layer 303 over the N-type first resistive epitaxial layer 302;
  • an N-type single crystal silicon layer is epitaxially formed over the N-type substrate by an epitaxial method to form an N-type first resistive epitaxial layer 302, and the doped ions and the N-type liner of the first resistivity epitaxial layer are formed.
  • the ions in the bottom are the same.
  • the resistivity of the first resistive epitaxial layer is 5-20 ohm.cm.
  • an N-type second resistive epitaxial layer 303 may be formed over the first resistive epitaxial layer 302. And the resulting resistivity is 2-10 ohm.cm.
  • Step 4 engraving two trench regions 312 on both sides of the upper surface of the N-type second resistive epitaxial layer 303 and extending from the upper surface to the bottom of the second resistive epitaxial layer;
  • Step 5 implanting a P-type third resistive epitaxial layer 304 in the shallow trench
  • the formed N-type second resistivity epitaxial layer 303 Two trenches 312 are formed, the trenches having a width between 0 and 10 um and a depth between 0 and 30 um; in the embodiment provided by the present invention, the two shallow trenches formed by the ion implantation method are formed.
  • the P-type epitaxial layer 304 is implanted therein and subjected to chemical mechanical polishing or chemical etching so that the P-type epitaxy remains only in the trench; the P-type ions implanted in this step may be boron or indium.
  • Step 6 generating an N-type fourth resistive epitaxial layer 305 on the upper surface of the N-type second resistive epitaxial layer 303;
  • Step 7 Two P-type well regions implanted on both sides of the upper surface of the N-type fourth resistive epitaxial layer 305 and connected to the third resistive epitaxial layer 304 in the two trenches.
  • an N-type fourth resistive epitaxial layer 305 is first formed on the upper surface of the appeal N-type second resistive epitaxial layer 303, and the generated resistivity is 2-10 ohms.
  • Cm on the N-type fourth resistivity epitaxial layer 305, using a photoresist as a barrier layer, being implanted from the surface of the epitaxial layer, and forming a P-well 306 after thermal annealing over the P region in the trench, and P well 306 is connected to the P region within the trench.
  • the third resistive epitaxial layer 303 formed in the trench is mechanically polished or chemically etched beyond the upper surface portion of the second resistive epitaxial layer 303, so that the P-type epitaxy remains only in the trench, ensuring the second
  • the upper surface of the resistivity epitaxial layer 303 is on the same plane as the upper surface of the third resistive epitaxial layer 304.
  • Step 8 forming a gate region 308 on the surface of the fourth resistive epitaxial layer 305;
  • a gate oxide layer 308 is grown over the fourth resistivity epitaxial layer, the gate oxide layer 308 includes at least silicon oxide, and both ends of the lower surface of the gate oxide layer 308 are in contact with the P-type well region;
  • a polysilicon layer 309 is deposited over the gate oxide layer 308, and the polysilicon layer 309 is formed using a low pressure chemical vapor deposition process.
  • a photoresist layer having a gate region pattern is formed on the surface of the polysilicon layer by a photolithography process, and a photoresist layer having a gate region pattern is used as a mask, and the photoresist layer is simultaneously etched by dry etching.
  • the covered polysilicon layer and the gate oxide layer 308 thereunder temporarily retain the photoresist layer.
  • Step 9 generating two N-type source regions above the two P-type well regions: a first source region 313 and a second source region 313;
  • Step 10 forming a gate metal layer 310, a source metal layer 307, and a drain metal layer 311 over the gate region 308, over the two N-type source regions 313, and under the N-type substrate 301, respectively.
  • a metal layer is deposited on the upper surface and the back surface of the device, and the metal layer may be formed by a metal chemical vapor deposition method.
  • the metal layer formed over the polysilicon layer 309 is the gate metal layer 310.
  • the metal layer formed over the N-type source region is the source metal layer 307, and the metal layer formed on the back surface of the N-type substrate 301 is the drain metal layer 311.
  • the gate region and the gate metal layer 310 constitute a gate G, and the first source region 313, the second source region 313 and the source metal layer 307 constitute a source S, and the N-type substrate 301 and the drain metal layer 311 constitute Drain D.
  • the substrate in this embodiment may include a semiconductor element such as single crystal, polycrystalline or amorphous silicon or silicon germanium (SiGe), and may also include a mixed semiconductor structure such as silicon carbide or indium antimonide. Lead, lead arsenide, indium arsenide or gallium antimonide, alloy semiconductors or combinations thereof; or silicon-on-insulator (SOI).
  • the semiconductor substrate may also include other materials such as an epitaxial layer or a buried layer multilayer structure. Although a few examples of materials that can form a substrate are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.
  • This embodiment discloses a method for fabricating the shallow trench semi-superjunction VDMOS transistor.
  • a shallow trench structure is introduced on the basis of the conventional VDMOS device; specifically, in this embodiment, the N-type is A shallow trench is formed on the epitaxial layer 303, and then the shallow trench 312 is filled with a P-type epitaxial layer of appropriate resistivity by ion implantation or other means, in order to ensure that the P-type epitaxy remains only in the shallow trench, in the trench
  • the surface is chemically mechanical (CMP) or chemically etched.
  • An N-type epitaxial layer 305 is then formed on the N-type epitaxial layer 302, and then implanted into the P-well 306. After a thermal process, the P-well is connected to the P-type epitaxy in the trench to form a semi-superjunction.

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Abstract

一种浅沟槽半超结VDMOS器件及其制造方法，其中浅沟槽半超结VDMOS器件包括：第一导电类型衬底（301）；位于第一导电类型衬底（301）上方的第一电阻率外延层（302）；位于第一电阻率外延层（302）上方的第二电阻率外延层（303）；位于第二电阻率外延层（303）上表面两侧且由上表面延伸至第二电阻率外延层（303）底部的两沟槽区，沟槽内生成有第二导电类型的第三电阻率外延层（304）；由第四电阻率外延层（305）上表面两侧注入，且与两沟槽内的第三电阻率外延层（304）相连的阱区（306）。兼顾工艺流程的成本的同时方便制备；同时由于半超结结构的存在使VDMOS器件正向导通电阻大幅降低，单位面积电流导通能力更强。

Description

一种浅沟槽半超结VDMOS器件及其制造方法
相关申请的交叉引用
本专利申请要求于2014年10月15日提交的、申请号为201410547047.X、申请人为无锡华润华晶微电子有限公司、发明名称为“一种浅沟槽半超结VDMOS器件及其制造方法”的中国专利申请的优先权，该申请的全文以引用的方式并入本文中。
技术领域
本发明涉及半导体器件及其制造工艺技术领域，尤其是涉及一种浅沟槽半超结VDMOS器件及其制造方法。
背景技术
VDMOS(Vertical Double-diffused Metal Oxide Semiconductor，垂直双扩散金属氧化物半导体)器件，是同时具有双极型晶体管和普通MOS器件的优点的功率半导体器件。与双极型晶体管相比，它的开关速度快，开关损耗小，输入阻抗高，驱动功率小，频率特性好，跨导线性度高，没有双极型功率器件的二次击穿问题，安全工作区大。因此，不论是开关应用还是线性应用，VDMOS器件都是理想的功率半导体器件。
对于VDMOS器件而言，它的一个重要指标是导通电阻。随着VDMOS器件的发展，其结构不断地得到改进，以尽可能地降低导通电阻，从而提高导通电流的能力。
现有的VDMOS器件结构如图1所示，以N型VDMOS器件为例，包括：
基底，所述基底包括本体层101和所述本体层之上的外延层102，所述本体层101包括漏区，其中，本体层101和外延层102为N型掺杂；
位于外延层102内的第一体区103和第二体区104，所述第一体区103和第 二体区104的掺杂状态相同，为P型掺杂；
位于第一体区103内的第一源区105，位于第二体区104内的第二源区106，所述第一源区105和第二源区106的掺杂状态相同，为N型掺杂。
传统结构的VDMOS，随着击穿电压的提高，因为外延层掺杂浓度较低而且厚度也比较大，导致导通电阻将会很大，这就是通常所说的“硅极限”(“Si Limit”)，导通电阻随着耐压成2.5次方的关系增加。即导通电阻随着耐压的提高而迅速增加；同时，其正向导通电阻很高，导致需要大的芯片面积。由此可见，传统VDMOS器件具有导通电阻高的缺陷。
发明内容
有鉴于此，本发明提供一种浅沟槽半超结VDMOS器件及其制造方法，以此来解决传统结构的VDMOS器件正向导通电阻过大，单位面积电流导通能力弱等技术问题。
一种浅沟槽半超结VDMOS器件，包括：
第一导电类型衬底；
位于所述第一导电类型衬底上方的第一电阻率外延层，且所述第一导电类型衬底与第一电阻率外延层的导电类型相同；
位于所述第一电阻率外延层上方的第二电阻率外延层，且所述第一电阻率外延层与第二电阻率外延层的导电类型相同；
由所述第二电阻率外延层上表面延伸至第二电阻率外延层底部的两个第三电阻率外延层，两个第三电阻率外延层间隔设置；且所述第三电阻率外延层的导电类型与所述第二电阻率外延层的导电类型相反；
位于所述第二电阻率外延层上方的第四电阻率外延层，且所述第四电阻率外延层的导电类型与所述第二电阻率外延层的导电类型相同；
由第四电阻率外延层上表面注入，且与所述两个第三电阻率外延层相连的两个阱区，所述阱区的导电类型与所述第三电阻率外延层导电类型相同；
位于所述两个阱区上方的第一导电类型的第一源区和第二源区，以及位于所述第一源区和第二源区表面的源极金属层；
位于所述第一导电类型衬底下方的漏极金属层；位于所述第一源区和第二源区之间，且位于所述第四电阻率外延层上方的栅极区，以及位于栅极区上表面的栅极金属层。
进一步的，所述第一电阻率外延层的电阻率为5-20欧姆·厘米；所述第二电阻率外延层的电阻率为2-10欧姆·厘米；所述沟槽内的第三电阻率外延层的电阻率为2-10欧姆·厘米；所述第四电阻率外延层的电阻率为2-10欧姆·厘米。
进一步的，所述第二电阻率外延层上表面与第三电阻率外延层上表面在同一平面内。
一种浅沟槽半超结VDMOS器件的制造方法，包括：
提供第一导电类型衬底；
在所述第一导电类型衬底上方生成第一电阻率外延层，且所述第一导电类型衬底与第一电阻率外延层的导电类型相同；
在第一电阻率外延层生成第二电阻率外延层，且所述第一电阻率外延层与第二电阻率外延层的导电类型相同；
在所述第二电阻率外延层上表面且由上表面延伸至第二电阻率外延层底部刻制两沟槽区，两沟槽区间隔设置，两沟槽内生成第二导电类型的第三电阻率外延层，且所述第三电阻率外延层的导电类型与所述第二电阻率外延层的导电类型相反；
在所述第二电阻率外延层上方生成第四电阻率外延层，且所述第四电阻率 外延层的导电类型与所述第二电阻率外延层的导电类型相同；
在第四电阻率外延层上表面注入，且与所述沟槽内的第三电阻率外延层相连的两个阱区，所述阱区的导电类型与所述第三电阻率外延层导电类型相同；
在所述两个阱区上方生成第一导电类型的第一源区和第二源区；
在所述第一源区和第二源区之间，且位于所述第四电阻率外延层上方生成栅极区。
分别在所述第一导电类型衬底下方形成漏极金属层；在所述栅极区上方形成栅极金属层；在第一源区和第二源区上方形成源极金属层；在所述衬底下方形成漏极金属层。
进一步的，所述第一电阻率外延层的电阻率为5-20欧姆·厘米；所述第二电阻率外延层的电阻率为2-10欧姆·厘米；所述沟槽内的第三电阻率外延层的电阻率为2-10欧姆·厘米；所述第四电阻率外延层的电阻率为2-10欧姆·厘米。
进一步的，所述沟槽的宽度为0-10um之间，深度为0-30um之间。
进一步的，所述沟槽内生成的第三电阻率外延层，超出第二电阻率外延层上表面部分经过机械抛光或者化学刻蚀后，使第二电阻率外延层上表面与第三电阻率外延层上表面在同一平面上。
优选的，所述阱区的生成方法为：在第四电阻率外延层上，利用光刻胶作为阻挡层，在所述沟槽上方注入与沟槽内导电类型相同的杂质离子，经热退火后即形成阱区。
本发明涉及半导体技术领域，具体地说是公开了一种浅沟槽半超结VDMOS器件及其制造方法。本发明通过在传统VDMOS结构中引入一个浅的沟槽区，里面填上适当电阻率的某一导电类型的外延层，经化学机械抛光(CMP)或化学刻蚀后，使得该外延层仅留在沟槽内。然后再生长具有与上述相反导电类型的外延 层，接着利用光刻胶作为阻挡层，在沟槽内的外延层上方，注入与该外延层相同导电类型的杂质离子，经热退火后形成阱区，经过一定的热过程，该阱区和沟槽内的外延层相连，使原来传统结构VDMOS变成半超结的结构。本发明中，浅沟槽中填入某一导电类型的外延层，并与其上方具有相同导电类型的阱区相连形成一个柱，此柱的深度与传统的超结器件结构相比，要浅很多，故我们称其为半超结；其与传统的超结VDMOS器件相比，兼顾了工艺流程的成本，方便制备；同时由于半超结结构的存在，可以实现VDMOS中单位面积的电场强度的提高，即耐压能力增强，从而可使用具有更低电阻率的外延，大大降低导通电阻的内阻，使正向导通电阻大幅降低，单位面积电流导通能力更强。
附图说明
下面结合附图作进一步说明，在附图中，
图1是现有技术中VDMOS管的结构示意图；
图2为本发明实施例提供的浅沟槽半超结VDMOS器件的结构示意图；
图3为本发明实施例提供的N型浅沟槽半超结VDMOS器件的制造方法流程图；
图3A至图3F为本发明实施例提供的VDMOS器件制造方法各步骤中浅沟槽半超结VDMOS器件的剖面图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体的细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其他方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施 例的限制。
正如背景技术部分所述，传统的VDMOS的导通电阻随耐压的增长受硅极限的限制，即导通电阻随着耐压的提高而迅速增加，且为了防止电阻区被击穿，器件的横向尺寸不能做的太小，进而使得器件元胞占用面积大，导致基底表面的利用率低。对于超结VDMOS器件，虽然减小了导通电阻，但是制造工艺复杂，不能够得到大范围使用。
目前，在VDMOS器件中，应用最广泛的属于N型VDMOS器件。此处就以N型浅沟槽半超结VDMOS器件的条形元胞结构及其制作方法作为具体实施例来解释本发明。需要说明的是，本发明不限于N型浅沟槽半超结VDMOS器件的条形元胞结构及其制作方法，对于其他类型的VDMOS器件的条形元胞结构，本发明同样适用。
基于此，本发明实施例提供了一种浅沟槽半超结VDMOS器件，其结构如图2所示，包括：
第一导电类型N衬底301；
位于所述第一导电类型N衬底上方的电阻率约为5-20欧姆·厘米的N型第一电阻率外延层302；
位于所述N型第一电阻率外延层上方的电阻率约为2-10欧姆·厘米的N第二电阻率外延层303；
由所述N型第二电阻率外延层303上表面延伸至第二电阻率外延层底部的两个P型第三电阻率外延层304，两个第三电阻率外延层间隔设置；
位于所述N型第二电阻率外延层303上方生成N型第四电阻率外延层305，之后利用光刻胶作为阻挡层，由第四电阻率外延层305表面注入，且与所述第三电阻率外延层304相连的两P型阱区306；
另外，本实施例中的VDMOS器件还包括：位于所述第一导电类型衬底301下方的漏极金属层311；位于所述两P型阱区306上方的具有第一导电类型的第一源区313和第二源区313，以及位于所述第一源区313和第二源区313表面的源极金属层307；位于所述第一源区313和第二源区313之间，且位于所述第四电阻率外延层上方的栅极区308，以及位于栅极区上表面的栅极金属层310。
需要说明的是，以上是以N型的VDMOS器件为例来说明本发明的具体结构和掺杂类型等，而实质上，本发明所公开的VDMOS器件的结构同样适用于P型VDMOS器件，即第一导电类型可以是N型，第二导电类型为P型；或者第一导电类型可以是P型，第二导电类型为N型。
针对本实施例所提供的N型浅沟槽半超结VDMOS器件，可知所述P型电阻率外延层304与其上方的P阱相连形成一个P柱，此P柱的深度与传统的超结器件结构相比，要浅很多，故我们称其为半超结。该半超结的器件结构，可以实现单位面积的电场强度的提高，即耐压能力增强，从而可使用更低电阻的外延掺杂，大大降低导通电阻。
利用该实施例N型浅沟槽半超结VDMOS经过实验室测试，与传统的DMOS对比，可以如下数据对比表；其中BV是器件的击穿电压，Rsp是单位面积上的导通电阻，Vth是阈值电压。
  BV/V Rsp/Ω·cm2 Vth/V
传统DMOS 667 82.5 3.2
浅沟槽半超结VDMOS 665 58.1 3.3
通过上述表格，可以清楚的看出，相比传统的DMOS，该发明实施例提供的N型浅沟槽半超结的VDMOS器件使正向导通电阻大大降低。
半超结器件特性介于传统的超结和传统的平面高压DMOS之间，虽然其单位 面积的导通电阻相比超结的导通电阻较大，但仍然明显比传统的平面器件低30-40％之间，而且其体二极管的特性也比较接近与传统的DMOS，这是它比超结有优势的地方。引入半超结后，根据超结的电荷平衡原理，P柱之间的JFET区可以用更低N型电阻率材料(相比传统的平面DMOS)来达到同样的击穿电压。因此单位面积上的电阻会明显比传统的平面DMOS更低。
实施例还公开了本发明所述的半超结VDMOS器件的制造方法，图3为浅沟槽半超结VDMOS器件的制造方法流程图；图3A至图3F为该方法各步骤的剖面图，本实施例仅以N型浅沟槽半超结的VDMOS器件为例，并结合流程图和各步骤的剖面图进行说明：
步骤1：提供N型衬底301；
参考图3A，本实施例中，对单晶硅片进行N型离子重掺杂，形成N型半导体衬底，所述N型离子为磷或砷。
步骤2：在上述N型衬底上方生成N型第一电阻率外延层302；
步骤3：在N型第一电阻率外延层302上方生成N型第二电阻率外延层303；
参考图3B，本实施例采用外延法在N型衬底上方外延生成N型单晶硅层，形成N型第一电阻率外延层302，第一电阻率外延层的掺杂离子与N型衬底中的离子相同，可选的，第一电阻率外延层的电阻率为5-20欧姆·厘米；同上，可以在上述第一电阻率外延层302上方生成N型第二电阻率外延层303，且生成的电阻率为2-10欧姆·厘米。
步骤4：在所述的N型第二电阻率外延层303上表面两侧且由上表面延伸至第二电阻率外延层底部刻制两沟槽区312；
步骤5：在上述浅沟槽内注入P型第三电阻率外延层304；
参考图3C，本发明参考实施例中，即在所形成的N型第二电阻率外延层303 上刻制两沟槽312，沟槽的宽度在0-10um之间，深度在0-30um之间；在本发明所提供的实施例中，利用离子注入法向上述所形成的两浅沟槽内注入P型外延层304，并且经过化学机械抛光或者化学刻蚀，使得P型外延仅留在沟槽内；本步骤中注入的P型离子可以为硼或铟。
步骤6：在所述N型第二电阻率外延层303上表面生成N型第四电阻率外延层305；
步骤7：在N型第四电阻率外延层305上表面两侧注入，且与所述两沟槽内的第三电阻率外延层304相连的两P型阱区。
参考图3D，在本发明所提供的实施例中，首先在上诉N型第二电阻率外延层303上表面生成N型第四电阻率外延层305，且生成的电阻率为2-10欧姆·厘米，在N型第四电阻率外延层305上，利用光刻胶作为阻挡层，由其外延层表面注入，且在所述沟槽内P区上方，经热退火后形成P阱306，且P阱306和沟槽内的P区相连。且所述沟槽内生成的第三电阻率外延层303，超出第二电阻率外延层303上表面部分经过机械抛光或者化学刻蚀后，使得P型外延仅留在沟槽内，保证第二电阻率外延层303上表面与第三电阻率外延层304上表面在同一平面上。
步骤8：在上述第四电阻率外延层305表面形成栅极区308；
参考图3E，本实施例中，在第四电阻率外延层上方一次性生长栅氧化层308，栅氧化层308至少包括氧化硅，栅氧化层308下表面两端与P型阱区部分接触；在栅氧化层308上方淀积多晶硅层309，且多晶硅层309可采用低压化学气相淀积法形成。采用光刻工艺在多晶硅层表面形成具有栅区图案的光刻胶层，以具有栅区图案的光刻胶层为掩膜，采用干法刻蚀的方式同时刻蚀掉未被光刻胶层覆盖的多晶硅层和其下方的栅氧化层308，暂时保留光刻胶层。
步骤9：在所述两P型阱区上方生成两N型源区：第一源区313和第二源区313；
步骤10：分别在上述栅极区308上方、两N型源区313上方和N型衬底301下方形成栅极金属层310、源极金属层307和漏极金属层311。
参考图3F，本实施例中，在器件的上表面及背面淀积金属层，形成金属层的方法可以为金属化学气相淀积法，在多晶硅层309上方形成的金属层为栅极金属层310，在N型源区上方形成的金属层为源极金属层307，在N型衬底301背面形成的金属层为漏极金属层311。栅极区和栅极金属层310构成了栅极G，第一源区313、第二源区313与源极金属层307构成了源极S，N型衬底301和漏极金属层311构成了漏极D。
需要说明的是，本实施例中的基底可以包括半导体元素，例如单晶、多晶或非晶结构的硅或硅锗(SiGe)，也可以包括混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、砷化镓或锑化镓、合金半导体或其组合；也可以是绝缘体上硅(SOI)。此外，半导体基底还可以包括其他的材料，例如外延层或掩埋层的多层结构。虽然在此描述了可以形成基底的材料的几个示例，但是可以作为半导体基底的任何材料均落入本发明的精神和范围。
本实施例公开了该浅沟槽半超结VDMOS管的制造方法，简单的说，是在传统的VDMOS器件的基础上引入了一个浅沟槽结构；具体到本实施例，即为在N型外延层303上刻制浅沟槽，之后采用离子注入或其他方式向该浅沟槽312填上适当电阻率的P型外延，为了确保P型外延仅留在该浅沟槽内，在沟槽表面采用化学机械(CMP)或者化学刻蚀等方式。之后再在N型外延层302上生成N型外延305，之后注入P阱306，经过热过程，使P阱与上述沟槽内的P型外延相连，生成半超结。
以上所述实施例，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可以利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (8)

  1. 一种浅沟槽半超结VDMOS器件，其特征在于，包括：
    第一导电类型衬底；
    位于所述第一导电类型衬底上方的第一电阻率外延层，且所述第一导电类型衬底与第一电阻率外延层的导电类型相同；
    位于所述第一电阻率外延层上方的第二电阻率外延层，且所述第一电阻率外延层与第二电阻率外延层的导电类型相同；
    由所述第二电阻率外延层上表面延伸至第二电阻率外延层底部的两个第三电阻率外延层，两个第三电阻率外延层间隔设置；且所述第三电阻率外延层的导电类型与所述第二电阻率外延层的导电类型相反；
    位于所述第二电阻率外延层上方的第四电阻率外延层，且所述第四电阻率外延层的导电类型与所述第二电阻率外延层的导电类型相同；
    由第四电阻率外延层上表面注入，且与所述两个第三电阻率外延层相连的两个阱区，所述阱区的导电类型与所述第三电阻率外延层导电类型相同；
    位于所述两个阱区上方的第一导电类型的第一源区和第二源区，以及位于所述第一源区和第二源区上表面的源极金属层；
    位于所述第一导电类型衬底下方的漏极金属层；位于所述第一源区和第二源区之间，且位于所述第四电阻率外延层上方的栅极区，以及位于栅极区上表面的栅极金属层。
  2. 根据权利要求1所述的浅沟槽半超结VDMOS器件，其特征在于，所述第一电阻率外延层的电阻率为5-20欧姆·厘米；所述第二电阻率外延层的电阻率为2-10欧姆·厘米；所述第三电阻率外延层的电阻率为2-10欧姆·厘米；所述第四电阻率外延层的电阻率为2-10欧姆·厘米。
  3. 根据权利要求1所述的浅沟槽半超结VDMOS器件，其特征在于，所述第 二电阻率外延层上表面与第三电阻率外延层上表面在同一平面内。
  4. 一种浅沟槽半超结VDMOS器件的制造方法，其特征在于，包括：
    提供第一导电类型衬底；
    在所述第一导电类型衬底上方生成第一电阻率外延层，且所述第一导电类型衬底与第一电阻率外延层的导电类型相同；
    在第一电阻率外延层生成第二电阻率外延层，且所述第一电阻率外延层与第二电阻率外延层的导电类型相同；
    在所述第二电阻率外延层上表面且由上表面延伸至第二电阻率外延层底部刻制两沟槽区，两沟槽区间隔设置，两沟槽内生成第二导电类型的第三电阻率外延层，且所述第三电阻率外延层的导电类型与所述第二电阻率外延层的导电类型相反；
    在所述第二电阻率外延层上方生成第四电阻率外延层，且所述第四电阻率外延层的导电类型与所述第二电阻率外延层的导电类型相同；
    在第四电阻率外延层上表面注入，且与所述沟槽内的第三电阻率外延层相连的两个阱区，所述阱区的导电类型与所述第三电阻率外延层导电类型相同；
    在所述两个阱区上方生成第一导电类型的第一源区和第二源区；
    在所述第一源区和第二源区之间，且位于所述第四电阻率外延层上方生成栅极区；
    分别在所述第一导电类型衬底下方形成漏极金属层；在所述栅极区上方形成栅极金属层；在第一源区和第二源区上方形成源极金属层；在所述衬底下方形成漏极金属层。
  5. 根据权利要求4所述的浅沟槽半超结VDMOS器件的制造方法，其特征在于，所述第一电阻率外延层的电阻率为5-20欧姆·厘米；所述第二电阻率外延 层的电阻率为2-10欧姆·厘米；所述沟槽内的第三电阻率外延层的电阻率为2-10欧姆·厘米；所述第四电阻率外延层的电阻率为2-10欧姆·厘米。
  6. 根据权利要求4所述的浅沟槽半超结VDMOS器件的制造方法，其特征在于，所述沟槽的宽度为0-10um之间，深度为0-30um之间。
  7. 根据权利要求4-6任一所述的浅沟槽半超结VDMOS器件的制造方法，其特征在于，所述沟槽内生成的第三电阻率外延层，超出第二电阻率外延层上表面部分经过机械抛光或者化学刻蚀后，使第二电阻率外延层上表面与第三电阻率外延层上表面在同一平面上。
  8. 根据权利要求4-6任一所述的浅沟槽半超结VDMOS器件的制造方法，其特征在于，所述阱区的生成方法为：在第四电阻率外延层上，利用光刻胶作为阻挡层，在所述沟槽上方注入与沟槽内导电类型相同的杂质离子，经热退火后即形成阱区。
PCT/CN2014/095928 2014-10-15 2014-12-31 一种浅沟槽半超结vdmos器件及其制造方法 WO2016058277A1 (zh)

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