CN109065623A - 一种碳化硅金属氧化物半导体场效应晶体管及其制造方法 - Google Patents

一种碳化硅金属氧化物半导体场效应晶体管及其制造方法 Download PDF

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CN109065623A
CN109065623A CN201810650037.7A CN201810650037A CN109065623A CN 109065623 A CN109065623 A CN 109065623A CN 201810650037 A CN201810650037 A CN 201810650037A CN 109065623 A CN109065623 A CN 109065623A
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杨同同
柏松
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CETC 55 Research Institute
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Abstract

本发明公开了一种碳化硅金属氧化物半导体场效应晶体管及其制备方法，该碳化硅金属氧化物半导体场效应晶体的结构包括外延层、漏极、第一导电类型阱区域、第二导电类型源区域、第一导电类型重掺杂区、源电极、栅氧化层、栅电极、钝化保护层及若干个第一导电类型区域。本发明引入了第一导电类型区域，可以在增加JFET宽度的同时抑制器件栅氧内的电场强度，从而在不影响器件阻断的条件下，增加JFET区域的宽度，降低JFET区域的电阻，提升器件的导通特性。

Description

一种碳化硅金属氧化物半导体场效应晶体管及其制造方法
技术领域
本发明涉及半导体和功率半导体器件及其制备方法，尤其涉及碳化硅MOSFET器件及其制造方法。
背景技术
目前碳化硅MOSFET器件存在严重的栅氧可靠性问题。为了改善器件的可靠性，必须降低碳化硅MOSFET器件栅氧内的电场强度。
为了提升碳化硅MOSFET器件的正向导通特性，通常希望能够增加JFET区域的宽度，降低JFET区域的电阻。但是JFET宽度的增加，会使得相邻P阱对栅氧电场抑制能力减弱，从而又引起栅氧可靠性问题。
发明内容
发明目的：为了解决上述问题，本发明提出了一种碳化硅金属氧化物半导体场效应晶体管结构，解决了JFET宽度的增加，造成器件栅氧电场阻断状态时过高，而发生击穿的问题。本发明的另一目的是提供了该碳化硅金属氧化物半导体场效应晶体管的制备方法。
技术方案：本发明所述的一种碳化硅金属氧化物半导体场效应晶体管，包括：
第二导电类型外延层；
位于所述第二导电类型外延层背面的漏极；
与所述第二导电类型外延层相邻并分布于所述第二导电类型外延层两侧的第一导电类型阱区域；
位于所述第一导电类型阱区域中，靠近JFET区域的第二导电类型源区域；
位于所述第一导电类型阱区域中，远离JFET区域的第一导电类型重掺杂区；
位于所述第二导电类型源区域及所述第一导电类型重掺杂区之上的源电极；
位于JFET区域及部分所述第二导电类型源区域上方的栅氧化层；
位于所述栅氧化层之上的栅电极；
位于所述栅电极之上的钝化保护层；
位于所述第二导电类型外延层之内的若干个第一导电类型区域；
本发明优选地一种实施方式为所述第一导电类型区域掺杂浓度高于所述第二导电类型外延层。
本发明优选地一种实施方式为所述第一导电类型区域顶部延伸至所述栅氧化层下表面或与所述栅氧化层有一定距离。
本发明优选地一种实施方式为所述第一导电类型区域底部延伸至所述JFET区域底部或距离所述JFET区域底部有一定距离。
本发明优选地一种实施方式为所述第一导电类型区域位于所述JFET区域中。
本发明优选地一种实施方式为若干个所述第一导电类型区域的宽度相同。
本发明优选地一种实施方式为若干个所述第一导电类型区域的高度相同。
本发明优选地一种实施方式为所述第一导电类型区域为均匀掺杂或非均匀掺杂。
本发明适用于N型沟道MOSFET及P沟道MOSFET，进一步地，所述第一导电类型为N型，所述第二导电类型为P型；或所述第一导电类型为P型，所述第二导电类型为N型。
本发明优选地一种实施方式为所述第二导电类型外延层包括靠近所述漏极一侧的N型重掺衬底和远离所述漏极的N型轻掺杂漂移层。
本发明提供的另一种碳化硅金属氧化物半导体场效应晶体管，包括：
第二导电类型外延层；
位于所述第二导电类型外延层背面的漏极；
与所述第二导电类型外延层相邻并分布于所述第二导电类型外延层两侧的第一导电类型阱区域；
位于所述第一导电类型阱区域中，靠近JFET区域的第二导电类型源区域；
位于所述第一导电类型阱区域中，远离JFET区域的第一导电类型重掺杂区；
位于所述第二导电类型源区域及所述第一导电类型重掺杂区之上的源电极；
位于JFET区域及部分所述第二导电类型源区域上方的栅氧化层；
位于所述栅氧化层之上的栅电极；
位于所述栅电极之上的钝化保护层；
位于所述第二导电类型外延层之内的若干个第一导电类型区域；至少一个所述第一导电类型区域顶部与所述栅氧化层下表面具有一定距离。
上述碳化硅金属氧化物半导体场效应晶体管的制备方法，包括以下步骤：(1)在碳化衬底上形成外延层；(2)制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作第一导电类型阱区域；(3)去除步骤(2)中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作第二导电类型源区域；(4)去除步骤(3)中所述的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作第一导电类型重掺杂区；(5)去除步骤(4)中所述的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质；(6)通过离子注入形成第一导电类型区域；(7)去除步骤(5)中所述的掩膜介质，对器件表面进行牺牲氧化和CMP工艺，使得表面更加平整；(8)通过热氧化制作栅氧，然后制作栅电极；所述栅电极为多晶硅或金属；(9)制作源极金属化，制备钝化保护介质及漏极欧姆金属化，完成基本器件结构的制作。
有益效果：(1)本发明通过在JFET区域引入额外的注入掺杂区域，可以在增加JFET宽度的同时，很好的抑制器件栅氧的电场强度，同时也提高了器件的导通能力；(2)本发明有利于在器件正向导通特性和栅氧可靠性问题之间作更好的折中，提升器件的性能。
附图说明
图1为本发明实施例1碳化硅MOSFET器件剖面图；
图2a-l为本发明实施例1碳化硅MOSFET器件制备流程示意图；
图3为本发明实施例2碳化硅MOSFET器件剖面图；
图4a-l为本发明实施例2碳化硅MOSFET器件制备流程示意图；
图5为本发明实施例2碳化硅MOSFET器件另一种制备流程示意图；
图6为本发明JFET区域内形成的第一导电类型区域1的分布示意图；
图7为传统MOSFET结构和实例1中MOSFET结构器件阻断电场分布对比图。
具体实施方式
下面参照附图对本发明作出进一步说明，附图中所示的结构为本发明优选的实施例，然而，本发明可以有许多不同的形式实施，而不应限于本发明所列的实施例。
进一步需要说明的是，实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
本发明中，当第一导电类型为N型，则第二导电类型为P型；当第一导电类型为P型，则第二导电类型为N型。
必须指出的是，实施例中给出的制作过程可以根据实际情况作相应的修改或作顺序调整。同时为了表述方便，实施方式中仅仅以N型沟道MOSFET加以说明；针对P沟道MOSFET同样适用。
实施例中所述的第二导电类型外延层包括N型重掺衬底和N型轻掺杂漂移层，但是可以不存在N型重掺衬底。
实施例中所述的宽度是指沿X轴方向的长度，所述的高度或深度是指沿Y轴方向的长度。
实施例中所述的JFET区域的宽度是指相邻第一导电类型阱区域之间的宽度。
实施例1：本发明所述的一种碳化硅金属氧化物半导体场效应晶体管，包括外延层4及位于外延层4背面的漏极2；如图1所示，其中外延层4由N型轻掺杂漂移层41和N型重掺衬底42组成，N型轻掺杂漂移层41的厚度和掺杂浓度可根据器件的阻断电压进行选择。
P阱5与N型轻掺杂漂移层41相邻并分布于N型轻掺杂漂移层41两侧，P阱5之间的宽度为JFET区域的宽度；
第一导电类型区域1位于JFET区域内，第一导电类型区域1掺杂浓度高于N型轻掺杂漂移层41，底部高于JFET区域底部，第一导电类型区域1顶部距离栅氧化层8具有一定距离，第一导电类型区域1宽度小于JFET区域的宽度。
N+源区6位于P阱5中，靠近JFET区域；P+掺杂区3位于P阱5中，远离JFET区域；
源电极7位于N+源区6及P+掺杂区3之上；
栅氧化层8位于JFET区域及部分N+源区6上方，栅氧化层8之上为栅电极9，栅电极9之上为钝化保护层10。
如图2a-i所示，本发明实施例1结构的制备方法为：
(1)如图2a和图2b所示，在N型重掺衬底42衬底上形成N型轻掺杂漂移层41；
(2)如图2c所示，制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作P阱5；
(3)如图2d所示，去除上述步骤中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作N+源区6；
(4)如图2e所示，去除上述步骤中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作P+掺杂区3；
(5)如图2f所示，去除上述步骤中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质；
(6)如图2g所示，通过离子注入形成第一导电类型区域1；
(7)如图2h所示，去除上述步骤中的掩膜介质，对器件表面进行牺牲氧化和CMP工艺，使得表面更加平整；
(8)如图2i所示，通过热氧化制作栅氧化层8和制作栅电极9；
(9)如图2j、图2k、图2l所示，制作源电极7金属化，制备钝化保护介质10及漏极11欧姆金属化，完成基本器件结构的制作。
实施例2：本发明所述的碳化硅金属氧化物半导体场效应晶体管的另一种结构如图3所示，与实施例1结构不同的是，JFET区域内通过离子注入方式形成三个位于同一高度的第一导电类型区域1，且每个第一导电类型1的宽度不同，第一导电类型区域1掺杂浓度高于N型轻掺杂漂移层41，底部高于JFET区域底部，三个第一导电类型区域1顶部延伸至栅氧化层8下表面，即器件的表面。
如图4a-i所示，本发明实施例2结构的制备方法为：
(1)如图4a和图4b所示，在N型重掺衬底42衬底上形成N型轻掺杂漂移层41；
(2)如图4c所示，制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作P阱5；
(3)如图4d所示，去除上述步骤中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作N+源区6；
(4)如图4e所示，去除上述步骤中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作P+掺杂区3；
(5)如图4f所示，去除上述步骤中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质；
(6)如图4g所示，通过离子注入形成第一导电类型区域1；
(7)如图4h所示，去除上述步骤中的掩膜介质，对器件表面进行牺牲氧化和CMP工艺，使得表面更加平整；
(8)如图4i所示，通过热氧化制作栅氧化层8和制作栅电极9；
(9)如图4j、图4k、图4l所示，制作源电极7金属化，制备钝化保护介质10及漏极11欧姆金属化，完成基本器件结构的制作。
本发明实施例2的另一种制备方法如图5a-l所示：
(1)如图5a和图5b所示，在N型重掺衬底42衬底上形成N型轻掺杂漂移层41；
(2)如图5c所示，制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作P阱5；
(3)如图5d所示，去除上述步骤中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作N+源区6；
(4)如图5e所示，去除上述步骤中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作P+掺杂区3；
(5)如图5f所示，去除上述步骤中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质；
(6)如图5g所示，通过离子注入形成第一导电类型区域1；
(7)如图5h所示，去除上述步骤中的掩膜介质，对器件表面进行牺牲氧化和CMP工艺，使得表面更加平整；
(8)如图5i所示，通过热氧化制作栅氧化层8和制作栅电极9；
(9)如图5j、图5k、图5l所示，制作源电极7金属化，制备钝化保护介质10及漏极11欧姆金属化，完成基本器件结构的制作。
图6给出了本发明第一导电类型区域1的另一种分布形式，此外当本发明JFET区域内通过离子注入方式形成多个第一导电类型区域1，各第一导电类型区域1的宽度可以保持相等，也可以不相等，根据实际电场分布进行调整；各第一导电类型区域1的高度可以保持相等，也可以保持不相等，根据实际电场分布的要求来进行调整；各第一导电类型区域1掺杂浓度高于N型轻掺杂漂移层41，多个第一导电类型区域1的掺杂分布可以为均匀掺杂，也可以为非均匀掺杂；多个第一导电类型掺杂区域1的顶部都可以达到器件的表面，即栅氧化层8的下方。
为了进一步说明本发明对实际器件产生的效益，图7为传统MOSFET器件结构和本发明实施例1提出的MOSFET器件结构的仿真结果。仿真中针对1200V MOSFET器件，外延层厚度10μm，外延层掺杂为1e16cm-3。从仿真结果可以看出，对于传统MOSFET器件结构，栅氧内电场达到3.6MV/cm。而对于本发明实施例1的器件结构，栅氧内电场强度为1.5MV/cm。通过本发明实施例1可以显著降低栅氧电场强度，提高了器件可靠性。此时可通过调整JFET区域宽度或者JFET区掺杂来提升器件正向导通特性，提升器件的整体性能。

Claims (12)

1.一种碳化硅金属氧化物半导体场效应晶体管，其特征在于，包括：
第二导电类型外延层；
位于所述第二导电类型外延层背面的漏极；
与所述第二导电类型外延层相邻并分布于所述第二导电类型外延层两侧的第一导电类型阱区域；
位于所述第一导电类型阱区域中，靠近JFET区域的第二导电类型源区域；
位于所述第一导电类型阱区域中，远离JFET区域的第一导电类型重掺杂区；
位于所述第二导电类型源区域及所述第一导电类型重掺杂区之上的源电极；
位于JFET区域及部分所述第二导电类型源区域上方的栅氧化层；
位于所述栅氧化层之上的栅电极；
位于所述栅电极之上的钝化保护层；
位于所述第二导电类型外延层之内的若干个第一导电类型区域。
2.根据权利要求1所述的所述碳化硅金属氧化物半导体场效应晶体管，其特征在于，所述第一导电类型区域掺杂浓度高于所述第二导电类型外延层。
3.根据权利要求1所述的所述碳化硅金属氧化物半导体场效应晶体管，其特征在于，所述第一导电类型区域顶部延伸至所述栅氧化层下表面或与所述栅氧化层有一定距离。
4.根据权利要求1所述的所述碳化硅金属氧化物半导体场效应晶体管，其特征在于，所述第一导电类型区域底部延伸至所述JFET区域底部或距离所述JFET区域底部有一定距离。
5.根据权利要求1所述的碳化硅金属氧化物半导体场效应晶体管，其特征在于，所述第一导电类型区域位于所述JFET区域中。
6.根据权利要求1所述的所述碳化硅金属氧化物半导体场效应晶体管，其特征在于，若干个所述第一导电类型区域的宽度相同。
7.根据权利要求1所述的所述碳化硅金属氧化物半导体场效应晶体管，其特征在于，若干个所述第一导电类型区域的高度相同。
8.根据权利要求1所述的所述碳化硅金属氧化物半导体场效应晶体管，其特征在于，所述第一导电类型区域为均匀掺杂或非均匀掺杂。
9.根据权利要求1所述的碳化硅金属氧化物半导体场效应晶体管，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型；或所述第一导电类型为P型，所述第二导电类型为N型。
10.根据权利要求1所述的碳化硅金属氧化物半导体场效应晶体管，其特征在于，所述第二导电类型外延层包括靠近所述漏极一侧的N型重掺衬底和远离所述漏极的N型轻掺杂漂移层。
11.一种碳化硅金属氧化物半导体场效应晶体管，其特征在于，包括：
第二导电类型外延层；
位于所述第二导电类型外延层背面的漏极；
与所述第二导电类型外延层相邻并分布于所述第二导电类型外延层两侧的第一导电类型阱区域；
位于所述第一导电类型阱区域中，靠近JFET区域的第二导电类型源区域；
位于所述第一导电类型阱区域中，远离JFET区域的第一导电类型重掺杂区；
位于所述第二导电类型源区域及所述第一导电类型重掺杂区之上的源电极；
位于JFET区域及部分所述第二导电类型源区域上方的栅氧化层；
位于所述栅氧化层之上的栅电极；
位于所述栅电极之上的钝化保护层；
位于所述第二导电类型外延层之内的若干个第一导电类型区域；至少一个所述第一导电类型区域顶部与所述栅氧化层下表面具有一定距离。
12.一种碳化硅金属氧化物半导体场效应晶体管的制备方法，其特征在于，包括以下步骤：
(1)形成碳化衬底上形成外延层；
(2)制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作第一导电类型阱区域；
(3)去除步骤(2)中的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作第二导电类型源区域；
(4)去除步骤(3)中所述的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质，通过离子注入工艺制作第一导电类型重掺杂区；
(5)去除步骤(4)中所述的掩膜介质，重新制备掩膜介质，通过光刻、刻蚀等工艺后，制备注入掩膜介质；
(6)通过离子注入形成第一导电类型区域；
(7)去除步骤(5)中所述的掩膜介质，对器件表面进行牺牲氧化和CMP工艺，使得表面更加平整；
(8)通过热氧化制作栅氧，然后制作栅电极；所述栅电极为多晶硅或金属；
(9)制作源极金属化，制备钝化保护介质及漏极欧姆金属化，完成基本器件结构的制作。
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