WO2019134466A1 - 横向绝缘栅双极晶体管及其制作方法 - Google Patents

横向绝缘栅双极晶体管及其制作方法 Download PDF

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WO2019134466A1
WO2019134466A1 PCT/CN2018/117763 CN2018117763W WO2019134466A1 WO 2019134466 A1 WO2019134466 A1 WO 2019134466A1 CN 2018117763 W CN2018117763 W CN 2018117763W WO 2019134466 A1 WO2019134466 A1 WO 2019134466A1
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region
cathode
anode
buried
layer
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French (fr)
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郭厚东
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate

Definitions

  • the present disclosure relates to the field of electronic technology, but is not limited to the field of electronic technology, and in particular, to a lateral insulated gate bipolar transistor and a method of fabricating the same.
  • the Lateral Insulator Gate Bipolar Transistor is a composite power device in which a MOS gate device structure and a bipolar transistor structure are combined, and has a high input impedance and a low on-voltage drop.
  • the LIGBT is a bipolar device. When conducting, there is not only an electron current, but the anode P+ will inject holes into the drift region to generate electron current without an isolation layer. In the case of some holes, some holes will continue to be injected into the substrate, causing a considerable leakage current.
  • a lateral insulated gate bipolar transistor and a method of fabricating the same are provided in embodiments of the present disclosure.
  • Embodiments of the present disclosure provide a lateral insulated gate bipolar transistor, including:
  • a cathode P+ region and a first cathode N+ region formed in order from the left to the right in the cathode P body region, and an anode P+ region formed in the anode N buffer region;
  • a cathode disposed on an upper surface of the cathode P+ region and a portion of an upper surface of the first cathode N+ region, an upper surface of the right side of the first cathode N+ region, an upper surface of the cathode P body region, and an upper surface portion of the drift region portion a first gate, and an anode disposed on an upper surface of the anode P+ region;
  • An anode heavily doped N+ region disposed across the anode N buffer region is disposed, the upper end of the anode heavily doped N+ region is in contact with the anode, and the lower end is in contact with the buried oxide layer and the first N buried layer.
  • the embodiment of the present disclosure further provides a method for fabricating a lateral insulated gate bipolar transistor, including:
  • a cathode P body region at a left end of the semiconductor layer Forming a cathode P body region at a left end of the semiconductor layer, and forming an anode N buffer region on an upper side of a right end of the semiconductor layer, a bottom portion of the cathode P body region contacting the buried oxide layer, and the cathode P
  • the bottom of the body region is directly in contact with the upper surface of the first N buried layer to form a reverse bias PN junction, and the semiconductor layer region between the cathode P body region and the anode N buffer region is a drift region;
  • a lateral insulated gate bipolar transistor according to an embodiment of the present disclosure, and a method of fabricating the same, by forming a first N buried layer on a substrate and forming a buried oxide layer on the first N buried layer
  • the oxygen layer only partially covers the first N buried layer, and then the heavily doped N region is used at the anode to prevent holes from being implanted into the substrate, while the first N buried layer disposed under the buried oxide layer can serve as the second conductive channel. Reducing the on-state voltage drop, and contacting the substrate further enlarges the depletion region and increases the breakdown voltage.
  • the first N buried layer also forms a reverse bias PN junction with the P body region at the cathode end to prevent holes.
  • the heat generated by the work can be dissipated through the substrate, reducing the self-heating effect, improving the heat dissipation efficiency, and utilizing the substrate pressure,
  • the breakdown voltage can be further increased.
  • FIG. 1 is a schematic structural view of a lateral insulated gate bipolar transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a lateral insulated gate bipolar transistor according to an embodiment of the present disclosure
  • FIG. 3 is a schematic flow chart of a method for fabricating a lateral insulated gate bipolar transistor according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flow chart of another method for fabricating a lateral insulated gate bipolar transistor according to an embodiment of the present disclosure.
  • a SOI (Silicon-On-Insulator) isolation is proposed for this problem.
  • This method uses an oxide layer to directly isolate the substrate from the drift region, which can effectively reduce leakage current, but only drifts.
  • the area under pressure causes the breakdown voltage of the device to decrease.
  • FIG. 1 there is shown a typical lateral insulated gate bipolar transistor structure isolated by SOI (Silicon-On-Insulator, silicon on an insulating substrate), comprising a substrate 10, which may be a silicon liner. a buried oxide layer 11 formed on the substrate 10 and a drift layer 12 formed on the buried oxide layer 11.
  • SOI Silicon-On-Insulator, silicon on an insulating substrate
  • the buried oxide layer 11 isolates the substrate 10 from the drift layer 12, and the P body disposed on the left side of the drift layer 12 a region 13, a cathode P+ region 14 and a cathode N+ region 15 disposed in the P body region 13, an anode N buffer region 18 disposed on the upper right side of the drift layer 12, and an anode P+ region 19 formed in the anode N buffer region 18, and A surface oxide layer 111 formed on the upper surface of the drift layer 12, and a cathode 16, a gate electrode 17, and an anode 110 formed on the surface oxide layer 111.
  • This typical isolation structure directly isolates the substrate 10 from the drift layer 12 by the buried oxide layer 11, although the leakage current can be reduced, but since only the drift layer 12 is under pressure, the breakdown voltage is simultaneously lowered, and because the buried oxide layer 11 The thermal conductivity is poor, resulting in a self-heating effect, resulting in poor heat dissipation of the lateral insulated gate bipolar transistor.
  • the present embodiment provides a novel structure of a lateral insulated gate bipolar transistor including a substrate.
  • the substrate in this embodiment may be a silicon substrate or other types of substrates.
  • a first N buried layer on the substrate (the first N buried layer specifically doped impurity type can be flexibly set according to specific requirements), and the formed first N buried layer completely covers the upper surface of the substrate; further includes forming a buried oxide layer partially covering the first N buried layer on a buried layer, forming a drift region above the buried oxide layer, a cathode P body region formed on the left side of the drift region, and an anode formed on the upper right side of the drift region
  • the N buffer zone, the bottom of the cathode P body region directly contacts the upper surface of the first N buried layer to form a reverse bias PN junction to prevent leakage of holes, that is, the cathode P body region is located in the first N buried layer and is not buried in the oxygen layer.
  • the lateral insulated gate bipolar transistor in this embodiment further includes a cathode formed in order from the left to the right in the cathode P body region. a P+ region and a first cathode N+ region formed in the anode N buffer region Pole P + region, the P + region and the cathode of the first N + cathode region on the upper surface of the cathode flush with the surface P body region, P + anode region upper surface is flush with the upper surface of the anode buffer N.
  • the lateral insulated gate bipolar transistor in this embodiment further includes a cathode covering the upper surface of the cathode P+ region and the upper surface of the first cathode N+ region, and the cover cathode P body region is located on the upper surface of the right side of the first cathode N+ region, a first cathode N+ region portion upper surface and a first gate of the upper surface of the drift region portion, and an anode covering at least a portion of the upper surface of the anode P+ region.
  • the lateral insulated gate bipolar transistor in this embodiment further includes an anode heavily doped N+ region disposed vertically across the anode N buffer region, the upper end of the anode heavily doped N+ region is in contact with the anode, and the lower end is buried with the oxygen layer and the first buried layer contact.
  • the lateral insulated gate bipolar transistor provided in this embodiment has a buried silicon layer formed by forming a first buried layer on the substrate and forming a buried oxide layer on the first buried layer. a buried layer of N, then using a heavily doped N region at the anode to prevent holes from being implanted into the substrate, while a first buried layer of N under the buried oxide layer can serve as a second conductive channel, reducing on-state voltage drop Contact with the substrate further enlarges the depletion region and increases the breakdown voltage.
  • the first N buried layer also forms a reverse bias PN junction with the P body region at the cathode end to prevent hole leakage;
  • the layer does not completely isolate the drift region above the substrate from the substrate, so the heat generated by the work can be dissipated through the substrate, reducing the self-heating effect, improving the heat dissipation efficiency, and simultaneously utilizing the substrate pressure to further increase the breakdown voltage. .
  • the cathode P body region in this embodiment may also be disposed on the right side of the drift region, and the corresponding anode N buffer region may be disposed on the upper left side of the drift region.
  • the P body region is disposed on the left side of the drift region, and the anode N buffer is disposed on the upper right side of the drift region, which is exactly the same, and is merely a change of the direction of the setting direction.
  • the lateral insulated gate bipolar transistor may further include a second cathode N+ region formed on the left side of the cathode P+ region in the cathode P body region, and a second N buried layer formed on the left side of the cathode P body region.
  • the upper end of the second N buried layer is flush with the cathode P body region, the lower end is in contact with the first N buried layer, and further includes an upper surface covering the cathode P body region on the left side of the second cathode N+ region, and a second cathode N+ region portion a second gate of the upper surface and the upper surface of the second N buried layer portion; at this time, the cathode of the lateral insulated gate bipolar transistor covers the upper surface of the cathode P+ region, the upper surface of the first cathode N+ region portion, and simultaneously covers the second surface The upper surface of the cathode N+ zone portion.
  • the drift region is an N-type drift region, and of course, other types of drift regions may be set according to actual needs.
  • the first N buried layer may be an N buried layer in which the doping element includes the 15th (VA) group element (2), and includes, for example, a phosphorus element.
  • the thickness of the first N buried layer in this embodiment may be flexibly set according to a specific application scenario, and may be, for example, 5 um to 10 um, for example, 5 um, 6 um, 8 um, 9 um, or 10 um.
  • the second N buried layer may also be a N buried layer of the doping element including the 15th (VA) group element (2), or include other elements according to a specific application scenario; or the first N buried layer and the second N buried layer Both are doped elements including the N buried layer of the 15th (VA) group element (2).
  • the drift region, the first cathode N+ region, the second cathode N+ region, the anode N buffer region, the first N buried layer, the second N buried layer, and the anode heavily doped N+ region may be It is N type; the cathode P body region, the cathode P+ region, and the anode P+ region may specifically be P type.
  • the present embodiment further exemplifies the present disclosure by taking a specific lateral insulated gate bipolar transistor structure as an example.
  • the lateral insulated gate bipolar transistor includes a substrate 20, specifically a silicon substrate, having a first N buried layer 21 on the substrate 20, and buried above the first N buried layer 21.
  • the oxygen layer 22, the buried oxide layer 22 partially covers the first N buried layer 21; above the buried oxide layer 22 is a drift region 23, the drift region 23 may specifically be an N-type drift region; a cathode is formed on the left side of the drift region 23.
  • a cathode P+ region 25 (specifically, a heavily doped P+ region) is formed in the cathode P body region 24, and the first cathode N+ a region 281 and a first cathode N+ region 282 (specifically, a heavily doped N+ region); an anode N buffer (specifically a lightly doped N buffer) 29 formed on the upper right side of the drift region 23, and a buffer at the anode N
  • the anode P+ region 210 formed in the region 29 further includes an anode heavily doped N+ region 211 disposed vertically across the anode N buffer region 29. Specifically, as shown in FIG.
  • the anode heavily doped N+ region 211 is respectively spanned at upper and lower ends. Connected to the upper and lower sides of the anode N buffer region 29, the upper end of the anode heavily doped N+ region 211 is in contact with the anode 212 (in the specific structure, the anode heavily doped N+ region 211 upper end region and the anode 212 at least partially Stacked, the lower end of the anode heavily doped N+ region 211 extends out of the anode N buffer region 29 and is in contact with the buried oxide layer 22 and the first N buried layer 21 (in the specific structure, the anode is heavily doped with the lower end region of the N+ region 211 and the buried oxide layer 22
  • the first N buried layer 21 at least partially overlaps; the upper surface of the drift region 23 is formed with a surface oxide layer 213, and the cathode 25, the first gate 261, the second gate 262, and the anode 212 are sequentially formed on the surface oxide layer 213.
  • the upper end of the cathode P body region 24 is a double channel; the first gate 261 spans the first cathode N+ region 281, the right channel, and the drift region 23, that is, the first gate 261 covers the cathode P body region 24
  • the second gate 262 spans the second cathode N+ region 282, the left channel, and the second N buried layer 214, that is, the second gate 262 covers the cathode P body region 24 on the left side of the second cathode N+ region 282.
  • the drift region 23, the first cathode N+ region 281, the second cathode N+ region 282, the anode N buffer region 29, the first N buried layer 21, the second N buried layer 214, and the anode heavily doped N+ region 211 are N-type;
  • P substrate 20, cathode P body region 24, cathode P+ region 25, and anode P+ region 210 are P-type.
  • the lateral insulated gate bipolar transistor shown in FIG. 2 shortens the buried oxide layer 22 compared to a conventional SOI LIGBT, and uses a heavily doped N region at the anode to prevent holes from being implanted into the substrate while having a layer under the buried oxide layer.
  • the first N buried layer can serve as the second conductive path, and is in contact with the substrate to expand the depletion region and increase the breakdown voltage.
  • the cathode end also forms an inverse with the P body region.
  • the bias PN junction prevents the leakage of holes.
  • the buried oxide layer 22 does not completely isolate the drift region 23 and the substrate 20, heat generated by the operation can be dissipated through the substrate 20, reducing the self-heating effect, while the substrate is under pressure, and the breakdown is improved.
  • the voltage in addition to this, adds a conductive path that reduces the on-state voltage drop.
  • the lateral insulated gate bipolar transistor structure provided by the above embodiment can adopt various fabrication methods.
  • the present embodiment further exemplifies the present disclosure by an exemplary lateral insulated gate bipolar transistor method.
  • the manufacturing method of the lateral insulated gate bipolar transistor provided in this embodiment includes:
  • S301 Providing a substrate, which may be a silicon substrate.
  • the specific doping element specifically includes a 15th (VA) group element (2) ), for example, including phosphorus.
  • the doping concentration of the first N buried doping element is 0.9 ⁇ 10 15 cm ⁇ 3 to 1.1 ⁇ 10 15 cm ⁇ 3 , for example, 0.9 ⁇ 10 15 cm -3 , 0.95 ⁇ 10 15 cm -3 , 1.0 ⁇ 10 15 cm -3 , 1.05 ⁇ 10 15 cm -3 or 1.1 ⁇ 10 15 cm -3 and the like.
  • S303 forming a buried oxide layer covering the first N buried layer portion on the first N buried layer. Specifically, a silicon layer is further formed on the first N buried layer, and then the silicon layer is oxidized to form a buried oxide layer, and the formed buried oxide layer only partially covers the first N buried layer. Specifically, the buried oxide layer covering the first N buried layer portion may be formed by windowing or the like.
  • S304 forming a semiconductor layer on the first N buried layer and the buried oxide layer, specifically, an N-type semiconductor layer, and specifically forming a silicon layer, and then performing corresponding doping treatment on the silicon layer to obtain a semiconductor layer.
  • S305 forming a cathode P body region at a left end of the semiconductor layer, and forming an anode N buffer region on an upper side of the right end of the semiconductor layer.
  • the lower end of the cathode P body region formed in this step is in contact with the buried oxide layer, and the bottom portion thereof directly contacts the upper surface of the first N buried layer to form a reverse bias PN junction, and the semiconductor layer is located in the cathode P body region and the anode N buffer region.
  • the area between them is the drift area, as shown at 23 in Fig. 2.
  • an anode N buffer region may be formed on the upper side of the left end of the semiconductor layer, and a cathode P body region may be formed at the right end of the semiconductor layer. It should be understood that the order of forming the cathode P body region and the anode N buffer region in this embodiment is not strictly limited, and the cathode P body region may be formed first, and then the anode N buffer region may be formed, or the anode N buffer region may be formed first. Further, a cathode P body region is formed, or both are formed at the same time.
  • a corresponding doping treatment may be performed at a corresponding region on the left end of the semiconductor layer.
  • an anode N buffer region is formed on the upper side of the right end of the semiconductor layer, and the corresponding doping treatment can be performed on the corresponding region on the upper side of the right end of the semiconductor layer.
  • S306 forming a cathode P+ region and a first cathode N+ region from left to right in the cathode P body region, and forming an anode P+ region in the anode N buffer region, and forming an anode heavily doped N+ region of the vertical span N buffer region .
  • the formed cathode P+ region and the upper surface of the first cathode N+ region are flush with the upper surface of the cathode P body region, and the upper surface of the anode P+ region is flush with the upper surface of the anode N buffer region, and the anode is heavily doped with N+.
  • the upper end of the region is in direct contact with the anode region, and the lower end extends out of the anode N buffer to be in contact with the buried oxide layer and the first N buried layer.
  • the order of formation of the cathode P+ region, the first cathode N+ region, the anode P+ region, and the anode heavily doped N+ region in this embodiment is not strictly shown, and can be flexibly selected according to actual conditions.
  • S307 forming a cathode covering the upper surface of the cathode P+ region and the upper surface of the first cathode N+ region, covering the upper surface of the cathode P body region on the right side of the first cathode N+ region, the upper surface of the first cathode N+ region portion, and the drift region portion a first gate of the upper surface and an anode covering at least a portion of the upper surface of the anode P+ region.
  • the method before performing the foregoing S307, the method further includes:
  • the surface oxide layer will drift region, cathode P body region, cathode P+ region, first cathode N+ region, anode N buffer region, anode P+ region, and upper surface of the anode heavily doped N+ region cover.
  • a cathode P+ region can be formed at an intermediate position in the cathode P body region, and formed on the right side of the cathode P+ region.
  • the first cathode N+ region forms a cathode P+ region, and the upper surface of the first cathode N+ region is flush with the upper surface of the cathode P body region.
  • the second cathode N+ region may be formed in a region of the cathode P body region located on the left side of the cathode P+ region, and the semiconductor composition between the left side of the semiconductor layer and the left side of the cathode P body region is The second N buried layer, as shown by 214 in FIG. 2, when the cathode P body region is formed at the left end of the semiconductor layer, is not formed immediately adjacent to the left edge of the semiconductor layer, but has a certain distance from the left edge of the semiconductor. The size of the distance can be flexibly set.
  • it may further include forming a second gate covering the upper surface of the cathode P body region on the left side of the second cathode N+ region, the upper surface of the second cathode N+ region portion, and the upper surface of the second N buried layer portion;
  • the cathode simultaneously covers the upper surface of the cathode P+ region, the upper surface of the first cathode N+ region portion, and the upper surface of the second cathode N+ region portion.
  • the doping concentration of the first N buried region, the doping concentration of the N semiconductor layer, the anode N buffer region, the doping concentration of the cathode P body region, the first cathode N+ region and the second cathode N+ region can be flexibly set according to specific application requirements.
  • the present embodiment specifically takes a silicon substrate as an example, and describes a manufacturing method process of the dual-channel-based partial SOLSI IGBT device shown in FIG. 2 in the first embodiment as an example, as shown in FIG. 4, including :
  • S401 Performing N doping on the SOI silicon substrate to fabricate the first N buried layer.
  • S402 growing an oxide layer on the first N buried layer, the oxide layer covers the right end portion of the first N buried layer, and the left end portion is not covered.
  • S403 epitaxially depositing an N-type semiconductor layer on the first N buried layer and the oxide layer.
  • S404 implanting an anode lightly doped N buffer in the N-type semiconductor layer.
  • S405 implanting a cathode lightly doped P body region in the N-type semiconductor layer.
  • S406 implanting a cathode heavily doped N+ region into the first cathode N+ region and a second N+ region in the cathode lightly doped P body region, and implanting an anode heavily doped N+ region at the anode end.
  • S407 injecting a cathode heavily doped P+ region into the cathode lightly doped P body region, and implanting an anode heavily doped P+ region in the anode lightly mixed N buffer region.
  • S409 manufacturing an electrode cathode, a first gate, a second gate, and an anode on the surface.
  • the doping concentration of the first N buried region is 1 ⁇ 10 15 cm ⁇ 3
  • the doping concentration of the N-type semiconductor layer ie, the first N buried layer
  • N buffer zone The doping concentration is 3 ⁇ 10 17 cm ⁇ 3
  • the doping concentration of the P body region is 1 ⁇ 10 17 cm ⁇ 3
  • the doping concentration of the cathode heavily doped N+ region, the cathode heavily doped P+ region, and the anode heavily doped P+ region is 1 ⁇ 1021 cm -3
  • the doping concentration of the anode heavily doped N + region is 5 ⁇ 10 20 cm -3 .
  • the lateral insulated gate bipolar transistor provided by the embodiment has a shorter buried oxide layer, which is beneficial to conduction of heat to the substrate during operation, thereby reducing self-heating effect.
  • the substrate participates in the pressure, so the breakdown voltage can be greatly improved. Simultaneously having two conductive paths increases the current characteristics of the device and reduces the on-state voltage drop.

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Abstract

一种横向绝缘栅双极晶体管及其制作方法。横向绝缘栅双极晶体管包括：衬底（20），形成于衬底（20）上的第一N埋层（21），形成于第一N埋层（21）上将第一N埋层（21）部分覆盖的埋氧层（22），形成于埋氧层（22）之上的漂移区（23），形成于漂移区（23）左侧的阴极P体区（24），以及阳极N缓冲区（29），阴极P体区（24）的下端与埋氧层（22）接触，且阴极P体区（24）的底部直接与第一N埋层（21）的上表面接触形成反偏PN结；在阴极P体区（24）内从左往右依次形成的阴极P+区（25）以及第一阴极N+区（281），在阳极N缓冲区（29）内的阳极P+区（210）；在阴极P+区（25）上表面和第一阴极N+区（281）的部分上表面的阴极（27），在第一阴极N+区（281）右侧上表面、阴极P体区（24）的上表面和漂移区（23）部分上表面部分的第一栅极（261），以及在阳极P+区（210）的上表面的阳极（212）；竖跨阳极N缓冲区（29）的阳极重掺杂N+区（211）。

Description

横向绝缘栅双极晶体管及其制作方法
相关申请的交叉引用
本申请基于申请号为201810007205.0、申请日为2018年01月04日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及电子技术领域但不限于电子技术领域，尤其涉及一种横向绝缘栅双极晶体管及其制作方法。
背景技术
横向绝缘栅双极晶体管LIGBT((Lateral Insulator Gate Bipolar Transistor))是MOS栅器件结构与双极晶体管结构相结合而成的复合型功率器件，具有高输入阻抗和低导通压降的特点。和横向扩散金属氧化物半导体LDMOS(Lateral Diffusion MOS)不同的是LIGBT是一种双极型器件，导通时不仅有电子电流，阳极P+会向漂移区注入空穴产生电子电流，在没有隔离层的情况下部分空穴会继续向衬底注入，造成相当大的漏电流。
发明内容
本公开实施例提供的一种横向绝缘栅双极晶体管及其制作方法。
本公开实施例提供一种横向绝缘栅双极晶体管，包括：
衬底，形成于所述衬底上的第一N埋层，形成于所述第一N埋层上将所述第一N埋层部分覆盖的埋氧层，形成于所述埋氧层之上的漂移区，形 成于所述漂移区左侧的阴极P体区，以及形成于所述漂移区右上侧的阳极N缓冲区，所述阴极P体区的下端与所述埋氧层接触，且所述阴极P体区的底部直接与所述第一N埋层的上表面接触形成反偏PN结；
在所述阴极P体区内从左往右依次形成的阴极P+区以及第一阴极N+区，在所述阳极N缓冲区内形成的阳极P+区；
设置在所述阴极P+区上表面和第一阴极N+区的部分上表面的阴极，设置在所述第一阴极N+区右侧上表面、阴极P体区的上表面和漂移区部分上表面部分的第一栅极，以及设置在所述阳极P+区的上表面的阳极；
竖跨所述阳极N缓冲区设置的阳极重掺杂N+区，所述阳极重掺杂N+区上端与所述阳极接触，下端与所述埋氧层和所述第一N埋层接触。
本公开实施例还提供一种横向绝缘栅双极晶体管制作方法，包括：
在衬底上形成第一N埋层；
在所述第一N埋层上形成将所述第一N埋层部分覆盖的埋氧层；
在所述第一N埋层和所述埋氧层之上形成半导体层；
在所述半导体层的左端形成阴极P体区，并在所述半导体层的右端上侧形成阳极N缓冲区，所述阴极P体区的底部与所述埋氧层接触，且所述阴极P体区的底部直接与所述第一N埋层的上表面接触形成反偏PN结，所述阴极P体区和所述阳极N缓冲区之间的半导体层区域为漂移区；
在所述阴极P体区内从左往右形成阴极P+区以及第一阴极N+区，并在所述阳极N缓冲区内形成阳极P+区，以及形成竖跨所述阳极N缓冲区设置的阳极重掺杂N+区，所述阳极重掺杂下端与所述埋氧层和所述第一N埋层接触；
在所述阴极P+区上表面和第一阴极N+区部分上表面设置阴极，在所述阴极P体区位于所述第一阴极N+区右侧的上表面、第一阴极N+区部分上表面和漂移区部分上表面设置第一栅极，以及在所述阳极P+区上表面设置阳极，所述阳极与所述阳极重掺杂N+区上端接触。
本公开的有益效果是：
根据本公开实施例提供的横向绝缘栅双极晶体管及其制作方法，通过在衬底上形成一层第一N埋层，并在第一N埋层上形成一层埋氧层，形成的埋氧层仅部分覆盖第一N埋层，然后在阳极使用重掺杂N区来阻止空穴注入衬底，同时在埋氧层下方设置的第一N埋层既能够充当第二条导电通道，减小通态压降，又与衬底相接触扩大了耗尽区，提高了击穿电压，第一N埋层在阴极端也与P体区构成了一个反偏PN结阻止了空穴的泄漏；且由于埋氧层并没有完全将衬底上方的漂移区与衬底隔离，因此工作产生的热量可以通过衬底散发出去，降低自热效应，提升散热效率，同时可以利用衬底承压，可进一步提高击穿电压。
本公开其他特征和相应的有益效果在说明书的后面部分进行阐述说明，且应当理解，至少部分有益效果从本公开说明书中的记载变的显而易见。
附图说明
图1为一种本公开实施例提供的一种横向绝缘栅双极晶体管结构示意图；
图2为本公开实施例提供的一种横向绝缘栅双极晶体管结构示意图；
图3为本公开实施例提供的一种横向绝缘栅双极晶体管制作方法流程示意图；
图4为本公开实施例提供的另一种横向绝缘栅双极晶体管制作方法流程示意图。
具体实施方式
为了使本公开的目的、技术方案及优点更加清楚明白，下面通过具体实施方式结合附图对本公开实施例作进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本公开，并不用于限定本公开。
针对该问题提出了一种SOI(Silicon-On-Insulator，绝缘衬底上的硅)隔离，这种方式用氧化层直接隔离衬底与漂移区，可以非常有效的降低漏电流，但是因为只有漂移区承压导致器件的击穿电压降低。
参见图1所示，该图所示为一种通过SOI(Silicon-On-Insulator，绝缘衬底上的硅)隔离的典型的横向绝缘栅双极晶体管结构，包括衬底10，可以是硅衬底，在衬底10上形成的埋氧层11以及在埋氧层11上形成的漂移层12，埋氧层11将衬底10和漂移层12隔离，在漂移层12左侧设置的P体区13，在P体区13内设置的阴极P+区14以及阴极N+区15，在漂移层12右上侧设置的阳极N缓冲区18以及在阳极N缓冲区18内形成的阳极P+区19，以及在漂移层12上表面形成的表面氧化层111，以及在表面氧化层111上形成的阴极16、栅极17以及阳极110。这种典型的隔离结构是用埋氧层11直接隔离衬底10与漂移层12，虽然可以降低漏电流，但是因为只有漂移层12承压因此同时降低了击穿电压，且因为埋氧层11的导热能力很差，造成自热效应，导致横向绝缘栅双极晶体管散热性差。
为了解决上述问题，本实施例提供了一种新型结构的横向绝缘栅双极晶体管，其包括衬底，本实施例中的衬底可以是硅衬底，也可以是其他类型的衬底，形成于衬底上的第一N埋层(第一N埋层具体掺的杂质类型可以根据具体需求灵活设定)，形成的第一N埋层将衬底上表面完全覆盖；还包括形成于第一N埋层上将第一N埋层部分覆盖的埋氧层，形成于埋氧层之上的漂移区，形成于漂移区左侧的阴极P体区，以及形成于漂移区右上侧的阳极N缓冲区，阴极P体区的底部直接与第一N埋层的上表面接触形成反偏PN结以阻止空穴的泄露，也即阴极P体区位于第一N埋层未被埋 氧层覆盖区域之上，且本实施例中阴极P体区的下端还与埋氧层接触；本实施例中的横向绝缘栅双极晶体管还包括在阴极P体区内从左往右依次形成的阴极P+区以及第一阴极N+区，在阳极N缓冲区内形成的阳极P+区，阴极P+区和第一阴极N+区上表面与阴极P体区上表面齐平，阳极P+区上表面与所述阳极N缓冲区上表面齐平。
本实施例中的横向绝缘栅双极晶体管还包括覆盖阴极P+区上表面和第一阴极N+区部分上表面的阴极，覆盖阴极P体区位于所述第一阴极N+区右侧的上表面、第一阴极N+区部分上表面和漂移区部分上表面的第一栅极，以及覆盖阳极P+区至少部分上表面的阳极。
本实施例中的横向绝缘栅双极晶体管还包括竖跨阳极N缓冲区设置的阳极重掺杂N+区，阳极重掺杂N+区上端与阳极接触，下端与埋氧层和第一N埋层接触。
本实施例提供的横向绝缘栅双极晶体管，通过在衬底上形成一层第一N埋层，并在第一N埋层上形成一层埋氧层，形成的埋氧层仅部分覆盖第一N埋层，然后在阳极使用重掺杂N区来阻止空穴注入衬底，同时在埋氧层下方设置的第一N埋层既能够充当第二条导电通道，减小通态压降，又与衬底相接触扩大了耗尽区，提高了击穿电压，第一N埋层在阴极端也与P体区构成了一个反偏PN结阻止了空穴的泄漏；且由于埋氧层并没有完全将衬底上方的漂移区与衬底隔离，因此工作产生的热量可以通过衬底散发出去，降低自热效应，提升散热效率，同时可以利用衬底承压，可进一步提高击穿电压。
应当理解的是，根据实际需要，本实施例中的阴极P体区也可设置于漂移区右侧，对应的阳极N缓冲区则可以设置于漂移区的左上侧，这种设置方式与将阴极P体区设置于漂移区左侧，阳极N缓冲区设置于漂移区的右上侧完全等同，仅仅是设置方向的对调改变而已。
在本实施例中，横向绝缘栅双极晶体管还可包括形成于阴极P体区内位于阴极P+区左侧的第二阴极N+区，以及形成于阴极P体区左侧的第二N 埋层，第二N埋层上端与阴极P体区齐平，下端与第一N埋层接触，以及还包括覆盖阴极P体区位于第二阴极N+区左侧的上表面、第二阴极N+区部分上表面和第二N埋层部分上表面的第二栅极；此时，横向绝缘栅双极晶体管的阴极覆盖阴极P+区上表面、第一阴极N+区部分上表面外，还同时覆盖第二阴极N+区部分上表面。
在本实施例中，漂移区为N型漂移区，当然根据实际需求也可设置为其他类型的漂移区。
本实施例中第一N埋层可为掺杂元素包括第15(VA)族元素(2)的N埋层，例如包括磷元素。本实施例中第一N埋层的厚度可以根据具体应用场景灵活设定，例如可以为5um至10um，例如可为5um、6um、8um、9um或10um等。当然，第二N埋层也可为掺杂元素包括第15(VA)族元素(2)的N埋层，或者根据具体应用场景包含其他元素；或者第一N埋层和第二N埋层都为掺杂元素包括第15(VA)族元素(2)的N埋层。
在本实施例中的一种示例中，漂移区、第一阴极N+区、第二阴极N+区、阳极N缓冲区、第一N埋层、第二N埋层、阳极重掺杂N+区可为N型；阴极P体区、阴极P+区、阳极P+区具体可为P型。
为了便于理解，本实施例结合一种具体的横向绝缘栅双极晶体管结构为示例，对本公开做进一步示例说明。参见图2所示，该横向绝缘栅双极晶体管包括衬底20，具体可为硅衬底，在衬底20上具有一层第一N埋层21；在第一N埋层21上方有埋氧层22，埋氧层22将第一N埋层21部分覆盖；在埋氧层22上方是漂移区23，该漂移区23具体可为N型漂移区；在漂移区23左侧形成有阴极P体区24，以及在P体区24左侧形成有第二N埋层214；在阴极P体区中24形成有阴极P+区25(具体可为重掺杂P+区)、第一阴极N+区281和第一阴极N+区282(具体可为重掺杂N+区)；在漂移区23右上侧形成的阳极N缓冲区(具体可为轻掺杂N缓冲区)29，以及在阳极N缓冲区29内形成的阳极P+区210，还包括竖跨阳极N缓冲区29设置的阳极重掺杂N+区211，具体的，参见图2所示，阳极重掺杂 N+区211上下两端分别跨接在阳极N缓冲区29上下两侧，阳极重掺杂N+区211上端与阳极212接触(具体结构中，阳极重掺杂N+区211上端区域与阳极212至少部分重叠)，阳极重掺杂N+区211下端延伸出阳极N缓冲区29与埋氧层22和第一N埋层21接触(具体结构中，阳极重掺杂N+区211下端区域与埋氧层22和第一N埋层21至少部分重叠)；漂移区23上表面形成有表面氧化层213，在表面氧化层213上依次形成的阴极25、第一栅极261、第二栅极262、阳极212；阴极P体区24的上端为双沟道；第一栅极261横跨第一阴极N+区281、右侧沟道、漂移区23上方，也即第一栅极261覆盖阴极P体区24位于第一阴极N+区281右侧的上表面、第一阴极N+区281部分上表面(具体为右侧部分的上表面)和漂移区部分上表面(具体为左侧部分的上表面)，第二栅极262横跨第二阴极N+区282、左侧沟道、第二N埋层214上方，也即第二栅极262覆盖阴极P体区24位于第二阴极N+区282左侧的上表面、第二阴极N+区282部分上表面(具体为左侧部分的上表面)和第二N埋层214部分上表面(具体为右侧部分的上表面)。
图2中，漂移区23、第一阴极N+区281、第二阴极N+区282、阳极N缓冲区29、第一N埋层21、第二N埋层214、阳极重掺杂N+区211为N型；P衬底20、阴极P体区24、阴极P+区25、阳极P+区210为P型。
图2所示的横向绝缘栅双极晶体管与普通的SOI LIGBT相比较，将埋氧层22缩短，在阳极使用重掺杂N区来阻止空穴注入衬底，同时在埋氧层下方有一层第一N埋层，既能够充当第二条导电通道，又与衬底相接触扩大了耗尽区，提高了击穿电压，除此之外，在阴极端也与P体区构成了一个反偏PN结阻止了空穴的泄漏。在当LIGBT工作时，由于埋氧层22并没有完全隔离漂移区23和衬底20，因此工作产生的热量可以通过衬底20散发出去，降低自热效应，同时衬底承压，提高了击穿电压，除此之外增加了一条导电通道，减小了通态压降。
上述实施例提供的横向绝缘栅双极晶体管结构可以采用各种制作方法，为了便于理解，本实施例以一种示例的横向绝缘栅双极晶体管方法对本公开做进一步示例说明。
参见图3所示，本实施例提供的横向绝缘栅双极晶体管制作方法包括：
S301：提供衬底，该衬底可以是硅衬底。
S302：在衬底上形成第一N埋层，具体可以在衬底上生成一层硅层，然后掺杂形成第一N埋层，具体掺杂元素具体包括第15(VA)族元素(2)，例如包括磷元素。在本示例中，第一N埋层掺杂元素的掺杂浓度为0.9×10 15cm -3至1.1×10 15cm -3，例如可以为0.9×10 15cm -3，0.95×10 15cm -3，1.0×10 15cm -3，1.05×10 15cm -3或1.1×10 15cm -3等等。
S303：在第一N埋层上形成将第一N埋层部分覆盖的埋氧层。具体的在第一N埋层上再生成一层硅层，然后对硅层进行氧化处理形成埋氧层，形成的埋氧层仅部分覆盖第一N埋层。具体可通过开窗等方式形成将第一N埋层部分覆盖的埋氧层。
S304：在第一N埋层和埋氧层之上形成半导体层，具体可以为N型半导体层，具体的可以先生成一层硅层，然后对硅层进行相应的掺杂处理得到半导体层。
S305：在半导体层的左端形成阴极P体区，并在半导体层的右端上侧形成阳极N缓冲区。
本步骤中形成的阴极P体区的下端与埋氧层接触，且其底部直接与第一N埋层的上表面接触形成反偏PN结，半导体层位于阴极P体区和阳极N缓冲区之间的区域为漂移区，参见图2中的23所示。
另外，应当理解的是，在本实施例中，也可在半导体层的左端上侧形成阳极N缓冲区，并在半导体层的右端形成阴极P体区。且应当理解的是，本实施例中形成阴极P体区和阳极N缓冲区的顺序并无严格限制，可以先形成阴极P体区，再形成阳极N缓冲区，也可先形成阳极N缓冲区，再形 成阴极P体区，或者二者同时形成。
在半导体层的左端形成阴极P体区时，可在半导体层的左端相应区域进行相应的掺杂处理即可。相应的，在半导体层的右端上侧形成阳极N缓冲区，可在半导体层的右端上侧相应区域进行相应的掺杂处理即可。
S306：在阴极P体区内从左往右形成阴极P+区以及第一阴极N+区，并在阳极N缓冲区内形成阳极P+区，并形成竖跨阳极N缓冲区的阳极重掺杂N+区。
本实施例中，形成的阴极P+区和第一阴极N+区上表面与所述阴极P体区上表面齐平，阳极P+区上表面与阳极N缓冲区上表面齐平，阳极重掺杂N+区上端与阳极区直接接触，下端延伸出阳极N缓冲区与所述埋氧层和第一N埋层接触。
同样，应当理解的是，本实施例中阴极P+区、第一阴极N+区、阳极P+区以及阳极重掺杂N+区的形成顺序也并无严格显示，可根据实际情况灵活选择。
S307：形成覆盖阴极P+区上表面和第一阴极N+区部分上表面的阴极，覆盖阴极P体区位于第一阴极N+区右侧的上表面、第一阴极N+区部分上表面和漂移区部分上表面的第一栅极，以及覆盖阳极P+区至少部分上表面的阳极。
同样，应当理解的是，本实施例中阴极、第一阴栅极和阳极形成顺序也并无严格显示，可根据实际情况灵活选择。
在本实施例中，在执行上述S307之前，还包括：
在半导体层之上形成表面氧化层，表面氧化层将漂移区、阴极P体区、阴极P+区、第一阴极N+区、阳极N缓冲区、阳极P+区以及阳极重掺杂N+区的上表面覆盖。
在本实施例中，在S306中的阴极P体区内形成的阴极P+区以及第一阴极N+区时，可在阴极P体区内中间位置形成阴极P+区，并在阴极P+区 右侧形成第一阴极N+区，形成的阴极P+区、第一阴极N+区上表面与阴极P体区上表面齐平。
在本实施例中，还可包括在阴极P体区内位于阴极P+区左侧的区域形成第二阴极N+区，此时半导体层的左侧与阴极P体区左侧之间的半导体构成第二N埋层，参见图2中的214所示此时阴极P体区在半导体层的左端形成时，并非紧挨半导体层左侧边缘形成，而是距离半导体左侧边缘有一定的距离，该距离的大小可灵活设定。此时还可包括形成覆盖阴极P体区位于第二阴极N+区左侧的上表面、第二阴极N+区部分上表面和第二N埋层部分上表面的第二栅极；此时的形成的阴极同时覆盖阴极P+区上表面、第一阴极N+区部分上表面和第二阴极N+区部分上表面。
在上述各步骤中，第一N埋层区的掺杂浓度、N半导体层、阳极N缓冲区的掺杂浓度，阴极P体区的掺杂浓度，第一阴极N+区和第二阴极N+区的掺杂浓度、阴极P+区的掺杂浓度、阳极P+区的掺杂浓度，阳极重掺杂N+区的掺杂浓度具体可以根据具体应用需求灵活设定。
为了便于理解，本实施例具体以硅衬底为示例，对实施例一中图2所示的基于双通道的部分SOILIGBT器件的一种制造方法过程为示例进行说明，参见图4所示，包括：
S401：在SOI硅衬底上进行N掺杂制造第一N埋层。
S402：在第一N埋层上生长氧化层，氧化层将第一N埋层的右端部分覆盖，左端部分未覆盖。
S403：在第一N埋层和氧化层上外延N型半导体层。
S404：在N型半导体层注入阳极轻掺杂N缓冲区。
S405：在N型半导体层中注入阴极轻掺杂P体区。
S406：在阴极轻掺杂P体区中注入阴极重掺杂N+区形成第一阴极N+区和第二N+区，在阳极端注入阳极重掺杂N+区。
S407：在阴极轻掺杂P体区中注入阴极重掺杂P+区，在阳极轻杂N 缓冲区中注入阳极重掺杂P+区。
S408：在表面生长氧化层。
S409：在表面制造电极阴极、第一栅极、第二栅极以及阳极。
在一种示例中，第一N埋层区的掺杂浓度为1×1015cm-3，N型半导体层(也即第一N埋层)的掺杂浓度为1×1015cm-3，N缓冲区的掺杂浓度为3×1017cm-3，P体区的掺杂浓度为1×1017cm-3，阴极重掺杂N+区、阴极重掺杂P+区、阳极重掺杂P+区的掺杂浓度为1×1021cm-3，阳极重掺杂N+区的掺杂浓度为5×1020cm-3。
本实施例提供的横向绝缘栅双极晶体管，与现有横向绝缘栅双极晶体管结构相比，一方面埋氧层更短了，有利于工作时热量的导通到衬底，从而降低自热效应，另一方面衬底参与承压，因此击穿电压可以大大提升。同时具有两个导电通道提高了器件的电流特性，减小了通态压降。
以上内容是结合具体的实施方式对本公开实施例所作的进一步详细说明，不能认定本公开的具体实施只局限于这些说明。对于本公开所属技术领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本公开的保护范围。

Claims (10)

  1. 一种横向绝缘栅双极晶体管，包括：
    衬底，形成于所述衬底上的第一N埋层，形成于所述第一N埋层上将所述第一N埋层部分覆盖的埋氧层，形成于所述埋氧层之上的漂移区，形成于所述漂移区左侧的阴极P体区，以及形成于所述漂移区右上侧的阳极N缓冲区，所述阴极P体区的下端与所述埋氧层接触，且所述阴极P体区的底部直接与所述第一N埋层的上表面接触形成反偏PN结；
    在所述阴极P体区内从左往右依次形成的阴极P+区以及第一阴极N+区，在所述阳极N缓冲区内形成的阳极P+区；
    设置在所述阴极P+区上表面和第一阴极N+区的部分上表面的阴极，设置在所述第一阴极N+区右侧上表面、阴极P体区的上表面和漂移区部分上表面部分的第一栅极，以及设置在所述阳极P+区的上表面的阳极；
    竖跨所述阳极N缓冲区设置的阳极重掺杂N+区，所述阳极重掺杂N+区上端与所述阳极接触，下端与所述埋氧层和所述第一N埋层接触。
  2. 如权利要求1所述的横向绝缘栅双极晶体管，其中，还包括形成于所述阴极P体区内位于所述阴极P+区左侧的第二阴极N+区，和形成于所述阴极P体区左侧的第二N埋层，所述第二N埋层上端与所述阴极P体区齐平，下端与所述第一N埋层接触；以及还包括在所述阴极P体区位于所述第二阴极N+区左侧的上表面、所述第二阴极N+区部分上表面和所述第二N埋层部分上表面设置的第二栅极；
    所述阴极覆盖所述阴极P+区上表面、第一阴极N+区部分上表面和第二阴极N+区部分上表面。
  3. 如权利要求1所述的横向绝缘栅双极晶体管，其中，所述漂移区为N型漂移区。
  4. 如权利要求2所述的横向绝缘栅双极晶体管，其中，所述漂移 区、第一阴极N+区、第二阴极N+区、阳极N缓冲区、第一N埋层、第二N埋层、阳极重掺杂N+区为N型；所述阴极P体区、阴极P+区、阳极P+区为P型。
  5. 如权利要求2-4任一项所述的横向绝缘栅双极晶体管，其中，所述第一N埋层和/或所述第二N埋层为掺杂元素包括第15((VA))族元素((2))的N埋层。
  6. 如权利要求1至4任一项所述的横向绝缘栅双极晶体管，其中，所述N埋层的厚度为5um至10um。
  7. 一种横向绝缘栅双极晶体管制作方法，包括：
    在衬底上形成第一N埋层；
    在所述第一N埋层上形成将所述第一N埋层部分覆盖的埋氧层；
    在所述第一N埋层和所述埋氧层之上形成半导体层；
    在所述半导体层的左端形成阴极P体区，并在所述半导体层的右端上侧形成阳极N缓冲区，所述阴极P体区的下端与所述埋氧层接触，且所述阴极P体区的底部直接与所述第一N埋层的上表面接触形成反偏PN结，所述阴极P体区和所述阳极N缓冲区之间的半导体层区域为漂移区；
    在所述阴极P体区内从左往右形成阴极P+区以及第一阴极N+区，并在所述阳极N缓冲区内形成阳极P+区，以及形成竖跨所述阳极N缓冲区设置的阳极重掺杂N+区，所述阳极重掺杂下端与所述埋氧层和所述第一N埋层接触；
    在所述阴极P+区上表面和第一阴极N+区部分上表面设置阴极，在所述阴极P体区位于所述第一阴极N+区右侧的上表面、第一阴极N+区部分上表面和漂移区部分上表面设置第一栅极，以及在所述阳极P+区上表面设置阳极，所述阳极与所述阳极重掺杂N+区上端接触。
  8. 如权利要求7所述的横向绝缘栅双极晶体管制作方法，其中，所述形成覆盖所述阴极P+区上表面和第一阴极N+区部分上表面的阴极， 覆盖所述阴极P体区位于所述第一阴极N+区右侧的上表面、第一阴极N+区部分上表面和漂移区部分上表面的第一栅极，以及覆盖所述阳极P+区至少部分上表面的阳极之前，还包括：
    在所述半导体层之上形成表面氧化层，所述表面氧化层将所述漂移区、阴极P体区、阴极P+区、第一阴极N+区、阳极N缓冲区、阳极P+区以及阳极重掺杂N+区的上表面覆盖。
  9. 如权利要求7所述的横向绝缘栅双极晶体管制作方法，其中，所述半导体层为N型半导体层；
    所述横向绝缘栅双极晶体管制作方法还包括：
    在所述阴极P体区内位于所述阴极P+区左侧的区域形成第二阴极N+区，所述半导体层的左侧与所述阴极P体区左侧之间的半导体构成第二N埋层；
    形成覆盖所述阴极P体区位于所述第二阴极N+区左侧的上表面、所述第二阴极N+区部分上表面和所述第二N埋层部分上表面的第二栅极；
    所述阴极覆盖所述阴极P+区上表面、第一阴极N+区部分上表面和第二阴极N+区部分上表面。
  10. 如权利要求7至9任一项所述的横向绝缘栅双极晶体管制作方法，其中，所述第一N埋层掺杂元素的掺杂浓度为0.9×10 15cm -3至1.1×10 15cm -3。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090315072A1 (en) * 2008-06-20 2009-12-24 Hitachi, Ltd. Semiconductor Device, Semiconductor Integrated Circuit Equipment Using the Same for Driving Plasma Display, and Plasma Display Unit
CN105074922A (zh) * 2013-06-14 2015-11-18 富士电机株式会社 半导体器件
CN105633140A (zh) * 2016-03-30 2016-06-01 南京邮电大学 一种双层部分soi ligbt器件及其制造方法
CN105789286A (zh) * 2014-12-22 2016-07-20 无锡华润上华半导体有限公司 横向绝缘栅双极型晶体管

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5055813B2 (ja) * 2006-04-10 2012-10-24 富士電機株式会社 Ｓｏｉ横型半導体装置
CN100592532C (zh) * 2007-08-28 2010-02-24 电子科技大学 具有“u”字形漂移区的半导体器件
CN101834202B (zh) * 2010-04-13 2011-11-16 东南大学 降低热载流子效应的n型横向绝缘栅双极型器件
WO2014041652A1 (ja) * 2012-09-13 2014-03-20 富士電機株式会社 半導体装置および半導体装置の製造方法
CN103762230B (zh) * 2014-01-24 2016-06-29 东南大学 N沟道注入效率增强型绝缘栅双极型晶体管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090315072A1 (en) * 2008-06-20 2009-12-24 Hitachi, Ltd. Semiconductor Device, Semiconductor Integrated Circuit Equipment Using the Same for Driving Plasma Display, and Plasma Display Unit
CN105074922A (zh) * 2013-06-14 2015-11-18 富士电机株式会社 半导体器件
CN105789286A (zh) * 2014-12-22 2016-07-20 无锡华润上华半导体有限公司 横向绝缘栅双极型晶体管
CN105633140A (zh) * 2016-03-30 2016-06-01 南京邮电大学 一种双层部分soi ligbt器件及其制造方法

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