WO2021232807A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2021232807A1
WO2021232807A1 PCT/CN2020/140321 CN2020140321W WO2021232807A1 WO 2021232807 A1 WO2021232807 A1 WO 2021232807A1 CN 2020140321 W CN2020140321 W CN 2020140321W WO 2021232807 A1 WO2021232807 A1 WO 2021232807A1
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trench
region
semiconductor device
conductive structure
electrode
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PCT/CN2020/140321
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English (en)
French (fr)
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肖魁
方冬
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华润微电子（重庆）有限公司
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Publication of WO2021232807A1 publication Critical patent/WO2021232807A1/zh

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Definitions

  • This application relates to the field of semiconductors, and in particular to a semiconductor device and a manufacturing method thereof.
  • MOS Metal Oxide Semiconductor
  • MOS Metal Oxide Semiconductor
  • MOS Metal Oxide Semiconductor
  • the conduction channel is changed from horizontal to vertical, which greatly increases the density of the conduction channel and reduces the on-resistance.
  • the trench gate structure if you want to further reduce the on-resistance, you need to increase the doping concentration of the drift region, and increasing the doping concentration will weaken the withstand voltage capability of the device. Therefore, it is limited by the withstand voltage capability. , Making it difficult to further reduce the on-resistance of the device.
  • a semiconductor device and a manufacturing method thereof are provided.
  • a semiconductor device including:
  • the drift region has the first conductivity type and is formed on the semiconductor substrate;
  • the body region has the second conductivity type and is formed on the upper surface layer of the drift region;
  • the first doped region has the first conductivity type and is formed on the upper surface layer of the body region;
  • a first trench and a second trench the first trench extends from the inside of the body region to the drift region, and the second trench penetrates the first doped region, the body region, and Extending into the drift region, the sidewalls of the first trench and the sidewalls of the second trench are both formed with an oxide layer, and the first trench is filled with a first conductive structure, the The second trench is filled with a second conductive structure;
  • a first electrode that extends to the top of the first trench and is in contact with the first doped region, the body region, and the first trench;
  • the second electrode is in contact with the semiconductor substrate.
  • a method for manufacturing a semiconductor device includes:
  • drift region Forming a drift region on the semiconductor substrate, the drift region having the first conductivity type
  • the upper surface layer of the drift region is doped with the second conductivity type to form a body region in contact with the first trench and the second trench, and the upper surface layer of the body region is doped with the first conductivity type. Doped, forming a first doped region in contact with the first trench and the second trench;
  • the height of the first conductive structure and the oxide layer in the first trench is reduced to the body region, and formed to penetrate the first doped region and part of the body region and extend to contact the top of the first trench
  • the first electrode forms a gate in contact with the second conductive structure, and a second electrode in contact with the semiconductor substrate is formed.
  • FIG. 1 is a cross-sectional view of the semiconductor device in the first embodiment
  • FIG. 2 is a cross-sectional view of the semiconductor device in the second embodiment
  • FIG. 3 is a cross-sectional view of the semiconductor device in the third embodiment
  • FIG. 5 is a flowchart of steps of a method of manufacturing a semiconductor device in an embodiment
  • 6a to 6h are structural cross-sectional views corresponding to relevant steps of a method of manufacturing a semiconductor device in an embodiment.
  • drift region 110 body region; 111 first doped region; 112 heavily doped region; 121 first trench; 122 second trench; 131 oxide layer; 131a isolation oxide layer; 131b gate oxide layer; 141 first Conductive structure; 142 second conductive structure; 150 first extension area; 160 isolation layer; 200 dielectric layer; 310 first electrode; 320 second electrode; 410 semiconductor substrate.
  • the semiconductor device includes a drift region 100 formed on the front surface of a semiconductor substrate 410.
  • the drift region 100 may be formed by epitaxial growth of the semiconductor substrate 410.
  • a body region 110 is formed on the upper surface of the drift region 100, and a first doped region 111 is formed on the upper surface of the body region 110.
  • the first doped region 111 is connected to the first electrode 310, the semiconductor substrate 410 is connected to the second electrode 320, and the first electrode 310 and the second electrode 320 form a current path through the body region 110 and the drift region 100.
  • the semiconductor device also has a first trench 121 and a second trench 122.
  • the first trench 121 extends from the body region 110 to the drift region 100, that is, the top of the first trench 121 is in the body region 110 and the first trench 121 is in the body region 110.
  • the bottom end of a trench 121 is in the drift region 100; the second trench 122 penetrates the first doped region 111 and the body region 110 and extends into the drift region 100.
  • Both the sidewalls of the first trench 121 and the second trench 122 are formed with an oxide layer 131, wherein the oxide layer formed in the first trench 121 is an isolation oxide layer 131a, and the oxide layer is formed in the second trench 122
  • the oxide layer is the gate oxide layer 131b.
  • the first trench 121 is also filled with a first conductive structure 141
  • the second trench 122 is also filled with a second conductive structure 142.
  • the gate (not shown in the figure) is in contact with the second conductive structure 142; the first electrode 310 extends to the top of the first trench 121, and is connected to the first doped region 111, the body region 110, and the first doped region 111, respectively.
  • the trench 121 is in contact, so that the first doped region 111, the body region 110 and the first conductive structure 141 in the first trench 121 can all obtain the potential of the first electrode 310.
  • the first conductive structure 141 and the second conductive structure 142 may be polysilicon.
  • a first expansion region 150 is also formed in the drift region 100, and the first expansion region 150 is located under the first trench 121 and surrounds the bottom of the first trench 121.
  • the drift region 100 and the first doped region 111 have the first conductivity type
  • the body region 110 and the first extension region 150 have the second conductivity type.
  • the first conductivity type is P-type and the second conductivity type is N-type
  • the first conductivity type is N-type and the second conductivity type is P-type.
  • the second conductive structure 142 and the gate oxide layer 131b in the second trench 122 form a trench gate structure and are connected to the gate (not shown in the figure), and are formed in the body region 110 through the trench gate structure Longitudinal conductive channel. Further, in the second trench 122, only the second conductive structure 142 can be filled to form a common trench gate structure as shown in FIG. 1.
  • the first conductive structure 141 in the first trench 121 can obtain a potential from the first electrode 310, so that the first conductive structure 141 and the isolation oxide layer 131a in the first trench 121 constitute an internal field plate, In order to adjust the electric field of the drift region 100, the depletion of the drift region 100 is enhanced.
  • the conductivity type of the first extension region 150 at the bottom of the first trench 121 is opposite to that of the drift region 100, which can further enhance the depletion of the drift region 100. In this application, by adding the inner field plate and the first expansion region, the device withstand voltage can be effectively increased.
  • the drift region of the semiconductor device in this application can increase the doping concentration, thereby To achieve the purpose of reducing the on-resistance.
  • the breakdown position is the interface between the trench gate and the drift region.
  • the first trench 121 is provided in the drift region 100 and surrounds the bottom of the first trench 121 The first extension region 150 of the, so that the breakdown position is transferred from the interface between the trench gate and the drift region to the interface between the first extension region 150 and the drift region 100, so that the breakdown is more stable.
  • a second expansion region surrounding the second trench 122 can also be formed in the drift region 100 at the bottom of the second trench 122.
  • the second expansion region has the same properties and functions as the first expansion region, and can be further Enhance the depletion of the drift zone.
  • the bottom depth of the first trench 121 and the second trench 122 are different. Specifically, the bottom depth of the first trench 121 is greater than the bottom depth of the second trench 122, so that the three-dimensional loss of the drift region 100 is The best.
  • the above-mentioned semiconductor device further includes a heavily doped region 112 formed in the body region 110 and spaced apart from the second trench 122, and the heavily doped region 112 has the second conductivity type, That is, the conductive type of the heavily doped region 112 and the body region 110 are the same, but the doping concentration of the heavily doped region 112 is higher than the doping concentration of the body region 110.
  • the first trench 121 sequentially penetrates the heavily doped region 112 and the body region 110 and extends into the drift region 100.
  • a part of the bottom of the first electrode 310 is in contact with the first trench 121 and is covered by the first trench 121.
  • the first electrode 310 here includes a metal layer on the top layer as shown in the figure and a first lead structure extending from the metal layer to the first trench 121.
  • the dielectric layer 200 is covered on the first doped region 111 and the second trench 122, and the first lead-out structure of the first electrode 310 penetrates the dielectric layer 200, the first doped region 111 and extends to the first doped region 111.
  • the top of a trench 121 is in contact with the first trench 121.
  • an oxide layer is not formed at the bottom of the first trench 121, so that the first extension region 150 is in direct contact with the first conductive structure 141.
  • the inner wall of the first trench 121 is formed with an oxide layer 131 so that the first extension region 150 is isolated from the first conductive structure 141.
  • the first electrode 310 extends to the top of the first trench 121 and contacts the first trench 121, and the first conductive structure 141 fills the first trench 121 and directly contacts the first electrode 310 To get the electric potential.
  • the first conductive structure 141 does not fill the first trench 121, an isolation layer is further provided on the top of the first conductive structure 141, the first conductive structure 141 is isolated from the first electrode 310 by the isolation layer, and, The thickness of the isolation layer needs to satisfy that the first conductive structure 141 can obtain an induced potential from the first electrode 310.
  • FIG. 1 is a schematic diagram of the structure of the semiconductor device in the first embodiment.
  • the first electrode 310 extends to the top of the first trench 121 and directly contacts the first conductive structure 141 in the first trench 121, so that the first conductive structure 141 directly obtains the potential of the first electrode 310.
  • a conductive structure 141 and an oxide layer 131 are equivalent to an internal field plate, which adjusts the electric field of the drift region 100 and enhances the depletion of the drift region 100.
  • the oxide layer 131 is formed only on the sidewall of the first trench 121, that is, the oxide layer 131 is formed on the sidewall of the first trench 121, but the bottom of the first trench 121 No oxide layer is formed.
  • the first extension area 150 is in contact with the first conductive structure 141 in the first trench 121. After the first conductive structure 141 obtains the potential from the first electrode 310, the first extension area 150 can also pass through the first conductive structure 141.
  • the conductive structure 141 acquires an electric potential to enhance the depletion of the drift region 100 by the first expansion region 150.
  • the first conductive structure 141 is in direct contact with the first electrode 310, and the first extension area 150 is in direct contact with the first conductive structure 141, so that both the first extension area 150 and the first conductive structure 141 are stronger.
  • the potential of, can increase the depletion of the drift region 100.
  • FIG. 2 is a schematic diagram of the structure of the semiconductor device in the second embodiment.
  • the second embodiment differs from the first embodiment only in that the coverage area of the oxide layer 131 in the second embodiment is different.
  • the oxide layer 131 is formed on the inner wall of the first trench 121, that is, the oxide layer 131 is formed on the sidewall and bottom of the first trench 121, the first extension area 150 and the first conductive structure 141 Isolation, thereby cutting off the leakage path of the first electrode 310, the first conductive structure 141 and the first extension region 150, and reducing the leakage.
  • FIG. 3 is a schematic diagram of the structure of the semiconductor device in the third embodiment.
  • the only difference between the third embodiment and the first embodiment is that an isolation layer 160 is formed between the first conductive structure 141 and the first electrode 310 in the third embodiment, and the first conductive structure 141 is connected to the first conductive structure through the isolation layer 160.
  • the electrodes 310 are isolated, and the thickness of the isolation layer 160 needs to be such that the first conductive structure 141 can obtain an induced potential from the first electrode 310.
  • the isolation layer 160 may be silicon oxide.
  • an isolation layer 160 is provided between the first electrode 310 and the first conductive structure 141, and the isolation layer 160 is used to cut off the leakage path of the first electrode 310, the first conductive structure 141, and the first expansion region 150 to reduce Small leakage.
  • the first conductive structure 141 can obtain the induced potential of the first electrode 310. Therefore, in this embodiment, the first conductive structure 141 and the first expansion region 150 have a certain induced potential, which can enhance the depletion of the drift region 100. .
  • FIG. 4 is a schematic diagram of the structure of the semiconductor device in the fourth embodiment.
  • the fourth embodiment differs from the first embodiment only in that, in the fourth embodiment, an isolation layer 160 is provided between the first conductive structure 141 in the first trench 121 and the first electrode 310, and the first trench 121 An oxide layer 131 is formed on the inner wall to isolate the first expansion region 150 from the first conductive structure 141.
  • the first electrode 310 is isolated from the first conductive structure 141 by the isolation structure 160, and the first conductive structure 141 is isolated from the first extension region 150 by the oxide layer 131, which further cuts off the first electrode 310 and the first conductive structure.
  • the leakage path between the structure 141 and the oxide layer 131 avoids leakage.
  • the first conductive structure 141 can obtain the induced potential of the first electrode 310, and the first expansion region 150 has no potential.
  • the above-mentioned semiconductor device may be a VDMOS (Vertical Double Diffusion Metal Oxide Semiconductor) field effect transistor.
  • the first doped region 111 is the source region, and the semiconductor substrate 410 has the first conductivity type.
  • the first electrode 310 is a source electrode, and the second electrode 320 is a drain electrode.
  • the above-mentioned semiconductor device may also be an IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor).
  • the first doped region 111 is an emitter region, and the semiconductor substrate 410 has a second Conductive type, a buffer zone is also formed between the semiconductor substrate 410 and the drift region 100, and the buffer zone has a first conductivity type.
  • the first electrode 310 is an emitter, and the second electrode 320 is a collector.
  • This application also relates to a method for manufacturing a semiconductor device. As shown in FIG. 5, the manufacturing method includes the following steps:
  • Step S510 forming a drift region on the semiconductor substrate, the drift region having the first conductivity type.
  • a semiconductor substrate 410 is provided, and a drift region 100 is formed on the semiconductor substrate 410.
  • Step S520 A first trench is opened on the drift region, and an oxide layer is formed on the inner wall of the first trench.
  • a first trench 121 is formed on the drift region 100, and an oxide layer 131 is formed on the inner wall of the first trench 121.
  • the oxide layer 131 may be formed on the inner wall of the first trench 121 by a thermal oxidation process.
  • Step S530 implanting dopant ions of the second conductivity type into the drift region through the first trench to form a first expansion region in contact with the bottom of the first trench.
  • the second conductivity type dopant ions are implanted into the drift region 100 through the first trench 121 to form a first expansion region 150 that is in contact with the bottom of the first trench 121.
  • Step S540 Filling the first conductive structure into the first trench.
  • the first conductive structure 141 is filled into the first trench 121.
  • the first conductive structure 141 may be polysilicon.
  • step S530 and step S540 the method further includes:
  • the oxide layer at the bottom of the first trench is etched to expose the first expansion area.
  • the oxide layer 131 at the bottom of the first trench 121 is dry-etched to form an opening exposing the first expansion region 150.
  • step S540 after the first conductive structure 141 is filled, the first conductive structure 141 contacts the first extension region 150.
  • Step S550 opening a second trench isolated from the first trench on the drift region, forming an oxide layer on the inner wall of the second trench, and filling the second trench with a second conductive structure.
  • the second trench 122 is continuously opened on the drift region 100, and the first trench 121 and the second trench 122 are isolated from each other.
  • An oxide layer 131 is formed on the inner wall of the second trench 122, and the second conductive structure 142 is filled in the second trench 122.
  • the oxide layer formed in the first trench 121 is the isolation oxide layer 131a
  • the oxide layer formed in the second trench 122 is the gate oxide layer 131b.
  • the second conductive structure 142 may be polysilicon.
  • Step S560 Doping the upper surface layer of the drift region with the second conductivity type to form body regions that are in contact with the first trench and the second trench, respectively, and performing the second conductive type on the upper surface layer of the body region.
  • a conductivity type is doped to form first doped regions respectively in contact with the first trench and the second trench.
  • the body region and the first doped region are continuously formed.
  • the upper surface layer of the drift region 100 is doped with the second conductivity type to form the body regions 110 respectively in contact with the first trench 121 and the second trench 122.
  • the upper surface layer of the body region 110 is continuously doped with the first conductivity type to form the first doped region 111 in contact with the first trench 121 and the second trench 122.
  • the process of forming the body region 110 is specifically a high-temperature push-well process, wherein the temperature and time of the high-temperature push-well can be adjusted according to the doping depth and doping concentration of the body region.
  • the high-temperature push-well temperature The range can be controlled between 900°C and 1200°C, and the time range of high temperature trapping can be controlled between 10min and 180min. While the above-mentioned high temperature push well forms the body region 110, the doped ions of the first expansion region 150 diffuse outward, so that the first expansion region 150 expands outward, thereby increasing the volume of the first expansion region 150.
  • Step S570 Reduce the height of the first conductive structure and the oxide layer in the first trench to the body region, and form to penetrate through the first doped region and part of the body region and extend to the first trench.
  • the first electrode in contact with the top of the trench forms a gate in contact with the second conductive structure, and a second electrode in contact with the semiconductor substrate is formed.
  • the height of the first conductive structure 141 and the oxide layer 131 in the first trench is reduced, so that the height of the overall top surface of the first trench 121 and its internal filling structure is lowered to the body region, and is in the first trench.
  • the upper part of the trench 121 penetrates the first doped region 111 and extends to the first lead-out structure where the body region 110 is in contact with the first trench. Therefore, the first lead-out structure is also in contact with the first doped region 111 and the body region 110 .
  • the top of the first lead-out structure is connected to the first metal layer, and the first lead-out structure and the first metal layer together serve as the first electrode 310.
  • the width of the first lead-out structure in the cross section of FIG. 6h is greater than the width of the first trench 121, and the first lead-out structure covers the first trench 121.
  • a gate contacting the second conductive structure 142 is also formed.
  • the first doped region 111 is the source region, and the semiconductor substrate 410 has the first conductivity type.
  • the first doped region 111 is an emitter region, the semiconductor substrate 410 has the second conductivity type, and a first conductivity type buffer zone is also formed between the semiconductor substrate 410 and the drift region 100.
  • a second trench is opened in the cell region and a second conductive structure and an oxide layer are formed in the second trench, wherein the second conductive structure is connected to the gate to form a trench gate structure,
  • the vertical conduction channel is formed by the trench gate structure, the density of the conduction channel is increased, and the on-resistance is reduced.
  • a first trench is also opened in the cell area.
  • a first conductive structure and an oxide layer are formed in the first trench.
  • the field plate adjusts the electric field of the drift zone to enhance the depletion of the drift zone.
  • a first expansion region is also formed in the cell region to surround the bottom of the trench, and the conductivity type of the first expansion region is opposite to that of the drift region.
  • the first expansion region can also enhance the depletion of the drift region.
  • the inner field plate and the first expansion region are formed on the basis of the traditional trench gate structure. Under the combined action of the inner field plate and the first expansion region, the depletion of the drift region is increased and the drift is improved. The breakdown voltage of the zone.
  • the drift region of the semiconductor device in the present application can increase the doping concentration, thereby reducing the on-resistance, that is, under the condition of the same breakdown voltage, the semiconductor device in the present application Has a lower on-resistance.

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Abstract

本申请涉及一种半导体器件及其制备方法，器件包括：漂移区(100)和形成于漂移区(100)上表层的体区(110)；形成于体区(110)上表层的第一掺杂区(111)；第一沟槽(121)，自体区(110)内延伸至漂移区(100)内，第二沟槽(122)，贯穿第一掺杂区(111)、体区(110)并延伸至漂移区(100)内，第一沟槽(121)的侧壁和第二沟槽(122)的侧壁均形成有氧化层(131)，第一沟槽(121)内填充有第一导电结构(141)，第二沟槽(122)填充有第二导电结构(142)；第一扩展区(150)，包围第一沟槽(121)的底部；栅极(图中未示出)与第二导电结构(142)接触；第一电极(310)延伸至第一沟槽(121)顶部并与第一掺杂区(111)、体区(110)和第一沟槽(121)接触；第二电极(320)与半导体衬底(410)接触。漂移区(100)、第一掺杂区(111)、具有第一导电类型，体区(110)、第一扩展区(150)具有第二导电类型。

Description

半导体器件及其制备方法
相关申请的交叉引用
本申请要求于2020年05月18日提交中国专利局、申请号为2020104188496、发明名称为“半导体器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，尤其涉及一种半导体器件及其制备方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
在MOS(Metal Oxide Semiconductor，金属氧化物半导体)管中以及具有MOS管结构的其他半导体器件中，由于器件导通时会存在一定的导通电阻，导通电阻越大，器件功耗越大，因此，需要尽量减小导通电阻。目前，通常采用沟槽栅结构，通过形成沟槽栅结构，使导通沟道由横向变成纵向，大大提高了导通沟道的密度，降低导通电阻。然而，在沟槽栅结构的基础上，若想进一步降低导通电阻，需提高漂移区的掺杂浓度，而提高掺杂浓度又会减弱器件的耐压能力，因此，受耐压能力的限制，使得进一步降低器件的导通电阻变得困难。
发明内容
根据本申请的各种实施例，提供一种半导体器件及其制备方法。
一种半导体器件，包括：
漂移区，具有第一导电类型，形成于半导体衬底上；
体区，具有第二导电类型，形成于所述漂移区的上表层；
第一掺杂区，具有第一导电类型，形成于所述体区的上表层；
第一沟槽和第二沟槽，所述第一沟槽自所述体区内部延伸至所述漂移区内，所述第二沟槽贯穿所述第一掺杂区、所述体区并延伸至所述漂移区内，所述第一沟槽的侧壁和所述第二沟槽的侧壁均形成有氧化层，且所述第一沟槽内填充有第一导电结构，所述第二沟槽填充有第二导电结构；
第一扩展区，具有第二导电类型，形成于所述第一沟槽下方的漂移区内并包围所述第一沟槽的底部；
栅极，与所述第二导电结构接触；
第一电极，延伸至所述第一沟槽顶部并与所述第一掺杂区、所述体区和所述第一沟槽接触；以及
第二电极，与所述半导体衬底接触。
一种半导体器件的制备方法，包括：
在半导体衬底上形成漂移区，所述漂移区具有第一导电类型；
在所述漂移区上开设第一沟槽，在第一沟槽的内壁形成氧化层；
通过所述第一沟槽向所述漂移区注入第二导电类型掺杂离子，形成与第一沟槽底部接触的第一扩展区；
向所述第一沟槽内填充第一导电结构；
在所述漂移区上开设与第一沟槽隔离的第二沟槽，在所述第二沟槽的内壁形成氧化层，向所述第二沟槽内填充第二导电结构；
对所述漂移区的上表层进行第二导电类型掺杂，形成与所述第一沟槽和所述第二沟槽接触的体区，对所述体区的上表层进行第一导电类型掺杂，形成与所述第一沟槽和所述第二沟槽接触的第一掺杂区；以及
削减第一沟槽内的第一导电结构和氧化层的高度至所述体区内，形成贯穿所述第一掺杂区和部分所述体区并延伸至与所述第一沟槽顶部接触的第一电极，形成与所述第二导电结构接触的栅极，形成与所述半导体衬底接触的 第二电极。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为第一实施例中半导体器件的剖面图；
图2为第二实施例中半导体器件的剖面图；
图3为第三实施例中半导体器件的剖面图；
图4为第四实施例中半导体器件的剖面图；
图5为一实施例中半导体器件的制备方法的步骤流程图；
图6a～6h为一实施例中半导体器件的制备方法相关步骤对应的结构剖视图。
标号说明
100漂移区；110体区；111第一掺杂区；112重掺杂区；121第一沟槽；122第二沟槽；131氧化层；131a隔离氧化层；131b栅氧层；141第一导电结构；142第二导电结构；150第一扩展区；160隔离层；200介质层；310第一电极；320第二电极；410半导体衬底。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来 实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1所示，半导体器件包括漂移区100，漂移区100形成于半导体衬底410的正面，漂移区100具体可以是半导体衬底410通过外延生长而成。漂移区100上表层形成有体区110，体区110上表层形成有第一掺杂区111。第一掺杂区111与第一电极310连接，半导体衬底410与第二电极320连接，第一电极310和第二电极320通过体区110和漂移区100形成电流通路。
半导体器件内还具有第一沟槽121和第二沟槽122，其中，第一沟槽121自体区110内部延伸至漂移区100内，即第一沟槽121的顶端在体区110内、第一沟槽121的底端在漂移区100内；第二沟槽122贯穿第一掺杂区111、体区110并延伸至漂移区100内。第一沟槽121的侧壁和第二沟槽122的侧壁均形成有氧化层131，其中，第一沟槽121内形成的氧化层为隔离氧化层131a，第二沟槽122内形成的氧化层为栅氧层131b。同时，第一沟槽121内还填充有第一导电结构141，第二沟槽122内还填充有第二导电结构142。进一步的，栅极(图中未示出)与第二导电结构142接触；第一电极310延伸至第一沟槽121的顶部，并分别与第一掺杂区111、体区110和第一沟槽121接触，使第一掺杂区111、体区110和第一沟槽121内的第一导电结构141均能获取第一电极310的电位。具体的，第一导电结构141和第二导电结构142可为多晶硅。
漂移区100内还形成有第一扩展区150，第一扩展区150位于第一沟槽121的下方并包围第一沟槽121的底部。
其中，漂移区100、第一掺杂区111具有第一导电类型，体区110、第一 扩展区150具有第二导电类型。具体的，第一导电类型为P型，第二导电类型为N型，或，第一导电类型为N型，第二导电类型为P型。
上述半导体器件，第二沟槽122内的第二导电结构142和栅氧层131b形成沟槽栅结构并与栅极(图中未示出)连接，通过沟槽栅结构在体区110内形成纵向导电沟道。进一步的，在第二沟槽122内，可仅填入第二导电结构142，形成如图1所示的普通沟槽栅结构。
同时，一方面，第一沟槽121内的第一导电结构141能够从第一电极310处获取电势，使得第一沟槽121内的第一导电结构141和隔离氧化层131a构成内场板，以调节漂移区100的电场，增强漂移区100的耗尽。另一方面，第一沟槽121底部的第一扩展区150与漂移区100的导电类型相反，也能进一步增强漂移区100的耗尽。在本申请中，通过增加内场板和第一扩展区，能够有效提高器件耐压，因此，在具有同等击穿电压的条件下，本申请中半导体器件的漂移区可以提高掺杂浓度，从而达到降低导通电阻的目的。且，传统的沟槽栅结构中，击穿位置为沟槽栅与漂移区的交界面，在本申请中，由于在漂移区100内设置有第一沟槽121和包围第一沟槽121底部的第一扩展区150，使得击穿位置从沟槽栅与漂移区的交界面转移至第一扩展区150与漂移区100的交界面，从而使击穿更加稳定。
在一实施例中，也可在第二沟槽122底部的漂移区100内形成包围第二沟槽122的第二扩展区，第二扩展区与第一扩展区的性质及作用相同，可进一步增强漂移区的耗尽。
在一实施例中，第一沟槽121和第二沟槽122的底部深度不同，具体的，第一沟槽121的底部深度大于第二沟槽122的底部深度，这样漂移区100的三维耗尽最优。
在一实施例中，上述半导体器件还包括有重掺杂区112，重掺杂区112形成于体区110内并与第二沟槽122间隔设置，重掺杂区112具有第二导电类型，即重掺杂区112与体区110的导电类型相同，但重掺杂区112的掺杂浓度高于体区110的掺杂浓度。此时，第一沟槽121依次贯穿重掺杂区112、 体区110并延伸至漂移区100内，第一电极310的底部一部分与第一沟槽121接触并被第一沟槽121覆盖，另一部分则并被重掺杂区112包围，以降低第一电极310与体区110的接触电阻。需要说明的是，此处的第一电极310包括位于图示顶层的金属层以及自金属层延伸至第一沟槽121处的第一引出结构。
在一实施例中，在第一掺杂区111和第二沟槽122上覆盖有介质层200，第一电极310的第一引出结构贯穿介质层200、第一掺杂区111并延伸至第一沟槽121顶部与第一沟槽121接触。
具体的，在一实施例中，第一沟槽121底部未形成有氧化层，使得第一扩展区150与第一导电结构141直接接触。在另一实施例中，第一沟槽121的内壁均形成有氧化层131，使得第一扩展区150与第一导电结构141隔离。
具体的，在一实施例中，第一电极310延伸至第一沟槽121顶部并与第一沟槽121接触，第一导电结构141填满第一沟槽121并直接与第一电极310接触以获取电势。在另一实施例中，第一导电结构141未填满第一沟槽121，第一导电结构141顶部还设有隔离层，第一导电结构141通过隔离层与第一电极310隔离，且，隔离层的厚度需满足第一导电结构141能从第一电极310处获取感应电势。
为详细介绍本申请中的半导体结构，以下以四个实施例进一步说明。
第一实施例：
图1是第一实施例中半导体器件的结构示意图。
继续参见图1，第一电极310延伸至第一沟槽121顶部并与第一沟槽121内的第一导电结构141直接接触，使得第一导电结构141直接获取第一电极310的电势，第一导电结构141和氧化层131相当于内场板，调节漂移区100的电场，增强漂移区100的耗尽。
具体的，在第一沟槽内121内，氧化层131仅形成于第一沟槽121的侧壁，即第一沟槽121的侧壁形成有氧化层131，但第一沟槽121的底部未形成氧化层，第一扩展区150与第一沟槽121内的第一导电结构141接触，第 一导电结构141从第一电极310处获取电势后，第一扩展区150也可通过第一导电结构141获取电势，增强第一扩展区150对漂移区100的耗尽。
在本实施例中，第一导电结构141与第一电极310直接接触、第一扩展区150与第一导电结构141直接接触，使得第一扩展区150和第一导电结构141均均有较强的电势，可以提高对漂移区100的耗尽。
第二实施例：
图2是第二实施例中半导体器件的结构示意图。
第二实施例与第一实施例的区别仅在于，第二实施例中氧化层131的覆盖区域不同。在本实施例中，第一沟槽121的内壁上均形成有氧化层131，即第一沟槽121的侧壁和底部均形成有氧化层131，第一扩展区150与第一导电结构141隔离，由此切断第一电极310、第一导电结构141和第一扩展区150的漏电通道，减小漏电。
第三实施例：
图3是第三实施例中半导体器件的结构示意图。
第三实施例与第一实施例的区别仅在于，第三实施例中第一导电结构141与第一电极310之间还形成有隔离层160，第一导电结构141通过隔离层160与第一电极310隔离，且隔离层160的厚度需满足第一导电结构141可从第一电极310处获取感应电势。具体的，隔离层160可为氧化硅。
在本实施例中，第一电极310与第一导电结构141之间设有隔离层160，利用隔离层160切断第一电极310、第一导电结构141和第一扩展区150的漏电通道，减小漏电。同时，第一导电结构141可以获取第一电极310的感应电势，因此，在本实施例中，第一导电结构141和第一扩展区150具有一定的感应电势，可增强漂移区100的耗尽。
第四实施例：
图4是第四实施例中半导体器件的结构示意图。
第四实施例与第一实施例的区别仅在于，第四实施例中第一沟槽121内的第一导电结构141与第一电极310之间设有隔离层160，且第一沟槽121 内壁均形成有氧化层131，使第一扩展区150与第一导电结构141隔离。
在本实施例中，第一电极310通过隔离结构160与第一导电结构141隔离，且第一导电结构141通过氧化层131与第一扩展区150隔离，进一步切断第一电极310、第一导电结构141和氧化层131的漏电通道，避免漏电，此时，第一导电结构141可获取第一电极310的感应电势，而第一扩展区150无电势。
在一具体的实施例中，上述半导体器件可为VDMOS(Vertical Double diffusion Metal Oxide Semiconductor，垂直型双扩散金属氧化物半导体)场效应管。其中，第一掺杂区111为源区，半导体衬底410具有第一导电类型。第一电极310为源极，第二电极320为漏极。
在另一具体的实施例中，上述半导体器件也可为IGBT((Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)。其中，第一掺杂区111为发射区，半导体衬底410具有第二导电类型，半导体衬底410与漂移区100之间还形成有缓冲区，缓冲区具有第一导电类型。第一电极310为发射极，第二电极320为集电极。
本申请还涉及一种半导体器件的制备方法，如图5所示，该制备方法包括以下步骤：
步骤S510：在半导体衬底上形成漂移区，所述漂移区具有第一导电类型。
如图6a所示，提供半导体衬底410，半导体衬底上410形成有漂移区100。
步骤S520：在所述漂移区上开设第一沟槽，在第一沟槽的内壁形成氧化层。
如图6b所示，在漂移区100上开设第一沟槽121，第一沟槽121的内壁形成氧化层131。具体的，可通过热氧化工艺在第一沟槽121的内壁形成氧化层131。
步骤S530：通过所述第一沟槽向所述漂移区注入第二导电类型掺杂离子，形成与第一沟槽底部接触的第一扩展区。
如图6c所示，通过第一沟槽121向漂移区100注入第二导电类型掺杂离子，形成与第一沟槽121底部接触的第一扩展区150。
步骤S540：向所述第一沟槽内填充第一导电结构。
如图6e所示，向第一沟槽121内填充第一导电结构141。具体的，第一导电结构141可为多晶硅。
在一实施例中，在步骤S530和步骤S540之间，还包括：
刻蚀所述第一沟槽底部的氧化层，暴露出所述第一扩展区。
如图6d所示，通过干法刻蚀第一沟槽121底部的氧化层131，形成暴露出第一扩展区150的开口。此时，在步骤S540中，填充第一导电结构141后，第一导电结构141与第一扩展区150接触。
步骤S550：在所述漂移区上开设与第一沟槽隔离的第二沟槽，在所述第二沟槽的内壁形成氧化层，向所述第二沟槽内填充第二导电结构。
如图6f所示，继续在漂移区100上开设第二沟槽122，第一沟槽121和第二沟槽122相互隔离。在第二沟槽122的内壁形成氧化层131，并在第二沟槽122内填充第二导电结构142。此时，第一沟槽121内形成的氧化层为隔离氧化层131a，第二沟槽122内形成的氧化层为栅氧层131b。具体的，第二导电结构142可为多晶硅。
步骤S560：对所述漂移区的上表层进行第二导电类型掺杂，形成分别与所述第一沟槽和所述第二沟槽接触的体区，对所述体区的上表层进行第一导电类型掺杂，形成分别与所述第一沟槽和所述第二沟槽接触的第一掺杂区。
如图6g所示，在形成第一沟槽121和第二沟槽122之后，继续形成体区和第一掺杂区。具体的，对漂移区100的上表层进行第二导电类型掺杂，形成分别与第一沟槽121和第二沟槽122接触的体区110。继续对体区110的上表层进行第一导电类型掺杂，形成与第一沟槽121和第二沟槽122接触的第一掺杂区111。
在一实施例中，形成体区110的工艺具体为高温推阱工艺，其中，高温推阱的温度和时间可根据体区的掺杂深度和掺杂浓度调节，具体的，高温推 阱的温度范围可控制在900℃～1200℃之间，高温推阱的时间范围可控制在10min～180min之间。在上述高温推阱形成体区110的同时，第一扩展区150的掺杂离子向外扩散，使得第一扩展区150向外扩展，从而增大第一扩展区150的体积。
步骤S570：削减第一沟槽内的第一导电结构和氧化层的高度至所述体区内，形成贯穿所述第一掺杂区和部分所述体区并延伸至与所述第一沟槽顶部接触的第一电极，形成与所述第二导电结构接触的栅极，形成与所述半导体衬底接触的第二电极。
如图6h所示，削减第一沟槽内的第一导电结构141和氧化层131的高度，使第一沟槽121及其内部填充结构整体顶面高度下降至体区内，并在第一沟槽121的上方贯穿第一掺杂区111并延伸至体区110已与第一沟槽接触的第一引出结构，因此，第一引出结构还与第一掺杂区111和体区110接触。第一引出结构的顶部与第一金属层连接，第一引出结构与第一金属层共同作为第一电极310。具体的，第一引出结构在图6h截面中的宽度大于第一沟槽121的宽度，且第一引出结构覆盖第一沟槽121。
同时，还形成与第二导电结构142接触的栅极。
当上述半导体器件为VDMOS场效应管时，第一掺杂区111为源区，半导体衬底410具有第一导电类型。当上述半导体器件为IGBT时，第一掺杂区111为发射区，半导体衬底410具有第二导电类型，半导体衬底410与漂移区100之间还形成有第一导电类型缓冲区。
上述半导体器件的制备方法，在元胞区开设第二沟槽且在第二沟槽内形成第二导电结构和氧化层，其中，第二导电结构与栅极连接，从而构成沟槽栅结构，通过该沟槽栅结构形成纵向导通沟道，提高导通沟道的密度，降低导通电阻。
同时，在元胞区还开设第一沟槽，一方面，第一沟槽内形成有第一导电结构和氧化层，第一导电结构能够从第一电极获取一定的电势，与氧化层形成内场板，调节漂移区电场，增强漂移区的耗尽。另一方面，在元胞区域还 形成有第一扩展区包围沟槽底部，且第一扩展区的导电类型与漂移区的导电类型相反，第一扩展区也可以增强漂移区的耗尽。在本申请中，通过在传统沟槽栅结构的基础上，形成内场板和第一扩展区，在内场板和第一扩展区的共同作用下，增大漂移区的耗尽，提高漂移区的击穿电压。因此，在具有同等击穿电压的条件下，本申请中半导体器件的漂移区可以提高掺杂浓度，从而降低导通电阻，即，在具有同等击穿电压的条件下，本申请中的半导体器件具有更低的导通电阻。
以上实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体器件，包括：
    漂移区，具有第一导电类型，形成于半导体衬底上；
    体区，具有第二导电类型，形成于所述漂移区的上表层；
    第一掺杂区，具有第一导电类型，形成于所述体区的上表层；
    第一沟槽和第二沟槽，所述第一沟槽自所述体区内部延伸至所述漂移区内，所述第二沟槽贯穿所述第一掺杂区、所述体区并延伸至所述漂移区内，所述第一沟槽的侧壁和所述第二沟槽的侧壁均形成有氧化层，且所述第一沟槽内填充有第一导电结构，所述第二沟槽填充有第二导电结构；
    第一扩展区，具有第二导电类型，形成于所述第一沟槽下方的漂移区内并包围所述第一沟槽的底部；
    栅极，与所述第二导电结构接触；
    第一电极，延伸至所述第一沟槽的顶部，并分别与所述第一掺杂区、所述体区和所述第一沟槽接触；以及
    第二电极，与所述半导体衬底接触。
  2. 如权利要求1所述的半导体器件，其中所述第一沟槽的底部深度大于所述第二沟槽的底部深度。
  3. 如权利要求1所述的半导体器件，其中所述第一沟槽底部未形成有所述氧化层，所述第一扩展区与所述第一导电结构接触。
  4. 如权利要求1所述的半导体器件，其中所述第一沟槽的内壁均形成有所述氧化层，所述第一扩展区与所述第一导电结构隔离。
  5. 如权利要求1至4任一项所述的半导体器件，其中所述第一导电结构与所述第一电极接触。
  6. 如权利要求1至4任一项所述的半导体器件，其中所述第一沟槽内还形成有位于所述第一导电结构顶部的隔离层，所述第一导电结构通过所述隔离层与所述第一电极隔离。
  7. 如权利要求1所述的半导体器件，其中还包括：
    重掺杂区，具有第二导电类型，形成于所述体区内并与所述第二沟槽间隔设置，且所述重掺杂区的掺杂浓度高于所述体区的掺杂浓度，所述第一沟槽自所述重掺杂区内部延伸至所述漂移区内，所述第一电极的底部未被所述第一沟槽覆盖的部分被所述重掺杂区包围。
  8. 如权利要求1所述的半导体器件，其中所述半导体器件还包括：
    第二扩展区，具有第二导电类型，形成于所述第二沟槽下方的漂移区内并包围所述第二沟槽的底部。
  9. 如权利要求1所述的半导体器件，其中第一电极包括位于顶层的金属层和自金属层延伸至第一沟槽的第一引出结构。
  10. 如权利要求9所述的半导体器件，其中半导体器件还包括：
    介质层，覆盖在第一掺杂区和第二沟槽上，第一电极的第一引出结构贯穿介质层、第一掺杂区并延伸至第一沟槽顶部与第一沟槽接触。
  11. 如权利要求1所述的半导体器件，其中所述半导体器件为VDMOS场效应管，所述第一掺杂区为源区，所述半导体衬底具有第一导电类型，所述第一电极为源极，所述第二电极为漏极。
  12. 如权利要求1所述的半导体器件，其中所述半导体器件为IGBT器件，所述第一掺杂区为发射区，所述半导体衬底具有第二导电类型，所述半导体衬底与所述漂移区之间还形成有缓冲区，所述缓冲区具有第一导电类型，所述第一电极为发射极，所述第二电极为集电极。
  13. 一种半导体器件的制备方法，包括：
    在半导体衬底上形成漂移区，所述漂移区具有第一导电类型；
    在所述漂移区上开设第一沟槽，在第一沟槽的内壁形成氧化层；
    通过所述第一沟槽向所述漂移区注入第二导电类型掺杂离子，形成与第一沟槽底部接触的第一扩展区；
    向所述第一沟槽内填充第一导电结构；
    在所述漂移区上开设与第一沟槽隔离的第二沟槽，在所述第二沟槽的内壁形成氧化层，向所述第二沟槽内填充第二导电结构；
    对所述漂移区的上表层进行第二导电类型掺杂，形成分别与所述第一沟槽和所述第二沟槽接触的体区，对所述体区的上表层进行第一导电类型掺杂，形成分别与所述第一沟槽和所述第二沟槽接触的第一掺杂区；以及
    削减第一沟槽内的第一导电结构和氧化层的高度至所述体区内，形成贯穿所述第一掺杂区和部分所述体区并延伸至与所述第一沟槽顶部接触的第一电极，形成与所述第二导电结构接触的栅极，形成与所述半导体衬底接触的第二电极。
  14. 如权利要求13所述的制备方法，其中所述向所述第一沟槽内填充第一导电结构之前还包括：
    刻蚀所述第一沟槽底部的氧化层，暴露出所述第一扩展区。
  15. 如权利要求13所述的制备方法，其中形成体区的工艺具体为高温推阱工艺。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114551589A (zh) * 2022-04-26 2022-05-27 安建科技(深圳)有限公司 一种功率半导体器件及其制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117012810B (zh) * 2023-10-07 2024-01-12 希力微电子(深圳)股份有限公司 一种超结沟槽型的功率半导体器件及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120299091A1 (en) * 2011-05-25 2012-11-29 Great Power Semiconductor Corp. Trenched power semiconductor device and fabrication method thereof
JP2012243985A (ja) * 2011-05-20 2012-12-10 Shindengen Electric Mfg Co Ltd 半導体装置及びその製造方法
US20140042535A1 (en) * 2012-02-13 2014-02-13 Maxpower Semiconductor, Inc. Trench transistors and methods with low-voltage-drop shunt to body diode
CN105637644A (zh) * 2014-09-24 2016-06-01 新电元工业株式会社 碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法
US20180076318A1 (en) * 2016-09-14 2018-03-15 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100603931B1 (ko) * 2005-01-25 2006-07-24 삼성전자주식회사 반도체 소자 제조방법
JP2011512677A (ja) * 2008-02-14 2011-04-21 マックスパワー・セミコンダクター・インコーポレイテッド 半導体素子構造及び関連プロセス
US20120037983A1 (en) * 2010-08-10 2012-02-16 Force Mos Technology Co., Ltd. Trench mosfet with integrated schottky rectifier in same cell
CN105990423A (zh) * 2015-02-02 2016-10-05 无锡华润上华半导体有限公司 横向双扩散场效应管
US9673318B1 (en) * 2016-01-13 2017-06-06 Infineon Technologies Americas Corp. Semiconductor device including a gate trench having a gate electrode located above a buried electrode

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012243985A (ja) * 2011-05-20 2012-12-10 Shindengen Electric Mfg Co Ltd 半導体装置及びその製造方法
US20120299091A1 (en) * 2011-05-25 2012-11-29 Great Power Semiconductor Corp. Trenched power semiconductor device and fabrication method thereof
US20140042535A1 (en) * 2012-02-13 2014-02-13 Maxpower Semiconductor, Inc. Trench transistors and methods with low-voltage-drop shunt to body diode
CN105637644A (zh) * 2014-09-24 2016-06-01 新电元工业株式会社 碳化硅半导体装置，碳化硅半导体装置的制造方法以及碳化硅半导体装置的设计方法
US20180076318A1 (en) * 2016-09-14 2018-03-15 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114551589A (zh) * 2022-04-26 2022-05-27 安建科技(深圳)有限公司 一种功率半导体器件及其制备方法
CN114551589B (zh) * 2022-04-26 2022-09-09 安建科技(深圳)有限公司 一种功率半导体器件及其制备方法

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