WO2021227518A1 - 沟槽栅半导体器件及其制备方法 - Google Patents

沟槽栅半导体器件及其制备方法 Download PDF

Info

Publication number
WO2021227518A1
WO2021227518A1 PCT/CN2020/140339 CN2020140339W WO2021227518A1 WO 2021227518 A1 WO2021227518 A1 WO 2021227518A1 CN 2020140339 W CN2020140339 W CN 2020140339W WO 2021227518 A1 WO2021227518 A1 WO 2021227518A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
trench
gate
conductivity type
drift
Prior art date
Application number
PCT/CN2020/140339
Other languages
English (en)
French (fr)
Inventor
肖魁
方冬
Original Assignee
华润微电子（重庆）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华润微电子（重庆）有限公司 filed Critical 华润微电子（重庆）有限公司
Publication of WO2021227518A1 publication Critical patent/WO2021227518A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • This application relates to the field of semiconductors, and in particular to a trench gate semiconductor device and a manufacturing method thereof.
  • a semiconductor device usually includes an active region and a terminal region surrounding the active region. Both the active region and the terminal region are formed in different regions of the drift region. Among them, the active region is used to form specific trench-type electronic components such as MOS (Metal Oxide Semiconductor) tube or IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor), etc.
  • the terminal region is located in the active At the periphery of the region, an auxiliary structure is provided in the terminal region to enhance the depletion of the drift region, thereby improving the withstand voltage capability of the semiconductor device.
  • a doped region with a conductivity type opposite to that of the drift region is formed in the terminal region, and a PN junction is constructed in the terminal region to enhance the depletion of the drift region.
  • the degree of depletion enhanced by the PN junction is limited.
  • the doped regions will diffuse to the surroundings during the subsequent annealing. In order to ensure that the adjacent doped regions will not be integrated after annealing, the distance between the adjacent doped regions is relatively large. The above is not conducive to the improvement of device integration.
  • a trench gate semiconductor device includes an active region and a terminal region located at the periphery of the active region, wherein the active region includes: a drift region having a first conductivity type; a body region having a second conductivity type , Located on the drift region; a first doped region having the first conductivity type, located on the body region, the first doped region is provided with a first trench, the first trench penetrates The first doped region and the body region extend to the drift region; the second doped region has a second conductivity type and is located on the body region; and the trench gate includes a trench filled in the drift region.
  • the gate conductive layer in the first trench and the gate dielectric layer between the inner wall of the first trench and the gate conductive layer; the terminal region includes: the drift region, the drift region is provided with a second A trench; a second dielectric structure filled in the second trench; and a second floating region, having a second conductivity type, located in the drift region and surrounding the bottom of the second dielectric structure.
  • a method for manufacturing a trench gate semiconductor device includes: forming a drift region having a first conductivity type, the drift region including an active region and a terminal region surrounding the active region; A trench, opening a second trench in the terminal area; forming a second floating area of the second conductivity type surrounding the bottom of the second trench in the drift area at the bottom of the second trench; A second dielectric structure is filled in the second trench; a gate dielectric layer is formed on the inner wall of the first trench, and a gate conductive layer is filled in the trench; ion implantation is performed on the active region of the drift region to form A body region of the second conductivity type; and ion implantation of the body region to form a first doped region of the first conductivity type and a second doped region of the second conductivity type, the first doped region and The first trenches are adjacent and in contact.
  • FIG. 1 is a flow chart of the steps of a method for manufacturing a trench gate semiconductor device in an embodiment
  • Figures 2a to 2k are structural diagrams of an embodiment corresponding to related steps of the preparation method of Figure 1;
  • FIG. 3 is a schematic diagram of the structure of a trench gate semiconductor device in an embodiment
  • FIG. 4 is a schematic diagram of the structure of a trench gate semiconductor device in another embodiment.
  • Drift zone 100.
  • Active zone 102. Terminal zone; 103.
  • Mask 104.
  • Oxide layer 105.
  • Isolation layer 111.
  • the semiconductor device includes an active area AA and a terminal area W located at the periphery of the active area AA.
  • the active area AA includes a variety of doped areas and is used to connect with electrodes
  • the terminal area W is used to set auxiliary structures to improve the withstand voltage of the semiconductor device and protect the semiconductor device.
  • the active region AA includes a drift region 100, a body region 140, a first doped region 141, a second doped region 142, and a trench gate.
  • the drift region 100 has the first conductivity type, and the drift region 100 may specifically be an epitaxial layer formed by epitaxial growth on the semiconductor substrate 180.
  • the material of the drift region 100 may be silicon, germanium, silicon germanium, or any other suitable semiconductor materials. In this embodiment, the material of the drift region 100 is silicon.
  • the body region 140 has the second conductivity type, and the body region 140 is located on the drift region 100.
  • the upper surface layer of the drift region 100 may be doped to change the upper surface layer of the drift region 100 from the first conductivity type to the second conductivity type.
  • the above-mentioned body region 140 is formed.
  • the first doped region 141 and the second doped region 142 are both formed on the body region 140.
  • the first doped region 141 has the first conductivity type
  • the second doped region 142 has the second conductivity type
  • the second doped region 142 has the second conductivity type.
  • the doping concentration of the doping region 142 is higher than the doping concentration of the body region 140.
  • the first doped region 141 and the second doped region 142 are formed by doping the body region 140 at different positions. Wherein, a first trench is formed on the first doped region 141, and the first trench penetrates the first doped region 141 and the body region 140 sequentially and extends into the drift region 100.
  • the trench gate is formed by filling the first trench.
  • the first trench is filled with a gate conductive layer 132 electrically isolated from the drift region 100, and a gate dielectric layer 131 between the gate conductive layer 132 and the body region 140 is formed on the sidewall of the first trench, the gate dielectric layer 131 and
  • the gate conductive layer 132 constitutes a gate structure, and the gate conductive layer 132 of the gate structure is drawn out and electrically connected to the gate electrode (the gate electrode is not shown in the figure).
  • a gate dielectric layer 131 is formed on the sidewalls formed by the body region 140 of the first trench.
  • the gate dielectric layer 131 may be a silicon oxide layer
  • the gate conductive layer 132 may be a polysilicon layer.
  • the terminal region W includes a second dielectric structure 122 and a second floating region 112 located in the drift region 100.
  • the second dielectric structure 122 is filled in the second trench, where the second trench is opened on the drift region 100 located in the terminal region W, and the second dielectric structure 122 extends into the drift region 100.
  • the second floating region 112 has the second conductivity type.
  • the second floating region 112 is located in the drift region 100 under the second trench and surrounds the bottom of the second dielectric structure 122.
  • the doping concentration of the second floating region 122 is greater than the doping concentration of the drift region 100. Increasing the doping concentration of the second floating region 122 can increase the effect of the second floating region 122 on the drift region 100. Exhaustion.
  • the second dielectric structure 122 may be a single structure composed of one dielectric material, or a composite structure composed of multiple dielectric materials. Specifically, the second dielectric structure 122 includes any one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the second dielectric structure 122 may be silicon oxide.
  • the above-mentioned first conductivity type is opposite to the second conductivity type.
  • the second conductivity type is P-type
  • the first conductivity type is N-type
  • the second conductivity type is P type.
  • the gate conductive layer 132 is led to the gate electrode (the gate electrode is not shown in the figure), and the carrier distribution state of the body region 140 on both sides of the trench gate is controlled by the trench gate, so that both sides of the trench gate
  • the body region 140 forms an inversion region, which serves as a conductive channel to connect the first doped region 141 and the drift region 100, thereby turning on the semiconductor device.
  • the withstand voltage capability of the semiconductor device depends on the voltage that the drift region 100 can withstand.
  • the auxiliary structure provided in the terminal area W includes a second dielectric structure 122 and a second floating area 112.
  • the second dielectric structure 122 extends into the drift region 100, and the reverse breakdown voltage of the drift region 100 can be increased through the second dielectric structure 122.
  • the size of the second dielectric structure 122 is not affected by annealing. After annealing, the area occupied by the second dielectric structure 122 is smaller, so that the distribution density of the second dielectric structure 122 can be increased, so that the withstand voltage level of the semiconductor device can be improved. higher.
  • this solution is also provided with a second floating region 112 surrounding the second dielectric structure 122.
  • the conductivity type of the second floating region 112 is opposite to that of the drift region 100, that is, the first floating region 111 and the drift region 100 A PN junction is formed to enhance the depletion of the drift region 100.
  • the first floating region 111 and the second dielectric structure 122 are used in combination to further enhance the voltage withstand capability of the drift region 100.
  • the gate dielectric layer on the sidewall of the first trench extends toward the bottom of the trench and covers the entire inner wall of the first trench.
  • the gate dielectric layer 131 is formed only on the sidewall of the first trench, and the first trench is added between the gate conductive layer 132 and the bottom of the first trench.
  • the dielectric structure 121, the first dielectric structure 121 is filled at the bottom of the first trench, and the upper surface of the first dielectric structure 121 is lower than the lower surface of the body region 140.
  • the thickness of the first dielectric structure 121 is greater than the thickness of the gate dielectric layer 131.
  • the first dielectric structure 121 is arranged in the drift region 100 of the active region AA, which can improve the voltage withstand capability of the drift region 100. At the same time, the first dielectric structure 121 is located at the bottom of the first trench, which can reduce the problem of electric field concentration at the bottom of the trench and improve device stability.
  • the thickness of the first dielectric structure 121 can be set according to specific needs. The deeper the depth of the first groove and the thicker the first dielectric structure 121, the stronger the pressure resistance. In one embodiment, the depths of the first trench and the second trench are the same, and the first trench and the second trench can be simultaneously formed in the same etching process. In another embodiment, the depths of the first trench and the second trench are different. In an embodiment, the first dielectric structure 121 may be a single structure composed of one dielectric material, or a composite structure composed of multiple dielectric materials. Specifically, the first dielectric structure 121 includes any one or more of silicon nitride, silicon oxide, and silicon oxynitride.
  • the first dielectric structure 121 is the same as the above-mentioned second dielectric structure 122, both of which are silicon oxide.
  • the first dielectric structure 121 and the second dielectric structure 122 can be deposited in the first trench and the second trench through a deposition process. It is formed by simultaneous deposition of the same kind of dielectric material inside.
  • the active area AA further includes a first floating region 111 formed in the drift region 100, the first floating region 111 is located under the first trench and surrounds the first dielectric structure in the first trench 121.
  • the doping concentration of the first floating region 111 is greater than the doping concentration of the drift region 100, and the doping concentration of the first floating region 111 is higher, which can improve the effect of the first floating region 111 on the drift region 100.
  • the first floating region 111 is located under the first trench and surrounds at most half the thickness of the first dielectric structure 121 in the first trench.
  • the first floating region 111 has the second conductivity type, that is, the first floating region 111 and the drift region 100 form a PN junction, which can enhance the depletion of the drift region 100 and further improve the voltage resistance of the device.
  • the first floating region 111 surrounds the bottom of the first trench, which can avoid electric field concentration at the bottom of the trench, thereby improving device reliability.
  • the ratio of the depth of the second trench to the thickness of the drift region 100 ranges from 1:8 to 1:15. Within this range, the second trench can better assist the drift region 100 in power consumption. However, the interference to the current in the drift region 100 is also small.
  • the spacing between adjacent second trenches increases in a direction away from the active region AA. Since the breakdown location is usually located in the active area or near the edge of the active area, in the direction close to the active area AA, the distribution density of the second trenches increases, and the distribution of the second trenches is denser, thereby enhancing the proximity of the active area The drift region is depleted, thereby increasing the withstand voltage of the device. In a specific embodiment, in the terminal region W, the spacing between adjacent second trenches gradually increases in a direction away from the active region AA.
  • the terminal area W may be divided into a first area close to the active area AA and a second area far away from the active area AA, wherein one of the adjacent second trenches in the first area
  • the distance between adjacent second trenches is the same, and the distance between adjacent second trenches in the second area is also the same, and the distance between adjacent second trenches in the first area is smaller than that between adjacent second trenches in the second area.
  • the spacing between In other specific embodiments, the spacing between adjacent second trenches in the first area gradually increases in the direction away from the active area AA, and the distance between adjacent second trenches in the second area The spacing between the two is the same and greater than the spacing between adjacent second trenches in the first region.
  • the distance between adjacent second trenches ranges from 1 to 10 ⁇ m.
  • the distance between adjacent first trenches on the active area AA increases in a direction closer to the terminal area W, that is, the closer to the terminal area W, the distance between adjacent first trenches The larger is, the second dielectric structure 112 arranged in the terminal region W can assist the drift region in the terminal region and the drift region in the active region close to the terminal region to be depleted. Therefore, in the active region, the farther away from the terminal region is In the region of, it is necessary to increase the distribution density of the first trenches to enhance the depletion of the drift region, thereby increasing the device withstand voltage.
  • the distance between adjacent first trenches ranges from 1 to 10 ⁇ m.
  • the area covered by the body area 140 is designated as the active area AA, and the area outside the body area 140 is designated as the terminal area W.
  • the side surface of the second dielectric structure 122 adjacent to the active area AA of the terminal area W is in contact with the body area 140.
  • the second dielectric structure 122 is close to the body region 140 and surrounds the body region 140, which can reduce the degree of outward diffusion of the body region 140 and maintain the doping concentration of the body region 140.
  • the second trench body The regions 140 are adjacent and in contact, which can also reduce the risk of breakdown from the side of the body region 140, thereby improving the stability of the device.
  • the above-mentioned trench gate semiconductor device is further provided with a plurality of electrodes.
  • a gate electrode (the gate electrode is not shown in the figure) connected to the gate conductive layer 132 can be provided, and a voltage control signal is connected to the gate electrode to control the on-off of the device.
  • an interlayer dielectric layer 150 is provided on the first doped region 141 and the second doped region 142, and a first electrode 210 is also provided on the interlayer dielectric layer 150.
  • the first electrode 210 is located Above the first doped region 141 and the second doped region 142, and are electrically connected to the first doped region 141 and the second doped region 142.
  • the first doped region 141 and the second doped region 142 can be led out to the first electrode 210 through a contact hole.
  • the first electrode 210 extends from the active area AA to the terminal area W and covers a part of the second dielectric structure 122.
  • the first electrode 210 located in the active area AA is used to electrically connect to the first doped area 141 and the second doped area 142, and the first electrode 210 extends beyond the active area AA and extends to the terminal area W
  • it can ensure that the first electrode 210 can cover all the contact holes in the active area AA, and at the same time, the first electrode 210 extending to the terminal area W can also act as a metal field plate to adjust the electric field of the drift region 100 in the terminal area W. , To further improve the voltage withstand capability of the drift region 100.
  • the positions of the first doped region 141 and the second doped region 142 on the body region 140 can be flexibly set.
  • the first doped region 141 and the second doped region 142 both extend downward from the upper surface of the body region 140, that is, the first doped region 141 and the second doped region 142 are on the same plane.
  • the first doped region 141 and the second doped region 142 are electrically connected to the first electrode 210 through different contact holes, respectively.
  • the first doped region 141 and the second doped region 142 are sequentially stacked on the body region 140.
  • the second doped region 142 is located on the body region 140 and Spaced apart from the first trench, the first doped region 141 overlaps the second doped region 142 and extends to both sides of the first trench, that is, the coverage of the second doped region 142 is smaller than The coverage of the first doped region 141 overlapped on the second doped region 142.
  • the above-mentioned trench gate semiconductor device further includes an interlayer dielectric layer 150 and a contact hole.
  • the interlayer dielectric layer 150 is located on the first doped region 141, the first electrode 210 is located on the interlayer dielectric layer 150, and the top of the contact hole is connected to the The first electrode 210 is in contact, and the bottom end of the contact hole penetrates the interlayer dielectric layer 150 and the first doped region 141 and is in contact with the second doped region 142.
  • the surface layer of the body region 140 can be doped, so that the surface layer of the body region 140 becomes the first doped region 141, and then an interlayer dielectric layer 150 is formed, and a penetration is provided on the interlayer dielectric layer 150
  • the interlayer dielectric layer 150, the first doped region 141 and the contact hole of the body region 140 are exposed, the exposed body region 140 is doped, the second doped region 142 is formed at the bottom of the contact hole, and the metal is deposited to fill the contact hole And the first electrode 210 is formed.
  • the first doped region 141 and the second doped region 142 are overlapped on the body region 140, and the first electrode 210 is simultaneously connected to the first doped region 141 and the second doped region 142 through the same contact hole.
  • the number of contact holes provided in this embodiment is smaller and the structure is simpler.
  • the first doped regions 141 are formed in all the body regions 140 on both sides of the first trenches, that is, the coverage of the first doped regions 141 is the same as the coverage of the body regions 140, and each first trench Conductive channels are formed on both sides of the groove.
  • the first doped region 141 is formed only on the body region 140 between adjacent first trenches, and the body region between the first trench at the outermost periphery of the active area AA and the terminal region W The region 140 does not form the first doped region 141, here the body region 140 only forms the second doped region 142, and the second doped region 142 is electrically connected to the first electrode 210 through the contact hole.
  • the device will be burnt when the parasitic transistor undergoes avalanche breakdown.
  • the first doped area 141 is not formed in the body area 140 located at the edge of the active area AA. That is, no parasitic transistor is formed at the edge of the active area AA, which can avoid the above-mentioned problems.
  • the above trench gate semiconductor device should also form a second electrode 220 connected to the drift region 100.
  • One of the first electrode 210 and the second electrode 220 serves as a current input terminal, and the other serves as a current output terminal.
  • the arrangement of the second electrode 220 may have various forms.
  • the trench gate semiconductor device includes an IGBT, and the first electrode 210 is an emitter.
  • the semiconductor device on the trench further includes a collector region 170 and a second The electrode 220.
  • the second electrode 220 is a collector.
  • the collector region 170 is located on the side of the drift region 100 away from the body region 140, and the collector region 170 has the second conductivity type; the collector electrode is electrically connected to the collector region 170.
  • a buffer zone 160 can also be formed between the collector region 170 and the drift region 100.
  • the buffer zone 160 has the first conductivity type and the doping concentration of the buffer zone 160 is higher than the doping concentration of the drift region 100.
  • the introduction of the first dielectric structure 121 and the first floating region 111 under the trench gate can not only improve the withstand voltage of the device, but also reduce the switching capacitance of the IGBT and the turn-on voltage of the device. drop.
  • the trench gate semiconductor device includes a MOS tube, and the first electrode 210 is a source.
  • the trench gate semiconductor device includes a second electrode 220.
  • the second electrode 220 is a drain.
  • the second electrode is located on a side of the drift region 100 away from the body region 140 and is electrically connected to the drift region 100.
  • the drift region 100 is formed on the front surface of the semiconductor substrate 180, and the drain is formed on the back surface of the semiconductor substrate 180.
  • the trench gate semiconductor device also includes a gate electrode (the gate electrode is not shown in the figure).
  • the present application also relates to a method for manufacturing a trench gate semiconductor device, which is used for manufacturing the above trench gate semiconductor device.
  • the preparation method includes the following steps:
  • Step S210 forming a drift region having the first conductivity type, the drift region including an active region and a terminal region surrounding the active region.
  • the drift region 100 having the first conductivity type can be formed by epitaxial growth on a semiconductor substrate (not shown in the figure).
  • the drift region 100 includes an active area AA and a terminal area W surrounding the active area AA.
  • Step S220 Open a first trench in the active area, and open a second trench in the terminal area.
  • a first trench is formed on the active area AA, and a second trench is formed on the terminal area W.
  • a first trench can be opened in the active area AA and a second trench can be opened in the terminal area W through different etching steps.
  • the first trench and the second trench can be simultaneously opened in the etching step.
  • a mask 103 is formed on the drift region 100, and the mask 103 is used in the active area AA.
  • the active area AA and the terminal area W of the drift region 100 are simultaneously etched, and trenches are etched in both the active area AA and the terminal area W. Among them, the active area AA and the terminal area W define an etching window.
  • the groove in the area AA is defined as the first groove
  • the groove in the terminal area W is defined as the second groove.
  • the size of the first trench and the second trench are the same, that is, the depth and the opening width of the first trench and the second trench are the same. In another embodiment, the sizes of the first groove and the second groove are different, that is, the depth and the opening width of the first groove and the second groove are different.
  • the number and pitch of the first trenches, and the number and pitch of the second trenches can be set according to specific needs.
  • the ratio of the depth of the second trench to the thickness of the drift region ranges from 1:8 to 1:15, and the ratio of the depth of the first trench to the thickness of the drift region is The range is also 1:8 ⁇ 1:15.
  • the distance between two adjacent second trenches increases in a direction away from the active region. In an embodiment, the spacing between adjacent first trenches on the active area AA increases in a direction close to the terminal area W.
  • step S230 may be directly performed without removing the mask 103.
  • Step S230 forming a second floating region of the second conductivity type surrounding the bottom of the second trench in the drift region at the bottom of the second trench.
  • ion implantation is directly performed on the bottom of the second trench to form a second floating region.
  • step S230 includes the following sub-steps:
  • Step S231 forming an oxide layer on the inner wall of the second trench.
  • the inner wall of the second trench is thermally oxidized to form an oxide layer 104 on the inner wall of the second trench.
  • the inner wall of the first trench is also thermally oxidized, that is, the structure formed in step S220 is thermally oxidized.
  • An oxide layer 104 is formed on the inner walls of a trench and a second trench. At this time, the upper surface of the drift region 100 outside the trench is protected by the mask 103 and will not be thermally oxidized.
  • Step S232 Perform ion implantation on the drift region at the bottom of the second trench to form a second floating region with the second conductivity type surrounding the bottom of the second trench.
  • ion implantation is performed on the drift region 100 under the second trench through the second trench.
  • the implanted ions have the second conductivity type and have a certain energy, which can be implanted through the oxide layer 104 in the trench.
  • a second floating region 112 surrounding the bottom of the second trench is formed below the second trench.
  • ion implantation is performed on the drift region 100 under the second trench through the second trench
  • ion implantation is also performed on the drift region 100 under the first trench to form the drift region 100 under the first trench.
  • the first floating region 111 surrounding the bottom of the first trench is formed under the second trench and the second floating region 112 surrounding the second trench is formed.
  • the doping concentration of the first floating region 111 is greater than the doping concentration of the drift region 100
  • the doping concentration of the second floating region 112 is greater than the doping concentration of the drift region 100.
  • Step S240 Fill the second dielectric structure in the second trench.
  • the second dielectric structure 122 is filled in the second trench by a deposition process.
  • the first dielectric structure 121 is filled in the first trench at the same time.
  • a thicker dielectric structure is deposited through a deposition process.
  • the dielectric structure fills the first trench and the second trench, the dielectric structure located in the first trench is defined as the first dielectric structure 121, and the dielectric structure located in the second trench is defined as the second dielectric structure 122 ,
  • the first dielectric structure 121 and the second dielectric structure 122 have the same material.
  • the first dielectric structure 121 in the first trench is etched back to expose part of the sidewall of the first trench. As shown in FIG.
  • the first dielectric structure 121 at the top of the first trench is engraved back, the first dielectric structure 121 at the bottom of the first trench is retained, and a part of the sidewall of the first trench is exposed.
  • the second dielectric layer in the second trench is not affected.
  • a protective layer is formed in the terminal area W. When the active area AA is etched, the terminal area W is not affected by the etching.
  • the mask 103 located on the drift region 100 is removed.
  • Step S250 forming a gate dielectric layer on the inner wall of the first trench, and filling the gate conductive layer in the trench.
  • an oxide layer is formed on the sidewalls of the exposed first trench as a gate dielectric layer 131 through a thermal oxidation process, and a gate conductive layer 132 is filled in the first trench through a deposition process.
  • the gate dielectric layer 131 is located Between the gate conductive layer 132 and the sidewall of the first trench.
  • the gate conductive layer 132 may be polysilicon.
  • the gate dielectric layer 131 and the gate conductive layer 132 form a gate structure.
  • the first dielectric structure 121 is not filled in the first trench, and in step S250, only the gate structure is formed in the first trench.
  • the bottom of the first trench is filled with the first dielectric structure 121.
  • the gate dielectric layer 131 and the gate conductive layer 132 are both located in the first trench above the first dielectric structure 121.
  • the gate conductive layer 132 is etched back so that the upper surface of the gate conductive layer 132 is lower than the first trench by two times.
  • an isolation layer 105 is formed on the gate conductive layer 132, and the isolation layer 105 is flush with the upper surface of the drift region 100.
  • the bottom of the first trench is filled with the first dielectric structure 121, and the gate dielectric layer 131 and the gate conductive layer 132 are only formed in the first trench above the first dielectric structure 121.
  • the thickness of the first dielectric structure 121 is greater than the thickness of the gate dielectric layer 131.
  • Step S260 Perform ion implantation on the active region of the drift region to form a body region with the second conductivity type, perform ion implantation on the body region, and form a first conductivity type with the first conductivity type in the body region.
  • a doped region and a second doped region having a second conductivity type, and the first doped region is adjacent to and in contact with the first trench.
  • the active area AA of the drift region 100 is first implanted with dopant ions having the second conductivity type, and a body having the second conductivity type is formed in the active area AA of the drift region 100. ⁇ 140. Then, doping ions with the first conductivity type are implanted into the body region 140 to form a first doped region 141 with the first conductivity type on the surface of the body region 140. It is understandable that the depth of the body region 140 should not exceed the depth of the gate dielectric layer 131 to ensure that the body region 140 between the first doped region 141 and the drift region 100 can be controlled to form an inversion layer through the above-mentioned gate structure.
  • the inversion layer serves as a conductive channel to connect the first doped region 141 and the drift region 100, so that the device is turned on.
  • the lower surface of the body region 140 is higher than the upper surface of the first dielectric structure 121.
  • an interlayer dielectric layer 150 is formed on the first doped region 141, and the interlayer dielectric layer 150 covers the entire active area AA and the terminal area W.
  • the interlayer dielectric layer 150 and the first doped region 141 are sequentially etched downward to form a contact hole that penetrates the interlayer dielectric layer 150 and the first doped region 141 and exposes the body region 140, and injects a first doped region into the bottom of the contact hole.
  • Doping ions of the second conductivity type that is, doping ions of the second conductivity type are implanted into the exposed body region 140 to form a second doping region 142 at the bottom of the contact hole.
  • the active area AA of the drift region 100 forms an active area AA
  • the terminal area W of the drift region 100 forms a terminal area W. It should be noted that the above ion implantation process is designed for a high-temperature annealing process.
  • the dopant ions in the first floating region 111 and the second floating region 112 will both diffuse outward, so that the first floating region 111 and the second floating region 111 will diffuse outwardly.
  • the range of the doped area of the second floating region 112 is increased.
  • the coverage of the body region 140 is the same as that of the active region AA, that is, the coverage of the body region 140 and the formed active region are the same, and the second trench in the terminal region is close to the active region AA.
  • the groove is adjacent to and in contact with the body region 140, thereby reducing the risk of breakdown from the side of the body region 140 and improving the stability of the device.
  • a metal is filled in the through hole to form a contact hole, and a first electrode 210 that contacts the top of the contact hole is formed on the interlayer dielectric layer 150.
  • the electrode 210 is in contact with the first doped region 141 and the second doped region 142 through the contact hole.
  • the above trench gate semiconductor device should also form a gate electrode electrically connected to the gate conductive layer 132 (the gate electrode is not shown in the figure) and a second electrode connected to the drift region 100 220.
  • a gate electrode electrically connected to the gate conductive layer 132 (the gate electrode is not shown in the figure) and a second electrode connected to the drift region 100 220.
  • One of the first electrode 210 and the second electrode 220 serves as a current input terminal, and the other serves as a current output terminal.
  • the arrangement of the second electrode 220 may have various forms.
  • the trench gate semiconductor device includes an IGBT, and the first electrode 210 is an emitter.
  • the semiconductor device on the trench further includes a collector region 170 and a second The electrode 220.
  • the second electrode 220 is a collector.
  • the collector region 170 is located on the side of the drift region 100 away from the body region 140, and the collector region 170 has the second conductivity type; the collector electrode is electrically connected to the collector region 170.
  • a buffer zone 160 can also be formed between the collector region 170 and the drift region 100.
  • the buffer zone 160 has the first conductivity type and the doping concentration of the buffer zone 160 is higher than the doping concentration of the drift region 100.
  • the introduction of the first dielectric structure 121 and the first floating region 111 under the trench gate can not only improve the withstand voltage of the device, but also reduce the switching capacitance of the IGBT and the turn-on voltage of the device. drop.
  • the trench gate semiconductor device includes a MOS tube, and the first electrode 210 is a source.
  • the trench gate semiconductor device includes a second electrode 220.
  • the second electrode 220 is a drain.
  • the second electrode is located on a side of the drift region 100 away from the body region 140 and is electrically connected to the drift region 100. Further, the drift region 100 is formed on the front surface of the semiconductor substrate 180, and the drain is formed on the back surface of the semiconductor substrate 180.
  • the first dielectric structure 121 and the first floating area 111 are formed in the active area AA, and the second dielectric structure 122 and the second floating area 112 are formed in the terminal area W, which can enhance the device's performance
  • the second dielectric structure 122 and the first dielectric structure 121 are formed simultaneously, and the first floating area 111 and the second floating area 112 are also formed simultaneously. That is, the structure of the terminal area W is in the structure of the active area AA.
  • the preparation is completed simultaneously, no additional process is added to the preparation of the terminal area W structure, and the process is relatively simple.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种沟槽栅半导体器件及其制备方法，该器件包括有源区(101)和位于有源区(101)外围的终端区(102)，其中，有源区(101)包括：漂移区(100)、位于漂移区(100)上的体区(140)以及位于体区(140)上的第一掺杂区(141)和第二掺杂区(142)，沟槽栅是通过对第一沟槽进行填充所形成，第一沟槽穿透第一掺杂区(141)和体区(140)并延伸至漂移区(100)内，第一沟槽内填充有与漂移区(100)电隔离的栅导电层(132)，第一沟槽侧壁上形成有位于栅导电层(132)与体区(140)之间的栅介质层(131)；终端区(102)包括填充于第二沟槽内的第二介质结构(122)和包围第二介质结构(122)底部的第二浮空区(112)，第二沟槽开设于漂移区(100)上。

Description

沟槽栅半导体器件及其制备方法
相关申请的交叉引用
本申请要求于2020年05月11日提交中国专利局、申请号为2020103906066、发明名称为“沟槽栅半导体器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，尤其涉及一种沟槽栅半导体器件及其制备方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
半导体器件通常包括有源区和包围有源区的终端区，有源区和终端区均形成于漂移区的不同区域。其中，有源区用于形成具体的沟槽型电子元件如MOS(Metal Oxide Semiconductor，金属氧化物半导体)管或IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)等，终端区位于有源区的外围，通过在终端区设置辅助结构，增强漂移区的耗尽，从而提高半导体器件的耐压能力。
目前，一般是在终端区形成与漂移区导电类型相反的掺杂区，通过在终端区构建PN结以增强漂移区的耗尽。然而，通过PN结增强耗尽的程度有限，为了达到较好的耐压水平，往往需要增大终端掺杂区的掺杂范围。增大终端掺杂区的掺杂范围，虽然能在一定程度上提升漂移区的耐压能力，但是同时也会增大终端区的面积。同时，掺杂区在后续的退火期间会向周围扩散，为了确保相邻掺杂区在退火后不会连成一体，相邻掺杂区之间的间距较大。以上都不利于器件集成度的提高。
发明内容
基于此，有必要针对目前半导体器件终端区面积较大的技术问题，提出一种新的沟槽栅半导体器件及其制备方法。
一种沟槽栅半导体器件，包括有源区和位于所述有源区外围的终端区，其中，所述有源区包括：漂移区，具有第一导电类型；体区，具有第二导电类型，位于所述漂移区上；第一掺杂区，具有第一导电类型，位于所述体区上，所述第一掺杂区中开设有第一沟槽，所述第一沟槽穿透所述第一掺杂区和所述体区并延伸至所述漂移区内；第二掺杂区，具有第二导电类型，位于所述体区上；以及沟槽栅，包括填充于所述第一沟槽内的栅导电层和位于所述第一沟槽的内壁与所述栅导电层间的栅介质层；所述终端区包括：所述漂移区，所述漂移区内开设第二沟槽；第二介质结构，填充于第二沟槽内；以及第二浮空区，具有第二导电类型，位于所述漂移区内且包围所述第二介质结构的底部。
一种沟槽栅半导体器件制备方法，包括：形成具有第一导电类型的漂移区，所述漂移区包括有源区和包围所述有源区的终端区；在所述有源区上开设第一沟槽，在所述终端区开设第二沟槽；在所述第二沟槽底部的漂移区内形成包围第二沟槽底部的具有第二导电类型的第二浮空区；在所述第二沟槽内填充第二介质结构；在所述第一沟槽内壁形成栅介质层，在所述沟槽内填充栅导电层；对所述漂移区的有源区进行离子注入，形成具有第二导电类型的体区；以及对所述体区进行离子注入形成具有第一导电类型的第一掺杂区和具有第二导电类型的第二掺杂区，所述第一掺杂区与所述第一沟槽相邻并接触。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中沟槽栅半导体器件制备方法的步骤流程图；
图2a～图2k为一实施例对应图1制备方法相关步骤所形成的结构图；
图3为一实施例中沟槽栅半导体器件的结构示意图；
图4为另一实施例中沟槽栅半导体器件的结构示意图。
标号说明：
100、漂移区；101、有源区；102、终端区；103、掩膜；104、氧化层；105、隔离层；111、第一浮空区；112、第二浮空区；121；第一介质结构；122、第二介质结构；131、栅介质层；132、栅导电层；140、体区；141、第一掺杂区；142、第二掺杂区；150、层间介质层、160、缓冲区；170、集电区；180、半导体衬底；210、第一电极；211：接触孔；220、第二电极。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图3所示，在本申请中，半导体器件包括有源区AA和位于有源区AA外围的终端区W。其中，有源区AA包括多种掺杂区并用于与电极连接，终端区W用于设置辅助结构以提高半导体器件的耐压，对半导体器件进行保护。
具体的，有源区AA包括漂移区100、体区140、第一掺杂区141、第二掺杂区142和沟槽栅。
其中，漂移区100具有第一导电类型，漂移区100具体可以是在半导体衬底180上通过外延生长而成的外延层。具体的，漂移区100的材料可为硅、锗或锗化硅以及其他任何合适的半导体材料。在本实施例中，漂移区100的 材料为硅。
体区140具有第二导电类型，体区140位于漂移区100上，具体可以是对漂移区100的上表层进行掺杂，使漂移区100的上表层由第一导电类型转变为第二导电类型，形成上述体区140。
第一掺杂区141和第二掺杂区142均形成于体区140上，其中，第一掺杂区141具有第一导电类型，第二掺杂区142具有第二导电类型，且第二掺杂区142的掺杂浓度高于体区140的掺杂浓度。具体的，第一掺杂区141和第二掺杂区142为对不同位置的体区140进行掺杂所形成。其中，第一掺杂区141上开设有第一沟槽，该第一沟槽依次穿透第一掺杂区141和体区140并延伸至漂移区100内。
沟槽栅是通过对第一沟槽进行填充所形成。第一沟槽内填充有与漂移区100电隔离的栅导电层132，且第一沟槽侧壁上形成有位于栅导电层132和体区140之间栅介质层131，栅介质层131和栅导电层132构成栅极结构，栅极结构的栅导电层132引出并与栅电极电连接(栅电极在图中未示出)。可以理解的，第一沟槽由体区140构成的侧壁上均形成有栅介质层131。具体的，栅介质层131可为氧化硅层，栅导电层132可为多晶硅层。
终端区W包括位于漂移区100内的第二介质结构122和第二浮空区112。第二介质结构122填充于第二沟槽内，其中，第二沟槽开设于位于终端区W的漂移区100上，第二介质结构122延伸至漂移区100内。第二浮空区112具有第二导电类型，第二浮空区112位于第二沟槽下方的漂移区100内且包围第二介质结构122的底部。在一实施例中，第二浮空区122的掺杂浓度大于漂移区100的掺杂浓度，提高第二浮空区122的掺杂浓度，可以增大第二浮空区122对漂移区100的耗尽。具体的，第二介质结构122可为由一种介质材料构成的单一结构，也可为由多种介质材料构成的复合结构。具体的，第二介质结构122包括氮化硅、氧化硅、氮氧化硅中的任意一种或多种。在本实施例中，第二介质结构122可为氧化硅。
上述第一导电类型与第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型则为N型。在本实施例中，第一导电类型为N型，第二导电类型为P型。
在本申请中，栅导电层132引出至栅电极(栅电极在图中未示出)，通过沟槽栅控制沟槽栅两侧体区140的载流子分布状态，使沟槽栅两侧体区140形成反型区，该反型区作为导电沟道接通第一掺杂区141和漂移区100，由此使得半导体器件导通。当半导体器件关断时，半导体器件的耐压能力取决于漂移区100所能承受电压的大小。在本申请中，终端区W设置的辅助结构包括第二介质结构122和第二浮空区112。其中，第二介质结构122延伸至漂移区100内，通过第二介质结构122可以提高漂移区100的反向击穿电压。同时，第二介质结构122的尺寸不受退火的影响，在退火后，第二介质结构122所占据的面积较小，从而可以提高第二介质结构122的分布密度，使得半导体器件的耐压水平更高。换言之，相比于传统技术，在获取同等耐压水平时，本方案中能够缩小终端面积，有利于提高器件的集成度。同时，本方案还设置有包围第二介质结构122的第二浮空区112，第二浮空区112的导电类型与漂移区100的导电类型相反，即第一浮空区111与漂移区100形成PN结而增强漂移区100的耗尽，第一浮空区111与第二介质结构122结合使用，能够进一步增强漂移区100的耐压能力。
在一实施例中，第一沟槽侧壁上的栅介质层向沟槽底部延伸并覆盖整个第一沟槽内壁。在另一实施例中，继续参考图3所示，在有源区AA，栅介质层131仅形成于第一沟槽的侧壁，栅导电层132与第一沟槽的底部间增设第一介质结构121，第一介质结构121填于第一沟槽的底部且第一介质结构121的上表面低于体区140的下表面。第一介质结构121的厚度大于栅介质层131的厚度。在本实施例中，有源区AA的漂移区100内设置第一介质结构121，可以提升漂移区100的耐压能力。同时，第一介质结构121位于第一沟槽底部，可以降低沟槽底部电场集中的问题，提高器件稳定性。
具体的，第一介质结构121的厚度可根据具体需要设定，第一沟槽深度越深、第一介质结构121越厚，耐压能力越强。在一实施例中，第一沟槽和第二沟槽的深度相同，第一沟槽和第二沟槽可在同一刻蚀过程中同步形成。在另一实施例中，第一沟槽和第二沟槽的深度不同。在一实施例中，第一介质结构121可为由一种介质材料构成的单一结构，也可为由多种介质材料构成的复合结构。具体的，第一介质结构121包括氮化硅、氧化硅、氮氧化硅 中的任意一种或多种。在本实施例中，第一介质结构121与上述第二介质结构122相同，均为氧化硅，第一介质结构121和第二介质结构122可通过沉积工艺在第一沟槽和第二沟槽内同步沉积同种介质材料所形成。
在一实施例中，有源区AA还包括形成于漂移区100内的第一浮空区111，第一浮空区111位于第一沟槽下方并包围第一沟槽内的第一介质结构121。在一实施例中，第一浮空区111的掺杂浓度大于漂移区100的掺杂浓度，第一浮空区111的掺杂浓度较高，可以提高第一浮空区111对漂移区100的耗尽。在一实施例中，第一浮空区111位于第一沟槽下方并最多包围至第一沟槽内的第一介质结构121的厚度的二分之一处。其中，第一浮空区111具有第二导电类型，即第一浮空区111和漂移区100形成PN结，从而可以增强漂移区100的耗尽，进一步提高器件耐压能力。同时，第一浮空区111包围第一沟槽底部，可以避免沟槽底部电场集中，从而提高器件可靠性。
在一实施例中，第二沟槽的深度与漂移区100的厚度之比的范围为1:8～1:15，在该范围内，第二沟槽既能较好地辅助漂移区100耗尽，对漂移区100内电流的干扰也较小。
在一实施例中，在终端区W内，相邻第二沟槽之间的间距沿远离有源区AA的方向增大。由于击穿位置通常位于有源区内或有源区边缘附近，在靠近有源区AA的方向，第二沟槽的分布密度增大，第二沟槽分布越密集，从而增强临近有源区的漂移区的耗尽，由此提高器件耐压。在一具体的实施例中，在终端区W内，相邻第二沟槽之间的间距沿远离有源区AA的方向逐渐增大。在另一具体的实施例中，可将终端区W划分为靠近有源区AA的第一区域和远离有源区AA的第二区域，其中，第一区域内的相邻第二沟槽之间的间距相同，第二区域内的相邻第二沟槽之间的间距也相同，且第一区域内相邻第二沟槽之间的间距小于第二区域内的相邻第二沟槽之间的间距。在其他具体的实施例中，也可以是第一区域内的相邻第二沟槽之间的间距沿远离有源区AA的方向逐渐递增，而第二区域内的相邻第二沟槽之间的间距相同且大于第一区域内的相邻第二沟槽之间的间距。进一步的，相邻第二沟槽之间的间距范围为1～10μm。在一实施例中，有源区AA上的相邻第一沟槽之间的间距沿靠近终端区W的方向上增大，即越靠近终端区W，相邻第一沟槽之间的间距 越大，由于终端区W内设置的第二介质结构112可以辅助终端区的漂移区和靠近终端区的有源区内的漂移区耗尽，因此，在有源区内，在越远离终端区的区域内，需要提升第一沟槽的分布密度来增强漂移区的耗尽，从而提高器件耐压。具体的，相邻第一沟槽之间的间距范围为1～10μm。
在一实施例中，体区140所覆盖的区域定为有源区AA，体区140之外的区域定为终端区W。此时，终端区W临近有源区AA的第二介质结构122的侧面与体区140接触。在本实施例中，第二介质结构122紧靠体区140并包围体区140，可以减小体区140向外扩散的程度，保持体区140的掺杂浓度，同时，第二沟槽体区140相邻并接触，也可以减弱从体区140侧面击穿的风险，从而提高器件的稳定性。
可以理解的，上述沟槽栅半导体器件还设置有多个电极。具体的，可设置与栅导电层132连接的栅电极(栅电极在图中未示出)，通过栅电极接入电压控制信号以控制器件的通断。同时，如图3所示，第一掺杂区141和第二掺杂区142上设有层间介质层150，在层间介质层150上还设置有第一电极210，第一电极210位于第一掺杂区141和第二掺杂区142上方，且与第一掺杂区141和第二掺杂区142电连接。具体可通过接触孔将第一掺杂区141和第二掺杂区142引出至第一电极210。第一电极210自有源区AA延伸至终端区W并覆盖部分第二介质结构122。在本实施例中，位于有源区AA的第一电极210用于与第一掺杂区141和第二掺杂区142电连接，第一电极210超出有源区AA并延伸至终端区W，一方面可以保证第一电极210能覆盖有源区AA内的所有接触孔，同时，延伸至终端区W的第一电极210，还可以充当金属场板，调节终端区W漂移区100的电场，进一步提高漂移区100的耐压能力。
其中，第一掺杂区141和第二掺杂区142在体区140上的位置可灵活设置。例如，在一实施例中，第一掺杂区141和第二掺杂区142均从体区140的上表面向下延伸，即第一掺杂区141和第二掺杂区142处于同一平面，此时，第一掺杂区141和第二掺杂区142分别通过不同的接触孔与第一电极210电连接。在另一实施例中，如图3所示，第一掺杂区141和第二掺杂区142依次叠设于体区140上，具体的，第二掺杂区142位于体区140上并与第一 沟槽间隔设置，第一掺杂区141叠设第二掺杂区142上并向两侧延伸至两侧的第一沟槽处，即，第二掺杂区142的覆盖范围小于叠设于该第二掺杂区142上方的第一掺杂区141的覆盖范围。上述沟槽栅半导体器件还包括层间介质层150和接触孔，其中，层间介质层150位于第一掺杂区141上，第一电极210位于层间介质层150上，接触孔的顶端与第一电极210接触，接触孔的底端穿透层间介质层150和第一掺杂区141并与第二掺杂区142接触。在具体的工艺过程中，可以对体区140的表层进行掺杂，使体区140的表层成第一掺杂区141，然后形成层间介质层150，在层间介质层150上开设穿透层间介质层150、第一掺杂区141并暴露出体区140的接触孔，对所暴露的体区140进行掺杂，在接触孔底部形成第二掺杂区142，沉积金属填充接触孔并形成第一电极210。在本实施例中，第一掺杂区141和第二掺杂区142叠设于体区140上，第一电极210通过同一接触孔同时与第一掺杂区141和第二掺杂区142电连接，相比于第一掺杂区141和第二掺杂区142分别通过不同的接触孔与第一电极210电连接，本实施例中所设置的接触孔数量更少，结构更加简单。
在一实施例中，在第一沟槽两侧的所有体区140均形成第一掺杂区141，即第一掺杂区141的覆盖范围与体区140的覆盖范围相同，各第一沟槽两侧均形成导电沟道。在另一实施例中，第一掺杂区141仅形成于相邻第一沟槽之间的体区140上，在有源区AA最外围的第一沟槽与终端区W之间的体区140未形成第一掺杂区141，此处体区140仅形成第二掺杂区142，第二掺杂区142通过接触孔与第一电极210电连接。若是在有源区AA边缘区域形成寄生三极管，寄生三极管发生雪崩击穿时，会烧毁器件，在本实施例中，在位于有源区AA边缘体区140内未形成第一掺杂区141，即在有源区AA边缘不形成寄生三极管，可以避免上述问题。
可以理解的，在形成上述结构后，上述沟槽栅半导体器件还应形成与漂移区100接通的第二电极220。第一电极210和第二电极220中的其中一个作为电流输入端，另一个作为电流输出端。
根据器件类型的不同，对于第二电极220的设置可具有多种形式。
在一实施例中，如图3所示，上述沟槽栅半导体器件包括IGBT，上述第 一电极210为发射极，除上述结构之外，沟槽上半导体器件还包括集电区170和第二电极220，此时，第二电极220为集电极。其中，集电区170位于漂移区100背离体区140的一侧，且集电区170具有第二导电类型；集电极则与集电区170电连接。进一步的，在集电区170和漂移区100之间，还可形成缓冲区160，缓冲区160具有第一导电类型且缓冲区160的掺杂浓度高于漂移区100的掺杂浓度。当上述沟槽栅半导体器件为IGBT时，在沟槽栅下方引入第一介质结构121和第一浮空区111，除能够提升器件耐压外，还可降低IGBT开关电容以及降低器件导通压降。
在一实施例中，如图4所示，上述沟槽栅半导体器件包括MOS管，上述第一电极210为源极，除上述结构外，沟槽栅半导体器件包括第二电极220，此时，第二电极220为漏极，第二电极位于漂移区100背离所述体区140的一侧且与漂移区100电连接。进一步的，漂移区100进行于半导体衬底180的正面，漏极则形成于半导体衬底180的背面。沟槽栅半导体器件还包括引出的栅电极(栅电极在图中未示出)。
本申请还涉及一种沟槽栅半导体器件的制备方法，用于制备上述沟槽栅半导体器件。如图1所示，该制备方法包括以下步骤：
步骤S210：形成具有第一导电类型的漂移区，所述漂移区包括有源区和包围所述有源区的终端区。
如图2a所示，可在半导体衬底(图中未示出)上通过外延生长，形成具有第一导电类型的漂移区100。漂移区100包括有源区AA和包围有源区AA的终端区W。
步骤S220：在所述有源区开设第一沟槽，在所述终端区开设第二沟槽。
如图2b所示，在有源区AA上开设第一沟槽，在终端区W上开设第二沟槽。在一实施例中，可通过不同的刻蚀步骤分别在有源区AA上开设第一沟槽并在终端区W上开设第二沟槽。在另一实施例中，可在刻蚀步骤中同时开设第一沟槽和第二沟槽，如图2b所示，在漂移区100上形成掩膜103，通过掩膜103在有源区AA和终端区W均定义出刻蚀窗口，同步对漂移区100的有源区AA和终端区W进行刻蚀，在有源区AA和终端区W均刻蚀出沟槽，其中，位于有源区AA的沟槽定义为第一沟槽，位于终端区W的沟槽定 义为第二沟槽。
在一实施例中，第一沟槽和第二沟槽的尺寸相同，即第一沟槽和第二沟槽的深度、开口宽度相同。在另一实施例中，第一沟槽和第二沟槽的尺寸不同，即第一沟槽和第二沟槽的深度、开口宽度不同。其中，第一沟槽的数量和沟槽间距以及第二沟槽的数量和沟槽间距可根据具体需要设定。在一实施例中，所述第二沟槽的深度与所述漂移区的厚度的比值范围为1:8～1:15，所述第一沟槽的深度与所述漂移区的厚度的比值范围也为1:8～1:15。在一实施例中，相邻两个所述第二沟槽的间距沿远离所述有源区的方向增大。在一实施例中，有源区AA上的相邻第一沟槽之间的间距沿靠近终端区W的方向上增大。
在步骤S220之后，可不去除掩膜103而直接执行步骤S230。
步骤S230：在所述第二沟槽底部的漂移区内形成包围第二沟槽底部的具有第二导电类型的第二浮空区。
在一实施例中，在形成第二沟槽后，直接对第二沟槽底部进行离子注入，形成第二浮空区。
在另一实施例中，步骤S230包括以下子步骤：
步骤S231：在所述第二沟槽内壁形成氧化层。
如图2c所示，对第二沟槽内壁进行热氧化，以在第二沟槽内壁上形成氧化层104。
在一实施例中，如图2c所示，在对第二沟槽内壁进行热氧化的同时，对第一沟槽内壁也进行热氧化，即对步骤S220所形成的结构进行热氧化，在第一沟槽和第二沟槽内壁均形成氧化层104，此时，沟槽外部漂移区100的上表面受掩膜103保护而不会被热氧化。
步骤S232：对所述第二沟槽底部的漂移区进行离子注入，形成包围第二沟槽底部的具有第二导电类型的第二浮空区。
如图2d所示，通过第二沟槽对第二沟槽下方的漂移区100进行离子注入，注入离子具有第二导电类型且具有一定的能量，其可穿过沟槽内的氧化层104注入沟槽下方的漂移区100内，在第二沟槽下方形成包围第二沟槽底部的第二浮空区112。
在一实施例中，在通过第二沟槽对第二沟槽下方的漂移区100进行离子注入的同时，对第一沟槽下方的漂移区100也进行离子注入，在第一沟槽下方形成包围第一沟槽底部的第一浮空区111，在第二沟槽下方形成包围第二沟槽的第二浮空区112。在一实施例中，第一浮空区111的掺杂浓度大于漂移区100的掺杂浓度，第二浮空区112的掺杂浓度大于漂移区100的掺杂浓度。
步骤S240：在所述第二沟槽内填充第二介质结构。
如图2e所示，通过沉积工艺在第二沟槽内填入第二介质结构122。
在一实施例中，在第二沟槽内填入第二介质结构的同时，在第一沟槽内填入第一介质结构121，具体的，通过沉积工艺沉积一层较厚的介质结构，该介质结构填满第一沟槽和第二沟槽，将位于第一沟槽内的介质结构定义为第一介质结构121，将位于第二沟槽内的介质结构定义为第二介质结构122，第一介质结构121和第二介质结构122材料相同。在向第一沟槽内填入第一介质结构121之后，回刻第一沟槽内的第一介质结构121，暴露出第一沟槽部分侧壁。如图2f所示，回刻位于第一沟槽顶部的第一介质结构121，保留第一沟槽底部的第一介质结构121，并暴露出第一沟槽部分侧壁。此时，第二沟槽内的第二介质层不受影响，在具体的工艺中，在终端区W形成保护层，对有源区AA进行刻蚀时，终端区W不受刻蚀影响。
在一实施例中，位于漂移区100上的掩膜103被去除。
步骤S250：在所述第一沟槽内壁形成栅介质层，在所述沟槽内填充栅导电层。
如图2g所示，通过热氧化工艺在所暴露的第一沟槽侧壁上形成氧化层作为栅介质层131，通过沉积工艺在第一沟槽内填充栅导电层132，栅介质层131位于栅导电层132和第一沟槽侧壁之间。具体的，栅导电层132可为多晶硅。栅介质层131和栅导电层132形成栅极结构。在一实施例中，在步骤S240中，第一沟槽内未填入第一介质结构121，在步骤S250中，第一沟槽内仅形成栅极结构。在另一实施例中，在步骤S240中，第一沟槽底部填入第一介质结构121，此时，栅介质层131和栅导电层132均位于第一介质结构121上方的第一沟槽内。
在一实施例中，如图2h所示，在填充第一沟槽内填充栅导电层132后， 对栅导电层132进行回刻，使栅导电层132的上表面低于第一沟槽两侧漂移区100的上表面，在栅导电层132上形成隔离层105，隔离层105与漂移区100上表面齐平。
在一实施例中，如图2h所示，第一沟槽底部填充有第一介质结构121，栅介质层131和栅导电层132仅形成于第一介质结构121上方的第一沟槽内，且第一介质结构121的厚度大于栅介质层131的厚度。
步骤S260：对所述漂移区的有源区进行离子注入，形成具有第二导电类型的体区，对所述体区进行离子注入，在所述体区内形成具有第一导电类型的第一掺杂区和具有第二导电类型的第二掺杂区，所述第一掺杂区与所述第一沟槽相邻并接触。
在一实施例中，如图2i所示，先对漂移区100的有源区AA注入具有第二导电类型的掺杂离子，在漂移区100的有源区AA形成具有第二导电类型的体区140。然后对体区140注入具有第一导电类型的掺杂离子，在体区140的表层形成具有第一导电类型的第一掺杂区141。可以理解的，体区140的深度应该不超过栅介质层131的深度，以保证通过上述栅极结构可以控制第一掺杂区141和漂移区100之间的体区140能够形成反型层，从而该反型层作为导电沟道接通第一掺杂区141和漂移区100，从而使器件导通。在一实施例中，当第一沟槽底部形成有第一介质结构121时，体区140的下表面高于第一介质结构121的上表面。如图2j所示，在形成第一掺杂区141后，在第一掺杂区141上形成层间介质层150，层间介质层150覆盖整个有源区AA和终端区W。依次向下刻蚀层间介质层150和第一掺杂区141，形成穿透层间介质层150和第一掺杂区141并暴露出体区140的接触孔，向接触孔底部注入具有第二导电类型的掺杂离子，也即在所暴露的体区140注入具有第二导电类型的掺杂离子，在接触孔底部形成第二掺杂区142。此时，漂移区100的有源区AA形成有源区AA，而漂移区100的终端区W形成终端区W。需要说明的是，上述离子注入工艺设计高温退火过程，在退火期间，第一浮空区111和第二浮空区112的掺杂离子均会向外扩散，使得第一浮空区111和第二浮空区112的掺杂区域范围增大。
在一实施例中，体区140的覆盖范围与有源区AA的覆盖范围相同，即 体区140与所形成的有源区的覆盖范围相同，终端区内靠近有源区AA的第二沟槽与体区140相邻并接触，从而减弱从体区140侧面击穿的风险，提高器件的稳定性。
在一实施例中，如图2k所示，通过沉积工艺，在上述通孔内填入金属形成接触孔，并在层间介质层150上形成于接触孔顶端接触的第一电极210，第一电极210通过接触孔与第一掺杂区141和第二掺杂区142接触。
可以理解的，在形成上述结构后，上述沟槽栅半导体器件还应形成与栅导电层132电连接的栅电极(栅电极在图中未示出)以及与漂移区100接通的第二电极220。第一电极210和第二电极220中的其中一个作为电流输入端，另一个作为电流输出端。
根据器件类型的不同，对于第二电极220的设置可具有多种形式。
在一实施例中，如图3所示，上述沟槽栅半导体器件包括IGBT，上述第一电极210为发射极，除上述结构之外，沟槽上半导体器件还包括集电区170和第二电极220，此时，第二电极220为集电极。其中，集电区170位于漂移区100背离体区140的一侧，且集电区170具有第二导电类型；集电极则与集电区170电连接。进一步的，在集电区170和漂移区100之间，还可形成缓冲区160，缓冲区160具有第一导电类型且缓冲区160的掺杂浓度高于漂移区100的掺杂浓度。当上述沟槽栅半导体器件为IGBT时，在沟槽栅下方引入第一介质结构121和第一浮空区111，除能够提升器件耐压外，还可降低IGBT开关电容以及降低器件导通压降。
在一实施例中，如图4所示，上述沟槽栅半导体器件包括MOS管，上述第一电极210为源极，除上述结构外，沟槽栅半导体器件包括第二电极220，此时，第二电极220为漏极，第二电极位于漂移区100背离所述体区140的一侧且与漂移区100电连接。进一步的，漂移区100进行于半导体衬底180的正面，漏极则形成于半导体衬底180的背面。
上述沟槽栅半导体器件制备方法，在有源区AA形成第一介质结构121和第一浮空区111，在终端区W形成第二介质结构122和第二浮空区112，能够增强器件的耐压能力，且第二介质结构122和第一介质结构121同步形成、第一浮空区111和第二浮空区112也同步形成，即终端区W的结构在制 备有源区AA的结构的同时同步制备完成，制备终端区W结构并未增加额外的工序，工艺制程相对简单。
以上实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种沟槽栅半导体器件，包括有源区和位于所述有源区外围的终端区，所述有源区包括：
    漂移区，具有第一导电类型；
    体区，具有第二导电类型，位于所述漂移区上；
    第一掺杂区，具有第一导电类型，位于所述体区上，所述第一掺杂区中开设有第一沟槽，所述第一沟槽穿透所述第一掺杂区和所述体区并延伸至所述漂移区内；
    第二掺杂区，具有第二导电类型，位于所述体区上；以及
    沟槽栅，包括填充于所述第一沟槽内的栅导电层和位于所述第一沟槽的内壁与所述栅导电层间的栅介质层；
    所述终端区包括：
    所述漂移区，所述漂移区内开设第二沟槽；
    第二介质结构，填充于第二沟槽内；以及
    第二浮空区，具有第二导电类型，位于所述漂移区内且包围所述第二介质结构的底部。
  2. 如权利要求1所述的沟槽栅半导体器件，其特征在于，
    所述第一沟槽底部填充有第一介质结构，所述第一介质结构的上表面低于所述体区的下表面，所述栅介质层和所述栅导电层位于所述第一介质结构的上方，所述第一介质结构的厚度大于所述栅介质层的厚度；
    所述有源区还包括第一浮空区，所述第一浮空区具有第二导电类型，位于所述漂移区内且包围所述第一介质结构的底部。
  3. 如权利要求2所述的沟槽栅半导体器件，其特征在于，所述第一浮空区的掺杂浓度大于所述漂移区的掺杂浓度。
  4. 如权利要求1所述的沟槽栅半导体器件，其特征在于，所述第二沟槽的深度与所述漂移区的厚度的比值范围为1:8～1:15。
  5. 如权利要求1所述的沟槽栅半导体器件，其特征在于，相邻两个所述第二沟槽的间距沿远离所述有源区的方向增大。
  6. 如权利要求1所述的沟槽栅半导体器件，其特征在于，相邻所述第二沟槽的间距范围为1至10微米。
  7. 如权利要求1所述的沟槽栅半导体器件，其特征在于，所述第二浮空区的掺杂浓度大于所述漂移区的掺杂浓度。
  8. 如权利要求1所述的沟槽栅半导体器件，其特征在于，所述体区的覆盖范围与所述有源区的覆盖范围相同，所述终端区的靠近所述有源区的第二沟槽与所述体区相邻并接触。
  9. 如权利要求1所述的沟槽栅半导体器件，其特征在于，还包括：
    栅电极，与所述栅导电层电连接；以及
    第一电极，位于所述第一掺杂区和所述第二掺杂区上方并与所述第一掺杂区和第二掺杂区电连接，所述第一电极自所述有源区延伸至所述终端区的至少一个所述第二沟槽的上方。
  10. 如权利要求1所述的沟槽栅半导体器件，其特征在于，相邻所述第一沟槽之间的间距范围为1至10微米。
  11. 一种沟槽栅半导体器件制备方法，包括：
    形成具有第一导电类型的漂移区，所述漂移区包括有源区和包围所述有源区的终端区；
    在所述有源区上开设第一沟槽，在所述终端区开设第二沟槽；
    在所述第二沟槽底部的漂移区内形成包围第二沟槽底部的具有第二导电类型的第二浮空区；
    在所述第二沟槽内填充第二介质结构；
    在所述第一沟槽内壁形成栅介质层，在所述沟槽内填充栅导电层；
    对所述漂移区的有源区进行离子注入，形成具有第二导电类型的体区；以及
    对所述体区进行离子注入形成具有第一导电类型的第一掺杂区和具有第二导电类型的第二掺杂区，所述第一掺杂区与所述第一沟槽相邻并接触。
  12. 如权利要求11所述的制备方法，其特征在于，所述在所述有源区上开设第一沟槽，在所述终端区开设第二沟槽的步骤中，所述第一沟槽和所述第二沟槽同时开设。
  13. 如权利要求11所述的制备方法，其特征在于：所述在所述第二沟槽底部的漂移区内形成包围第二沟槽底部的具有第二导电类型的第二浮空区，包括：
    先在所述第二沟槽内壁形成氧化层；
    再对所述第二沟槽底部的漂移区进行离子注入，形成包围第二沟槽底部的具有第二导电类型的第二浮空区。
  14. 如权利要求11所述的制备方法，其特征在于，相邻两个所述第二沟槽的间距沿远离所述有源区的方向增大。
  15. 如权利要求11所述的制备方法，其特征在于，所述体区的覆盖范围与所述有源区的覆盖范围相同，所述终端区内的靠近所述有源区的第二沟槽与所述体区相邻并接触。
PCT/CN2020/140339 2020-05-11 2020-12-28 沟槽栅半导体器件及其制备方法 WO2021227518A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010390606.6A CN113644108A (zh) 2020-05-11 2020-05-11 沟槽栅半导体器件及其制备方法
CN202010390606.6 2020-05-11

Publications (1)

Publication Number Publication Date
WO2021227518A1 true WO2021227518A1 (zh) 2021-11-18

Family

ID=78415233

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/140339 WO2021227518A1 (zh) 2020-05-11 2020-12-28 沟槽栅半导体器件及其制备方法

Country Status (2)

Country Link
CN (1) CN113644108A (zh)
WO (1) WO2021227518A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117038674A (zh) * 2023-10-10 2023-11-10 合肥新晶集成电路有限公司 半导体结构及其制备方法
CN117497569A (zh) * 2023-12-28 2024-02-02 苏州华太电子技术股份有限公司 一种双极性场效应管及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101868856A (zh) * 2007-09-21 2010-10-20 飞兆半导体公司 用于功率器件的超结结构及制造方法
CN102403353A (zh) * 2010-09-14 2012-04-04 力士科技股份有限公司 一种沟槽金属氧化物半导体场效应管及其制造方法
CN106356401A (zh) * 2016-11-21 2017-01-25 电子科技大学 一种功率半导体器件的场限环终端结构
CN107634095A (zh) * 2017-09-14 2018-01-26 全球能源互联网研究院 沟槽型半导体功率器件及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005041838B3 (de) * 2005-09-02 2007-02-01 Infineon Technologies Ag Halbleiterbauelement mit platzsparendem Randabschluss und Verfahren zur Herstellung eines solchen Bauelements
CN110137250B (zh) * 2019-04-12 2020-12-29 电子科技大学 一种具有超低导通压降的高速igbt器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101868856A (zh) * 2007-09-21 2010-10-20 飞兆半导体公司 用于功率器件的超结结构及制造方法
CN102403353A (zh) * 2010-09-14 2012-04-04 力士科技股份有限公司 一种沟槽金属氧化物半导体场效应管及其制造方法
CN106356401A (zh) * 2016-11-21 2017-01-25 电子科技大学 一种功率半导体器件的场限环终端结构
CN107634095A (zh) * 2017-09-14 2018-01-26 全球能源互联网研究院 沟槽型半导体功率器件及其制备方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117038674A (zh) * 2023-10-10 2023-11-10 合肥新晶集成电路有限公司 半导体结构及其制备方法
CN117038674B (zh) * 2023-10-10 2023-12-26 合肥新晶集成电路有限公司 半导体结构及其制备方法
CN117497569A (zh) * 2023-12-28 2024-02-02 苏州华太电子技术股份有限公司 一种双极性场效应管及其制备方法
CN117497569B (zh) * 2023-12-28 2024-05-14 苏州华太电子技术股份有限公司 一种双极性场效应管及其制备方法

Also Published As

Publication number Publication date
CN113644108A (zh) 2021-11-12

Similar Documents

Publication Publication Date Title
US20210126117A1 (en) Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region
US6815769B2 (en) Power semiconductor component, IGBT and field-effect transistor
US9105680B2 (en) Insulated gate bipolar transistor
US7999343B2 (en) Semiconductor component with a space-saving edge termination, and method for production of such component
WO2021227518A1 (zh) 沟槽栅半导体器件及其制备方法
US11522075B2 (en) Semiconductor device and method of manufacturing same
WO2021068420A1 (zh) 沟槽型场效应晶体管结构及其制备方法
WO2021232806A1 (zh) 沟槽栅金属氧化物半导体场效应管及其制备方法
WO2021232807A1 (zh) 半导体器件及其制备方法
CN110676306A (zh) 低emi深沟槽隔离平面功率半导体器件及其制备方法
CN111370479A (zh) 沟槽栅功率器件及其制造方法
WO2021114437A1 (zh) 沟槽型场效应晶体管结构及其制备方法
TWI571959B (zh) 改善ｕｉｓ性能的溝槽式功率半導體器件及其製備方法
WO2021232801A1 (zh) Igbt器件及其制备方法
WO2021232802A1 (zh) Igbt器件及其制备方法
CN111261702A (zh) 沟槽型功率器件及其形成方法
CN116313787A (zh) 带有超结结构的绝缘栅双极型晶体管及其制备方法
WO2021082273A1 (zh) 沟槽型场效应晶体管结构及其制备方法
CN113097297A (zh) 功率器件结构及制作方法
WO2021232805A1 (zh) 半导体器件及其制备方法
WO2021232796A1 (zh) 半导体器件及其制备方法
WO2023178895A1 (zh) 碳化硅器件的制造方法
WO2024017136A1 (zh) 一种半导体器件结构及其制备方法
CN215731715U (zh) 集成电路
CN112331716B (zh) 一种半导体器件及其制作方法、家用电器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20935869

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20935869

Country of ref document: EP

Kind code of ref document: A1