WO2021068420A1 - 沟槽型场效应晶体管结构及其制备方法 - Google Patents

沟槽型场效应晶体管结构及其制备方法 Download PDF

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WO2021068420A1
WO2021068420A1 PCT/CN2019/130503 CN2019130503W WO2021068420A1 WO 2021068420 A1 WO2021068420 A1 WO 2021068420A1 CN 2019130503 W CN2019130503 W CN 2019130503W WO 2021068420 A1 WO2021068420 A1 WO 2021068420A1
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layer
shielding
gate
dielectric layer
trench
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PCT/CN2019/130503
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English (en)
French (fr)
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姚鑫
余强
焦伟
桑雨果
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华润微电子（重庆）有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the invention belongs to the field of semiconductor device design and manufacturing, and particularly relates to a trench field effect transistor structure and a preparation method thereof.
  • deep trench power devices Compared with planar power devices, deep trench power devices have the characteristics of high integration, low on-resistance, fast switching speed, and low switching loss. They have been widely used in power conversion and control. Shielded gate trench MOSFET is currently the most advanced power MOSFET device technology, and a deep trench shielded gate is introduced in the drift zone to optimize device performance.
  • the purpose of the present invention is to provide a trench field effect transistor and a manufacturing method, which is used to solve the problem of the unsatisfactory longitudinal electric field distribution on the trench surface during device breakdown in the prior art, which is difficult to be effective Improve the contradiction between breakdown voltage and characteristic on-resistance.
  • the present invention provides a method for fabricating a trench field effect transistor structure.
  • the fabricating method includes the following steps:
  • a plurality of device trenches are formed in the epitaxial layer, a first shielding dielectric layer is formed on the inner wall of the device trenches, and a first shielding gate layer is formed on the surface of the first shielding dielectric layer.
  • the gate layer fills at least the bottom of the device trench, and the upper surface of the first shielding dielectric layer is lower than the upper surface of the first shielding gate layer.
  • the first shielding gate layer and the first shielding dielectric The upper surface of the layer is lower than the upper surface of the epitaxial layer;
  • a second shielding dielectric layer is formed on the first shielding gate layer, the second shielding dielectric layer covers at least the exposed surface of the first shielding gate layer, and a second shielding gate is formed on the second shielding dielectric layer Floor;
  • a gate dielectric layer is formed on the sidewalls of the device trench and the surface of the third shielding dielectric layer to form a gate trench in the device trench, and fill the gate trench to form a gate Floor;
  • At least an upper metal structure electrically connected to the body region and the source is formed in the epitaxial layer, and a lower metal structure electrically connected to the substrate is formed on the side of the substrate away from the epitaxial layer.
  • Metal structure is
  • the present invention also provides a trench field effect transistor structure, wherein the transistor structure is preferably prepared by the method for preparing the trench field effect transistor structure of the present invention, and the trench field effect transistor structure includes:
  • the epitaxial layer of the first doping type, the epitaxial layer is formed on the substrate, and a plurality of device trenches are formed in the epitaxial layer;
  • the first shielding dielectric layer is formed on the bottom and part of the sidewall of the device trench;
  • the first shielding gate layer is formed on the surface of the first shielding dielectric layer, filling at least the bottom of the device trench, and the upper surface of the first shielding dielectric layer is lower than the upper surface of the first shielding gate layer , The upper surfaces of the first shielding gate layer and the first shielding dielectric layer are lower than the upper surface of the epitaxial layer;
  • the second shielding dielectric layer is formed on the first shielding gate layer and covers at least the exposed surface of the first shielding gate layer;
  • the second shielding gate layer is formed on the second shielding dielectric layer
  • the third shielding dielectric layer is formed on the second shielding gate layer and covers at least the exposed surface of the second shielding gate layer;
  • a gate dielectric layer is formed on the sidewall of the device trench and the surface of the third shielding dielectric layer, and the surface of the gate dielectric layer encloses a gate trench;
  • the body region of the second doping type is formed in the epitaxial layer on both sides of the device trench;
  • the source electrode of the first doping type is formed in the body region
  • the upper metal structure is formed at least in the epitaxial layer and is electrically connected to the body region and the source electrode;
  • the lower metal structure is formed on the side of the substrate away from the epitaxial layer and is electrically connected to the substrate.
  • the field-effect transistor structure and preparation method of the present invention can increase the doping concentration of the drift region (epitaxial layer) and optimize the device trench
  • the surface longitudinal electric field distribution can solve the problem that the longitudinal electric field on the trench surface exhibits two peaks in the prior art when the device is broken down, and the electric field drops between the peaks of the electric field, thereby further improving the breakdown voltage and characteristic conduction of the device.
  • the contradictory relationship of resistance can solve the problem that the longitudinal electric field on the trench surface exhibits two peaks in the prior art when the device is broken down, and the electric field drops between the peaks of the electric field, thereby further improving the breakdown voltage and characteristic conduction of the device.
  • Fig. 1 shows a flow chart of the manufacturing process of the trench field effect transistor of the present invention.
  • FIG. 2 shows a schematic diagram of the structure of the device trench formed in the preparation of the transistor of the present invention.
  • FIG. 3 is a diagram showing the formation of the first shielding dielectric material layer and the first shielding gate material layer in the preparation of the transistor of the present invention.
  • FIG. 4 is a diagram showing the formation of the first shielding dielectric layer and the first shielding gate layer in the preparation of the transistor of the present invention.
  • FIG. 5 is a diagram showing the formation of the second shielding dielectric material layer and the second shielding gate layer in the preparation of the transistor of the present invention.
  • FIG. 6 is a diagram showing the formation of the second shielding dielectric layer and the second shielding gate layer in the preparation of the transistor of the present invention.
  • FIG. 7 is a diagram showing the formation of the third shielding dielectric layer in the preparation of the transistor of the present invention.
  • FIG. 8 is a diagram showing the formation of the gate dielectric layer and the gate layer in the preparation of the transistor of the present invention.
  • FIG. 9 is a diagram showing the formation of the body region and the source electrode in the preparation of the transistor of the present invention.
  • FIG. 10 is a diagram showing the formation of the upper metal electrode and the lower metal electrode in the preparation of the transistor of the present invention.
  • Figure 11 shows the device structure provided in the comparative example of the present invention.
  • FIG. 12 is a diagram showing the longitudinal electric field distribution on the trench surface when the device structure shown in FIG. 11 is broken down under blocking conditions.
  • FIG. 13 shows the longitudinal electric field distribution on the surface of the trench when the structure prepared by the method of Embodiment 1 is broken down under blocking conditions.
  • Fig. 14 shows the I-V curves of the device structure of Fig. 11 and the device structure prepared in Example 1 under blocking conditions.
  • Example 15 is a graph showing the normalized concentration of the lightly doped epitaxial layer and the change trend of the device breakdown voltage of the device structure of FIG. 11 and the device structure prepared in Example 1.
  • 16 is a graph showing the change trend of the ratio of the bottom depth of the second shielding gate layer to the device trench depth and the device breakdown voltage in the device structure prepared in the first embodiment.
  • FIG. 17 shows the ratio of the thickness of the second shielding dielectric layer to the thickness of the first shielding dielectric layer and the change trend graph of the breakdown voltage of the device in the device structure prepared in Example 1.
  • the present invention provides a method for manufacturing a trench field effect transistor structure.
  • the manufacturing method includes the following steps:
  • a plurality of device trenches are formed in the epitaxial layer, a first shielding dielectric layer is formed on the inner wall of the device trenches, and a first shielding gate layer is formed on the surface of the first shielding dielectric layer.
  • the gate layer fills at least the bottom of the device trench, and the upper surface of the first shielding dielectric layer is lower than the upper surface of the first shielding gate layer.
  • the first shielding gate layer and the first shielding dielectric The upper surface of the layer is lower than the upper surface of the epitaxial layer;
  • a second shielding dielectric layer is formed on the first shielding gate layer, the second shielding dielectric layer covers at least the exposed surface of the first shielding gate layer, and a second shielding is formed on the second shielding dielectric layer Gate layer
  • a gate dielectric layer is formed on the sidewalls of the device trench and the surface of the third shielding dielectric layer to form a gate trench in the device trench, and fill the gate trench to form a gate Floor;
  • At least an upper metal structure electrically connected to the body region and the source is formed in the epitaxial layer, and a lower metal structure electrically connected to the substrate is formed on the side of the substrate away from the epitaxial layer.
  • Metal structure is
  • This embodiment provides a method for manufacturing a shielded gate trench field effect transistor (SGT MOSFET).
  • the shielded gate trench field effect transistor may be an N-type device or a P-type device. In this embodiment, an N-type device is used. Take the cell as an example.
  • a substrate 100 of a first doping type is provided, and an epitaxial layer 101 of the first doping type is formed on the substrate 100.
  • the first doping type (ie, the first conductivity type) may be P-type doping or N-type doping, and may be implanting the first doping type (
  • the substrate 100 formed by P-type or N-type ions is set according to actual device requirements.
  • the N-type doped substrate 100 is selected.
  • it may be a heavily doped substrate.
  • the bottom 100 for example, may be that the concentration of the first doping type ions doped in the substrate 100 is greater than or equal to 1 ⁇ 10 19 /cm 3 .
  • the substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc.
  • the substrate 100 may be an N++ type doped silicon substrate, for example, it may be 0.001-0.003ohm*cm.
  • the first doping type and the second doping type (ie, the second conductivity type) mentioned later are opposite doping types, and when the first doping type (first conductivity type) semiconductor is an N-type semiconductor
  • the shielded gate trench MOSFET device of the present invention is an N-type device; conversely, the shielded gate trench MOSFET device of the present invention is a P-type device.
  • the doping concentration of the epitaxial layer is between 1E 16 -9E 16 cm -3 .
  • the doping type of the epitaxial layer 102 is consistent with the doping type of the substrate 100.
  • the doping concentration of the epitaxial layer 102 is lower than the doping concentration of the substrate 100
  • the intrinsic epitaxial layer 102 may be formed on the upper surface of the substrate 100 of the first doping type by an epitaxial process, and then the first dopant may be implanted into the intrinsic epitaxial layer 102 through an ion implantation process.
  • Impurity type ions to form the epitaxial layer 102 of the first doping type in another example, an epitaxial process can also be used to directly epitaxially form the second doping type on the upper surface of the substrate 100 of the first doping type.
  • An epitaxial layer 102 of doping type is selected as the N-type monocrystalline silicon epitaxial layer 102.
  • the structural design of the present invention based on the arrangement of the first shielding gate layer and the second shielding gate layer, can increase the same voltage level The concentration of the lower epitaxial layer.
  • the structure of the present invention uses a 30V-300V SGT MOSFET voltage level.
  • the doping concentration of the epitaxial layer is between 1E 16 -9E 16 cm -3 , which can be 6E 16 cm -3 .
  • a plurality of device trenches 102 are formed in the epitaxial layer 101, a first shielding dielectric layer 105 is formed on the inner wall of the device trenches 102, and the A first shielding gate layer 106 is formed on the surface of the first shielding dielectric layer 105.
  • the first shielding gate layer 106 fills at least the bottom of the device trench 102. In one example, as shown in FIG.
  • the material layer of the first shielding gate layer 106 (that is, the first shielding dielectric material layer 103) is filled at least at the bottom of the device trench 102, so that the first shielding gate layer 106 at least fills the device trench 102, and the upper surface of the first shielding dielectric layer 105 is lower than the upper surface of the first shielding gate layer 106, and the upper surface of the first shielding gate layer 106 and the first shielding dielectric layer 105 They are all lower than the upper surface of the epitaxial layer 101.
  • the method of forming the first shielding dielectric layer 105 and the first shielding gate layer 106 includes the following steps:
  • a first shielding dielectric material layer 103 is deposited on the inner wall of the device trench 102, and the first shielding dielectric material layer 103 extends to the epitaxial layer 101 around the device trench 102, as shown in FIG. 3;
  • a first shielding gate material layer 104 is deposited on the surface of the first shielding dielectric material layer 103.
  • the first shielding gate material layer 104 fills the device trenches and extends to the first shielding gate material layer around the device trenches.
  • the first shielding dielectric material layer 103 and the first shielding gate material layer 104 are etched back to obtain the first shielding dielectric layer 105 and the first shielding gate layer 106, as shown in FIG. 4.
  • the thickness of the first shielding dielectric layer 105 is between 1000 angstroms and 9000 angstroms.
  • a number of device trenches 102 are formed in the epitaxial layer 101.
  • the number and arrangement relationship of the device trenches 102 are set according to actual conditions, and a photolithography-etching process can be used.
  • the device trench 102 is formed, and then the first shielding dielectric layer 105 and the first shielding gate layer 106 are prepared in the device trench 102.
  • the first shielding dielectric material layer 103 is formed on the surface of the epitaxial layer 102 around the device trench.
  • the first shielding material layer 103 may include but is not limited to silicon oxide.
  • the shielding dielectric material layer 103 That is, the thickness of the obtained first shielding dielectric layer 105 is not less than 1000 angstroms to achieve a good shielding effect.
  • the thickness of the first shielding dielectric layer 105 may be between 1000 angstroms and 9000 angstroms.
  • processes such as physical vapor deposition, chemical vapor deposition, etc. may be used to fill the groove formed by the first shielding dielectric material layer 103 to form the first shielding gate material layer 104, and the first shielding gate material layer 104
  • the material may include, but is not limited to, polysilicon.
  • the step of re-etching the first shielding dielectric material layer 103 and the first shielding gate material layer 104 where wet etching or dry etching may be used Both are etched back in the manner of etching, or both dry etching and wet etching are combined to form the first shielding dielectric layer 105 and the first shielding gate layer. 106, so that the first shielding gate layer 106 protrudes from the first shielding dielectric layer 105.
  • the first shielding dielectric material layer 103 and the first shielding gate material layer 104 may be different from each other. Two kinds of etching solutions with different corrosion rates are used to etch back the first shielding dielectric material layer 103 and the first shielding gate material layer 104.
  • one etching solution is used to perform the first shielding gate material layer 104 on the first shielding gate material layer 104.
  • the first shielding gate layer 106 is formed by wet etching, and then another etching solution is used to wet-etch the first shielding dielectric material layer 103 to form the first shielding dielectric layer 105; in another example, It may also be formed by a process of dry etching the two materials with different etching ratios.
  • one etching gas is first used to dry etch the first shield gate material layer 104 to form the first shielding gate material layer 104.
  • a shielding gate layer 106 is used to dry-etch the first shielding dielectric material layer 103 with another etching gas to form the first shielding dielectric layer 105.
  • the first shielding dielectric material layer 103 is etched back by wet etching, so that the first shielding gate layer 106 forms a protruding portion protruding from the first shielding dielectric layer 105, and
  • the side of the protruding part is based on the engraving of the first shielding dielectric material layer to form a side groove 107, so that the upper surface of the first shielding dielectric layer 105 is lower than the upper surface of the first shielding gate layer 106. surface.
  • the shape of the bottom of the side groove 107 includes an arc shape.
  • the first shielding dielectric layer 105 is formed by a wet etching method, and side grooves 107 are formed on both sides of the first shielding layer 106 based on the wet etching process.
  • the side groove 107 with an arc-shaped bottom is formed.
  • a second shielding dielectric layer 110 is formed on the first shielding gate layer 106, and the second shielding dielectric layer 110 covers at least the first shielding gate layer 106 The exposed surface, and a second shielding gate layer 109 is formed on the second shielding dielectric layer 110.
  • the second shielding gate layer 109 and the second shielding dielectric layer 110 are formed, wherein, in an example, the second shielding dielectric layer 110 connects the first shielding gate layer 106 It is isolated from the second shielding gate layer 109.
  • the second shielding dielectric layer 110 and the first shielding dielectric layer 105 may jointly connect the first shielding gate layer 106 and The second shielding gate layer 109 is isolated, wherein the material of the second shielding dielectric layer 110 includes but not limited to silicon oxide, and the material of the second shielding gate layer 109 includes but not limited to polysilicon.
  • the method of forming the second shielding dielectric layer 110 and the second shielding gate layer 109 includes the following steps:
  • a second shielding dielectric material layer 108 is formed on the structure where the first shielding dielectric layer 105 and the first shielding gate layer 106 are formed, and the second shielding dielectric material layer 108 is formed on the first shielding dielectric layer
  • the second shielding dielectric material layer 108 is etched back to form the second shielding dielectric layer 110.
  • the first shielding dielectric layer 105, the first shielding gate layer 106, and the exposed sidewalls of the device trench 102 may be formed by chemical vapor deposition to form a continuous
  • the second shielding material layer 108 is deposited on the surface of the second shielding dielectric material layer 108 to form the second shielding gate material layer.
  • a chemical vapor deposition process may be used, and then dry etching and wet etching may be used.
  • the step of etching back to the target depth to form the second shielding gate layer 109 in addition, it also includes the step of performing back-etching on the second shielding dielectric material layer 108 to form the second shielding dielectric layer 110, A dry etching or wet etching process may be used.
  • the second shielding dielectric layer 110 exposes part of the sidewalls of the device trench 102.
  • the second The upper surface of the shielding dielectric layer 110 is flush with the upper surface of the second shielding gate layer 109, which may facilitate the implementation of subsequent processes.
  • the second shielding dielectric layer 110 includes a groove portion formed on the side of the first shielding gate layer 106, and the groove portion is located away from the first shielding gate based on the second shielding dielectric layer 110.
  • the surface of the layer 106 is enclosed, wherein the second shielding gate layer 109 includes a convex portion 109a corresponding to the groove portion and a body portion 109b formed on the convex portion 109a and connected to the convex portion 109a .
  • the second shielding gate layer 109 including the protrusion 109a and the body 109b is formed, wherein the first shielding gate layer 106 protrudes from the first
  • the shielding dielectric layer 105 for example, side grooves 107 are formed on both sides of the first shielding layer 106.
  • the second shielding dielectric material layer 108 is controlled when the second shielding dielectric material layer 108 is formed.
  • the material of the layer 109 can be deposited in the reserved space during deposition to form the convex portion 109a, and then the body portion 109b is formed.
  • the height of the convex portion 109a is between 2000 angstroms. Between 5000 angstroms, which is conducive to the improvement of the longitudinal electric field of the device.
  • the thickness of the second shielding dielectric layer 110 is between 30% and 70% of the thickness of the first shielding dielectric layer 105.
  • the thickness of the second shielding dielectric layer 110 is further controlled to be between 30% and 70% of the thickness of the first shielding dielectric layer 105, where the thickness here refers to The distance from the sidewall of the device trench to the center of the device trench, that is, the thickness of the second shielding dielectric material layer 108 formed is 30% of the thickness of the first shielding material layer 103 formed -70%, such as 35%, 39.7%, 40%, 50%, etc., control the above ratio, so that the breakdown voltage of the device can be improved based on it, which is beneficial to balance the breakdown voltage and the electric field distribution during device breakdown
  • the thickness of the second shielding dielectric layer 110 is set to be less than 60% of the thickness of the first shielding dielectric layer 105, thereby helping to alleviate the deterioration of the electric field distribution inside the device.
  • the bottom of the second shielding gate layer 110 is disposed at a position between 30% and 50% of the depth 102 of the device trench.
  • the depth of the device trench 102 is between 1.2um-9um.
  • the bottom of the second shielding gate layer 110 is controlled to be at 30%-50% of the depth of the device trench 102, that is, the bottom of the second shielding gate layer 110 reaches the device
  • the distance from the top of the trench 102 is 30%-50% of the depth (longitudinal length) of the device trench 102, such as 40%, 43%, or 45%.
  • the above ratio can be controlled to improve the device performance based on it.
  • the breakdown voltage can be beneficial to balance the breakdown voltage and the electric field distribution during device breakdown.
  • the bottom of the second shielding gate layer 110 is set at 30 which is greater than the device trench depth 102.
  • the bottom of the second shielding gate layer 110 is It refers to the bottom of the body portion 109b, that is, the portion directly above the first shielding gate layer.
  • a third shielding dielectric layer 111 is formed on the second shielding gate layer 109, and the third shielding dielectric layer 111 covers at least the exposed area of the second shielding gate layer 109 surface.
  • the thickness of the third shielding dielectric layer 111 is between 2000 angstroms and 4000 angstroms.
  • the third shielding dielectric layer 111 is prepared on the structure where the second shielding gate layer 109 and the second shielding dielectric layer 110 are prepared, and the material of the third shielding dielectric layer 111 includes but not limited to oxidation Silicon, in an example, can be a third shielding dielectric material layer deposited on the upper surface of the second shielding gate layer 109 and the second shielding dielectric layer 110, and it can be used to deposit a third shielding dielectric material layer on the third shielding dielectric material layer.
  • the third shielding dielectric layer 111 with a preset thickness is obtained by engraving back.
  • the third shielding dielectric layer isolates the second shielding gate layer from the gate layer to be subsequently formed.
  • the third shielding dielectric layer 111 is between 2000 angstroms and 4000 angstroms, which is conducive to the realization of the device shielding effect and the isolation effect between the material layers.
  • the thickness here refers to the lower surface of the third shielding dielectric layer 111 and the The vertical distance between corresponding positions on the upper surface of the second shielding gate layer 109.
  • a gate dielectric layer 112 is formed on the surface of the third shielding dielectric layer 111 to form a gate trench in the device trench 102, and in the gate trench The groove is filled to form a gate layer 113.
  • the gate dielectric layer 112 is formed on the surface of the third shielding dielectric layer 111 and extends to the inner wall of the device trench 102, and the upper surface of the gate layer 113 is lower than the epitaxial layer 101
  • the step of forming the gate layer 113 includes depositing a gate material layer in the gate trench, and etching the gate material layer back to form the gate layer 113.
  • a gate dielectric layer 112 is prepared on the structure where the third shielding dielectric layer 111 is formed.
  • the formed third shielding dielectric layer 111 has a flat upper surface and reveals the device The sidewall of the trench 102, the gate dielectric layer 102 is continuously formed on the sidewall of the device trench 102 and the upper surface of the third shielding dielectric layer 111, and the gate dielectric layer 112 surrounds the gate A pole trench, and then the gate layer 113 is formed in the gate trench.
  • the upper surface of the gate dielectric layer 112 is formed flush with the upper surface of the epitaxial layer 101, The formed upper surface of the gate layer 113 is lower than the upper surface of the gate dielectric layer 112 and lower than the upper surface of the epitaxial layer 101.
  • the gate dielectric layer 112 may be formed by a thermal oxidation process.
  • the material of the gate dielectric layer 112 may be a silicon oxide layer or a high dielectric constant dielectric layer, but is not limited to this.
  • the material of the gate layer 113 Including but not limited to polysilicon.
  • a second doping type body region 114 is formed in the epitaxial layer 101 on both sides of the device trench 102, and the body region 114 is formed in the body region 114.
  • the source 115 of the first doping type is shown in S6 in FIG. 1 and FIG. 9.
  • the second doping type represents a doping type opposite to the first doping type. If the first doping type is N-type, the second doping type is P-type, such as The first doping type is P-type, and the second doping type is N-type.
  • ion implantation is performed in the epitaxial layer 101 to form a body region 114, wherein the body region The doping type of 114 is opposite to the doping type of the epitaxial layer 101 and the substrate 100.
  • the depth of the body region 114 is less than the depth of the gate trench, that is, the distance between the bottom of the body region 114 and the bottom of the epitaxial layer 101 is greater than that of the gate trench.
  • the distance between the bottom and the bottom of the epitaxial layer 101, the bottom of the body region 114 and the bottom of the gate trench have a height difference, that is, there is a difference between the bottom of the body region and the bottom of the gate layer. Height difference to further improve the channel control ability of the gate layer 113 to the shielded gate trench field effect transistor.
  • the body region is selected as a P-doped body region.
  • a source electrode 115 is formed in the body region 114. Ion implantation can be performed in the body region to form the source electrode 115.
  • the ion doping type of the source electrode 115 is the same as that of the body region.
  • the doping type of the epitaxial layer 101 and the substrate 100 are the same, which is opposite to the doping type of the body region 114. In this example, N+ type doped silicon is selected.
  • an upper metal structure 118 electrically connected to both the body region 114 and the source electrode 115 is formed at least in the epitaxial layer 101, and is far away from the substrate 100
  • a lower metal structure 119 electrically connected to the substrate 100 is formed on one side of the epitaxial layer 101.
  • the method of forming the upper metal structure 118 includes the following steps:
  • An isolation dielectric layer 116 is deposited on the gate layer 113 and the epitaxial layer 101, and the isolation dielectric layer 116 and the epitaxial layer 101 are etched to form source contact holes and gate contact holes.
  • the bottom of the source contact hole exposes the body region 114, the sidewalls expose the source 115, and the bottom of the gate contact hole exposes the gate layer 113;
  • a conductive material is deposited on the isolation dielectric layer 116 and in the source contact hole and the gate contact hole to form the upper metal structure 118 to realize the electrical connection of the source 115 and the gate layer. Sexual elicitation.
  • the upper metal structure 118 is formed to form the lead-out electrode.
  • the isolation dielectric layer 116 is formed first.
  • the material of the isolation dielectric layer includes but is not limited to a silicon oxide layer.
  • a material layer is deposited and then etched back to a target depth by dry etching or wet etching, wherein the isolation dielectric layer 116 covers the gate layer 113, the gate dielectric layer 112, and
  • the upper surface of the source electrode 115 in contact with the gate dielectric layer optionally, forming the source electrode contact hole and the gate contact hole (not shown in the figure) based on a photolithography-etching process
  • the source contact hole extends through the isolation dielectric layer 116 into the epitaxial layer 101 and contacts the source electrode 115.
  • the source contact hole The bottom of the exposed body region, in an example, the bottom of the source contact hole is lower than the bottom of the source, the body region 114 can be jointly led out through the source 115, in addition, the gate
  • the electrode contact hole penetrates the isolation dielectric layer 116 and extends to expose the gate layer 113, and then a conductive material is deposited to form the upper metal structure, so that the source and gate layers 113 can be led out, wherein the upper metal structure
  • the material of 118 includes but is not limited to tungsten or polysilicon.
  • a lower metal structure is also prepared at the bottom of the substrate 100 to electrically draw the substrate 100 as a metal drain.
  • the material of the lower metal structure 119 includes, but is not limited to, tungsten or polysilicon.
  • the method before depositing the conductive material, the method further includes the step of forming a doped contact region 117 in the body region 114 based on the source contact hole, and the doping type of the doped contact region 117 is the same as that of the body region.
  • the doping type of 114 is the same, and the doped contact region 117 is in contact with the upper metal structure 118.
  • the preparation method of the three-dimensional memory structure further includes the step of preparing a doped contact region 117, and an ion implantation process may be used to perform ion implantation into the body region 114.
  • an ion implantation process may be used to perform ion implantation into the body region 114.
  • the doped contact region 117 is formed on the surface of the body region 114 exposed to the source contact hole, and the doping type of the doped contact region 117 is the same as that of the body region 114.
  • the impurity types are the same.
  • the doping concentration of the doped contact region 117 is greater than the doping concentration of the body region.
  • P+ type doping is selected to reduce contact resistance.
  • the first shielding gate layer 106 is electrically connected to the source electrode 115 through a layout layout.
  • the second shielding gate layer 109 is electrically connected to any one of the source electrode 115 and the gate electrode layer 113 through a layout layout.
  • the first shielding gate layer 106 is electrically connected to the source electrode 115 through a layout layout
  • the second shielding gate layer 109 is connected to the source electrode 115 and the gate layer 113 through a layout layout. Any one of the phases is electrically connected, so that the shielding function of the first shielding gate layer 106 and the second shielding gate layer 109 can be realized.
  • a deep trench shielding gate is introduced in the drift region.
  • the deep trench shielding gate provides mobile charge compensation for the lateral drift region donor, and the vertical electric field of the device changes from the triangle of the traditional trench MOSFET.
  • the distribution is optimized into an approximate trapezoidal distribution, which greatly increases the breakdown voltage of the device; for devices with the same rated voltage, the shielded gate trench MOSFET can increase the doping concentration of the drift region, achieve a lower characteristic on-resistance (Rdson.sp), and improve the breakdown
  • Ron.sp characteristic on-resistance
  • the doping concentration of the epitaxial layer 101 can be 1.3-1.6 times the doping concentration of the epitaxial layer of the traditional shielded-gate trench MOSFET structure, which is beneficial to The characteristic on-resistance of the device is reduced.
  • a second shielding gate layer 109 is provided between the first shielding gate layer 106 and the gate layer 113, and a second shielding dielectric layer 110 is also provided. The structure of the gate layer and the second shielding dielectric layer provides more mobile charges to laterally compensate the donor or acceptor of the drift region, and optimizes the longitudinal electric field distribution on the surface of the device trench.
  • the present invention also provides a trench field effect transistor structure, wherein the field effect transistor structure preferably adopts the field effect transistor structure described in the first embodiment of the present invention.
  • the preparation method is prepared.
  • the trench field effect transistor structure includes:
  • the epitaxial layer 101 of the first doping type, the epitaxial layer 101 is formed on the substrate 100, and a plurality of device trenches 102 are formed in the epitaxial layer 101;
  • the first shielding dielectric layer 105 is formed on the bottom and part of the sidewalls of the device trench 102;
  • the first shielding gate layer 106 is formed at least on the surface of the first shielding dielectric layer 105, and the upper surface of the first shielding dielectric layer 105 is lower than the upper surface of the first shielding gate layer 106.
  • the upper surfaces of the shielding gate layer 106 and the first shielding dielectric layer 105 are lower than the upper surface of the epitaxial layer 101;
  • the second shielding dielectric layer 110 is formed on the first shielding gate layer 106 and covers at least the exposed surface of the first shielding gate layer 106;
  • the second shielding gate layer 109 is formed on the second shielding dielectric layer 110;
  • the third shielding dielectric layer 111 is formed on the second shielding gate layer 109, covering at least the exposed surface of the second shielding gate layer 109;
  • the gate dielectric layer 112 is formed on the sidewall of the device trench 102 and the surface of the third shielding dielectric layer 11, and the surface of the gate dielectric layer 112 encloses a gate trench;
  • the gate layer 113 is filled in the gate trench
  • the body region 114 of the second doping type is formed in the epitaxial layer 101 on both sides of the device trench 102;
  • the source 115 of the first doping type is formed in the body region 114;
  • the upper metal structure 118 is formed at least in the epitaxial layer 101 and is electrically connected to the body region 114 and the source electrode 115;
  • the lower metal structure 119 is formed on the side of the substrate 100 away from the epitaxial layer, and is electrically connected to the substrate.
  • the doping concentration of the epitaxial layer 101 is between 1E 16 -9E 16 cm -3 .
  • the doping type of the epitaxial layer 102 is consistent with the doping type of the substrate 100.
  • the doping concentration of the epitaxial layer 102 is lower than the doping concentration of the substrate 100.
  • the structure of the present invention uses a 30V-300V SGT MOSFET voltage level.
  • the doping concentration of the epitaxial layer is between 1E 16 -9E 16 cm -3 and may be 6E 16 cm -3 .
  • the thickness of the first shielding dielectric layer 105 is between 1000 angstroms and 9000 angstroms.
  • the thickness of the third shielding dielectric layer 111 is between 2000 angstroms and 4000 angstroms.
  • the formed third shielding dielectric layer 111 has a flat upper surface and exposes the sidewalls of the device trench 102, and the gate dielectric layer 102 is continuously formed on the device trench 102 And the upper surface of the third shielding dielectric layer 111, the gate dielectric layer 112 encloses a gate trench, and the gate layer 113 is formed in the gate trench, in an example ,
  • the formed upper surface of the gate dielectric layer 112 is flush with the upper surface of the epitaxial layer 101, and the upper surface of the gate layer 113 is lower than the upper surface of the gate dielectric layer 112 and lower than the upper surface of the gate dielectric layer 112.
  • the upper surface of the epitaxial layer 101 is flush with the upper surface of the epitaxial layer 101, and the upper surface of the gate layer 113 is lower than the upper surface of the gate dielectric layer 112 and lower than the upper surface of the gate dielectric layer 112.
  • the gate dielectric layer 112 may be formed by a thermal oxidation process.
  • the material of the gate dielectric layer 112 may be a silicon oxide layer or a high dielectric constant dielectric layer, but is not limited to this.
  • the material of the gate layer 113 Including but not limited to polysilicon.
  • the second shielding dielectric layer includes a groove portion formed on a side of the first shielding gate layer, and the groove portion is based on a surface of the second shielding dielectric layer away from the first shielding gate layer.
  • the second shielding gate layer includes a convex portion corresponding to the groove portion and a body portion formed on the convex portion and connected to the convex portion.
  • the second shielding gate layer 109 including the protrusion 109a and the body 109b is formed, wherein the first shielding gate layer 106 protrudes from the first
  • the shielding dielectric layer 105 for example, side grooves 107 are formed on both sides of the first shielding layer 106.
  • the second shielding dielectric material layer 108 is controlled when the second shielding dielectric material layer 108 is formed.
  • the material of the layer 109 can be deposited into the reserved space during deposition to form the convex portion 109a, and then the body portion 109b is formed.
  • the height of the convex portion 109a is between 2000 angstroms. Between 5000 angstroms, which is conducive to the improvement of the longitudinal electric field of the device.
  • the thickness of the second shielding dielectric layer 110 is between 30% and 70% of the thickness of the first shielding dielectric layer 105.
  • the thickness of the second shielding dielectric layer 110 is further controlled to be between 30% and 70% of the thickness of the first shielding dielectric layer 105, where the thickness here refers to The distance from the sidewall of the device trench to the center of the device trench, that is, the thickness of the second shielding dielectric material layer 108 formed is 30% of the thickness of the first shielding material layer 103 formed -70%, such as 35%, 39.7%, 40%, 50%, etc.
  • the above ratio can be controlled so that the breakdown voltage of the device can be improved based on it, which can help balance the breakdown voltage and the breakdown time of the device Electric field distribution.
  • the thickness of the second shielding dielectric layer 110 is set to be less than 60% of the thickness of the first shielding dielectric layer 105, thereby helping to alleviate the deterioration of the electric field distribution inside the device.
  • the bottom of the second shielding gate layer 110 is disposed at a position between 30% and 50% of the depth 102 of the device trench.
  • the depth of the device trench 102 is between 1.2um-9um.
  • the bottom of the second shielding gate layer 110 is controlled to be at 30%-50% of the depth of the device trench 102, that is, the bottom of the second shielding gate layer 110 reaches the device
  • the distance from the top of the trench 102 is 30%-50% of the depth (longitudinal length) of the device trench 102, such as 40%, 43%, or 45%.
  • the above ratio can be controlled to improve the device performance based on it.
  • the breakdown voltage can be beneficial to balance the breakdown voltage and the electric field distribution during device breakdown.
  • the bottom of the second shielding gate layer 110 is set at 30 which is greater than the device trench depth 102. %, so as to help alleviate the deterioration of the internal electric field distribution of the device.
  • the second doping type represents a doping type opposite to the first doping type. If the first doping type is N-type, the second doping type is P-type, such as The first doping type is P-type, and the second doping type is N-type.
  • the doping type of the body region 114 is the same as that of the epitaxial layer 101 and the substrate 100. The doping type is opposite.
  • the depth of the body region 114 is less than the depth of the gate trench, that is, the distance between the bottom of the body region 114 and the bottom of the epitaxial layer 101 is greater than that of the bottom of the epitaxial layer 101.
  • the distance between the bottom of the gate trench and the bottom of the epitaxial layer 101, the bottom of the body region 114 and the bottom of the gate trench have a height difference, that is, the bottom of the body region and the bottom of the gate layer There is a height difference between the bottoms to further improve the channel control ability of the gate layer 113 to the shielded gate trench field effect transistor.
  • the body region is selected as a P-doped body region.
  • the ion doping type of the source electrode 115 is the same as the doping type of the epitaxial layer 101 and the substrate 100, which is opposite to the doping type of the body region 114.
  • N+ type doping is selected Of silicon.
  • the three-dimensional memory structure further includes a doped contact region 117, the doped contact region 117 is formed on the surface of the body region 114 exposed to the source contact hole, and the doped contact region 117
  • the doping type is consistent with the doping type of the body region 114.
  • the doping concentration of the doped contact region 117 is greater than the doping concentration of the body region.
  • P+ Type doping to reduce contact resistance.
  • the first shielding gate layer 106 is electrically connected to the source electrode 115 through a layout layout.
  • the second shielding gate layer 109 is electrically connected to any one of the source electrode 115 and the gate electrode layer 113 through a layout layout.
  • the first shielding gate layer 106 is electrically connected to the source electrode 115 through a layout layout
  • the second shielding gate layer 109 is connected to the source electrode 115 and the gate layer 113 through a layout layout. Any one of the phases is electrically connected, so that the shielding function of the first shielding gate layer 106 and the second shielding gate layer 109 can be realized.
  • the present invention provides a comparative example.
  • an N-type device is taken as an example.
  • the cell structure includes: a lightly doped N-type epitaxial layer 201 formed on a heavily doped N++-type silicon substrate On 200, the metal drain 212 is formed under the heavily doped N++ type silicon substrate 200; the deep trench 202 is formed in the lightly doped N-type epitaxial layer 201, and the sidewall of the deep trench 202 is long with a shielding oxide layer 203 , The deep trench 202 is filled with shielding polysilicon 204 and gate polysilicon 205; the shielding polysilicon 204 and the gate polysilicon 205 are separated by an oxide layer 206; the P-type body region 207 is formed on the surface of the lightly doped N-type epitaxial layer 201 The source region 208 is formed in the P-type body region 207; the contact hole penetrates the oxide dielectric layer 209 and the source region 208 into the P-type body region 207; the metal source
  • the substrate 100 is selected as a heavily doped N++ type silicon substrate, and the epitaxial layer 101 is selected as a lightly doped silicon substrate.
  • N-type epitaxial layer, the body region is selected as P-type doping, and the first shielding dielectric layer 105, the second shielding dielectric layer 110, the third shielding dielectric layer 111 and the isolation dielectric layer 116 are all selected as silicon oxide,
  • the first shielding gate layer 106, the second shielding gate layer 109, and the gate layer 113 are all selected to be polysilicon, wherein the first shielding gate layer 106 is connected to the source 115 through layout, and the second shielding gate layer 109 Equipotential with source 115.
  • the TCAD simulation tool sentaurus was used to simulate the shielded gate trench MOSFET device shown in Figure 11, and Figure 12 is the longitudinal direction of the trench surface when the shielded gate trench MOSFET structure shown in Figure 11 breaks down under blocking conditions.
  • the electric field distribution diagram it can be seen that the shielded gate trench MOSFET structure shown in Figure 11, when the device is blocking the breakdown condition, the longitudinal electric field on the surface of the device trench is shown in Figure 12: two peaks (one is located in the P-type body region/ N-type epitaxial junction, the other is located at the bottom of the deep trench), especially when the electric field drops severely between two electric field peaks.
  • conventional shielded gate trench MOSFETs cannot sufficiently improve the drift region doping.
  • the TCAD simulation tool sentaurus was used to simulate the trench field-effect transistor prepared by the scheme of the first embodiment of the present invention.
  • the concentration of the lightly doped N-type epitaxial layer 101 is the same as the rated voltage.
  • FIG. 11 The shielded gate trench MOSFET structure shown is 1.45 times the concentration of the lightly doped N-type epitaxial layer 201, the bottom of the second shielding gate layer 109 is set at 43% of the depth of the device trench 102; the thickness of the second shielding dielectric layer 110 is set to the first A shielding dielectric layer 105 is 40% of the thickness; the second shielding gate layer 109 is equipotential with the source 115, and other parameters are consistent with the device structure of FIG. 11.
  • Figure 13 shows the longitudinal electric field distribution on the trench surface when the simulated structure breaks down under blocking conditions. The electric field has three peaks. The third is formed at the second shielding gate layer 109 and the second shielding dielectric layer 110 structure. The peak electric field solves the serious problem of the electric field drop between the two electric field peaks of the shielded gate trench MOSFET structure shown in Figure 11.
  • FIG. 14 is the IV curve of the shielded gate trench MOSFET structure shown in FIG. 11 and the shielded gate trench MOSFET structure of an example of the embodiment of the present invention simulated using the TCAD simulation tool sentaurus under blocking conditions, where the simulated structure
  • the concentration of the lightly doped N-type epitaxial layer 101 is 1.45 times that of the lightly doped N-type epitaxial layer 201 of the shielded gate trench MOSFET structure shown in FIG. 11 for the same rated voltage.
  • the bottom of the second shielded gate layer 109 is set in the device trench.
  • the depth of the groove 102 is 43%; the thickness of the second shielding dielectric layer 110 is set to 39.7% of the thickness of the first shielding dielectric layer 105; the second shielding gate layer 109 is equipotential with the source 115, and other parameters are consistent with the device structure of FIG. It can be seen from FIG. 14 that the breakdown voltage of the shielded gate trench MOSFET structure shown in FIG. 11 is 114V, and the breakdown voltage of the shielded gate trench MOSFET structure proposed in an example of the present invention is 116V.
  • the breakdown voltages of the two analog structures are equivalent;
  • the concentration of the lightly doped N-type epitaxial layer of the shielded gate trench MOSFET structure proposed by the present invention is 1.45 times that of the lightly doped N-type epitaxial layer of the shielded gate trench MOSFET structure of FIG. 11, which means that the shielded gate trench MOSFET proposed by the present invention
  • the characteristic on-resistance (Rdson.sp) of the structural device is superior. From the simulation data, it is concluded that the characteristic on-resistance (Rdson.sp) of the shielded-gate trench MOSFET structure proposed by the present invention is lower than that of the conventional shielded-gate trench MOSFET structure. 19%, further improving the contradictory relationship between the breakdown voltage of the device and the characteristic on-resistance.
  • FIG. 15 is a simulation simulation of the shielded gate trench MOSFET structure shown in FIG. 11 and the lightly doped epitaxial layer of the shielded gate trench MOSFET structure of an example of the present invention.
  • the normalized concentration of the lightly doped epitaxial layer and the device breakdown voltage change trend diagram ; It can be seen from the figure that the concentration of the lightly doped epitaxial layer of the maximum breakdown voltage of the shielded gate trench MOSFET structure proposed by the present invention is 1.5 times the concentration of the lightly doped epitaxial layer of the maximum breakdown voltage of the shielded gate trench MOSFET structure of FIG.
  • the concentration of the lightly doped epitaxial layer 104 of the structure device proposed by the present invention can be set to 1.3-1.6 times the concentration of the lightly doped epitaxial layer of the shielded gate trench MOSFET structure in FIG. 11. Fig.
  • 16 is a simulation simulation of the bottom depth of the second shielding gate layer and the device trench depth in the shielded gate trench MOSFET structure proposed by the present invention and the change trend diagram of the device breakdown voltage; it can be seen from the figure that with the bottom of the second shielding gate layer The ratio of the depth to the device trench depth increases, and the device breakdown voltage first increases and then decreases, and when the ratio of the bottom depth of the second shielding gate layer to the device trench depth is greater than 50%, the device breakdown voltage decreases sharply, considering the breakdown Voltage and electric field distribution during device breakdown, and the bottom position of the second shielding gate layer is set at 30%-50% of the device trench depth.
  • the thickness of the second shielding dielectric layer is set to be 30%-70% of the thickness of the first shielding dielectric layer.
  • the breakdown voltage of the device is mainly related to the concentration and thickness of the epitaxial layer, the thickness of the first shielding oxide layer, and so on.
  • the product curves of all different breakdown voltages are slightly different, but the optimal design range is basically the same.
  • the curve relationship of different types of devices is slightly different, and the difference is small, which can be considered based on consistency.
  • the present invention provides a trench field effect transistor structure and a preparation method thereof. Based on the arrangement of the first shielding gate layer and the second shielding gate layer, the doping concentration of the drift region (epitaxial layer) can be increased, The longitudinal electric field distribution on the trench surface of the device is optimized, which can solve the problem that the vertical electric field on the trench surface exhibits two peaks in the prior art when the device is broken down, and the electric field drops between the peaks of the electric field, thereby further improving the device breakdown.

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Abstract

本发明提供一种沟槽型场效应晶体管结构及其制备方法，制备方法包括：提供衬底(100)，形成外延层；形成若干个器件沟槽(102)，于器件沟槽(102)的内壁形成第一屏蔽介质层(106)及第一屏蔽栅层(105)，第一屏蔽介质层(106)的上表面低于第一屏蔽栅层(105)的上表面，形成第二屏蔽介质层(110)及第二屏蔽栅层(109)；形成第三屏蔽介质层(111)，形成栅介质层(112)及栅极层(113)；形成体区(114)，源极(115)；以及上金属结构(118)和下金属结构(119)。本发明基于第一屏蔽栅层(105)及第二屏蔽栅层(109)的设置，可以提高漂移区(外延层)的掺杂浓度，并优化了器件沟槽表面纵向电场分布，可以解决现有技术中器件击穿时沟槽表面纵向电场呈两个峰值的悬挂式分布，电场峰值之间电场下降严重问题，从而进一步改善了器件击穿电压和特征导通电阻的矛盾关系。

Description

沟槽型场效应晶体管结构及其制备方法 技术领域
本发明属于半导体器件设计及制造领域，特别是涉及一种沟槽型场效应晶体管结构及其制备方法。
背景技术
深沟槽功率器件相较于平面功率器件，具有集成度高、导通电阻低、开关速度快、开关损耗小等特点，已广泛应用于电能变换及控制方面。屏蔽栅沟槽MOSFET是目前最先进的功率MOSFET器件技术，在漂移区内引入深沟槽屏蔽栅，优化器件性能。
然而，现有的屏蔽栅沟槽场效应晶体管击穿时沟槽表面纵向电场分布不理想，例如，呈两个峰值的悬挂式分布，且两个电场峰值之间电场下降严重问题，相同额定电压器件，常规屏蔽栅沟槽MOSFET无法充分有效的提高漂移区掺杂浓度，降低特征导通电阻(Rdson.sp)，难以有效的改善击穿电压和特征导通电阻的矛盾关系。
因此，如何提供一种沟槽型场效应晶体管及制备方法以解决现有上述问题实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种沟槽型场效应晶体管及制备方法，用于解决现有技术中器件击穿时沟槽表面纵向电场分布不理想，难以有效的改善击穿电压和特征导通电阻的矛盾关系等问题。
为实现上述目的及其他相关目的，本发明提供一种沟槽型场效应晶体管结构的制备方法，所述制备方法包括如下步骤：
提供第一掺杂类型的衬底，并于所述衬底上形成所述第一掺杂类型的外延层；
于所述外延层中形成若干个器件沟槽，于所述器件沟槽的内壁形成第一屏蔽介质层，并于所述第一屏蔽介质层表面形成第一屏蔽栅层，所述第一屏蔽栅层至少填充所述器件沟槽的底部，且所述第一屏蔽介质层的上表面低于所述第一屏蔽栅层的上表面，所述第一屏蔽栅层与所述第一屏蔽介质层的上表面均低于所述外延层的上表面；
于所述第一屏蔽栅层上形成第二屏蔽介质层，所述第二屏蔽介质层至少覆盖所述第一屏蔽栅层显露的表面，于所述第二屏蔽介质层上形成第二屏蔽栅层；
于所述第二屏蔽栅层上形成第三屏蔽介质层，所述第三屏蔽介质层至少覆盖所述第二屏蔽栅层显露的表面；
于所述器件沟槽的侧壁及所述第三屏蔽介质层表面形成栅介质层，以于所述器件沟槽中形成栅极沟槽，并在所述栅极沟槽中填充形成栅极层；
于所述器件沟槽两侧的所述外延层中形成第二掺杂类型的体区，并于所述体区中形成所述第一掺杂类型的源极；以及
至少于所述外延层中形成与所述体区及所述源极均电连接的上金属结构，以及于所述衬底远离所述外延层的一侧形成与所述衬底电连接的下金属结构。
本发明还提供一种沟槽型场效应晶体管结构，其中，所述晶体管结构优选采用本发明的沟槽型场效应晶体管结构的制备方法制备得到，所述沟槽型场效应晶体管结构包括：
第一掺杂类型的衬底；
所述第一掺杂类型的外延层，所述外延层形成于所述衬底上，所述外延层中形成有若干个器件沟槽；
第一屏蔽介质层，形成于所述器件沟槽的底部及部分侧壁；
第一屏蔽栅层，形成于所述第一屏蔽介质层表面，至少填充所述器件沟槽的底部，且所述第一屏蔽介质层的上表面低于所述第一屏蔽栅层的上表面，所述第一屏蔽栅层与所述第一屏蔽介质层的上表面均低于所述外延层的上表面；
第二屏蔽介质层，形成于所述第一屏蔽栅层上，至少覆盖所述第一屏蔽栅层显露的表面；
第二屏蔽栅层，形成于所述第二屏蔽介质层上；
第三屏蔽介质层，形成于所述第二屏蔽栅层上，至少覆盖所述第二屏蔽栅层显露的表面；
栅介质层，形成于所述器件沟槽的侧壁及所述第三屏蔽介质层表面，所述栅介质层的表面围成栅极沟槽；
栅极层，填充于所述栅极沟槽中；
第二掺杂类型的体区，形成于所述器件沟槽两侧的所述外延层中；
所述第一掺杂类型的源极，形成于所述体区中；
上金属结构，至少形成于所述外延层中，并于所述体区及所述源极均电连接；以及
下金属结构，形成于所述衬底远离所述外延层的一侧，并与所述衬底电连接。
如上所述，本发明的场效应晶体管结构及其制备方法，基于第一屏蔽栅层及第二屏蔽栅层的设置，可以提高漂移区(外延层)的掺杂浓度，并优化了器件沟槽表面纵向电场分布，可以解决现有技术中器件击穿时沟槽表面纵向电场呈两个峰值的悬挂式分布，电场峰值之间电场下降严重问题，从而进一步改善了器件击穿电压和特征导通电阻的矛盾关系。
附图说明
图1显示为本发明沟槽型场效应晶体管的制备工艺流程图。
图2显示为本发明晶体管制备中形成器件沟槽的结构示意图。
图3显示为本发明晶体管制备中形成第一屏蔽介质材料层及第一屏蔽栅材料层的图示。
图4显示为本发明晶体管制备中形成第一屏蔽介质层及第一屏蔽栅层的图示。
图5显示为本发明晶体管制备中形成第二屏蔽介质材料层及第二屏蔽栅层的图示。
图6显示为本发明晶体管制备中形成第二屏蔽介质层及第二屏蔽栅层的图示。
图7显示为本发明晶体管制备中形成第三屏蔽介质层的图示。
图8显示为本发明晶体管制备中形成栅介质层及栅极层的图示。
图9显示为本发明晶体管制备中形成体区及源极的图示。
图10显示为本发明晶体管制备中形成上金属电极及下金属电极的图示。
图11显示为本发明对比例中提供的器件结构。
图12显示为图11所示器件结构在阻断条件下击穿时沟槽表面纵向电场分布图。
图13显示为采用实施例一方法制备结构在阻断条件下击穿时沟槽表面纵向电场分布。
图14显示为图11器件结构与实施例一制备的器件结构在阻断条件下的I-V曲线。
图15显示为图11器件结构与实施例一制备的器件结构的轻掺杂外延层归一化浓度与器件击穿电压变化趋势图。
图16显示为实施例一制备的器件结构中第二屏蔽栅层底部深度和器件沟槽深度比例与器件击穿电压变化趋势图。
图17显示为实施例一制备的器件结构中第二屏蔽介质层厚度和第一屏蔽介质层厚度比例与器件击穿电压变化趋势图
具体实施方式
实施例一：
如图1-10所示，本发明提供一种沟槽型场效应晶体管结构的制备方法，所述制备方法包括如下步骤：
提供第一掺杂类型的衬底，并于所述衬底上形成所述第一掺杂类型的外延层；
于所述外延层中形成若干个器件沟槽，于所述器件沟槽的内壁形成第一屏蔽介质层，并于所述第一屏蔽介质层表面形成第一屏蔽栅层，所述第一屏蔽栅层至少填充所述器件沟槽的底部，且所述第一屏蔽介质层的上表面低于所述第一屏蔽栅层的上表面，所述第一屏蔽栅层 与所述第一屏蔽介质层的上表面均低于所述外延层的上表面；
于所述第一屏蔽栅层上形成第二屏蔽介质层，所述第二屏蔽介质层至少覆盖所述第一屏蔽栅层显露的表面，并于所述第二屏蔽介质层上形成第二屏蔽栅层；
于所述第二屏蔽栅层上形成第三屏蔽介质层，所述第三屏蔽介质层至少覆盖所述第二屏蔽栅层显露的表面；
于所述器件沟槽的侧壁及所述第三屏蔽介质层表面形成栅介质层，以于所述器件沟槽中形成栅极沟槽，并在所述栅极沟槽中填充形成栅极层；
于所述器件沟槽两侧的所述外延层中形成第二掺杂类型的体区，并于所述体区中形成所述第一掺杂类型的源极；以及
至少于所述外延层中形成与所述体区及所述源极均电连接的上金属结构，以及于所述衬底远离所述外延层的一侧形成与所述衬底电连接的下金属结构。
下面将结合附图详细说明本发明的沟槽型场效应晶体管结构的制备。本实施例提供一种屏蔽栅沟槽场效应晶体管(SGT MOSFET)的制造方法，所述屏蔽栅沟槽场效应晶体管可以为N型器件，也可以为P型器件，本实施例以N型器件元胞为例进行说明。
如图1中的S1及图2所示，提供第一掺杂类型的衬底100，并于所述衬底100上形成所述第一掺杂类型的外延层101。
具体的，所述第一掺杂类型(即第一导电类型)可以是P型掺杂，也可以是N型掺杂，可以为采用离子注入工艺在衬底100中注入第一掺杂类型(P型或N型)的离子而形成的衬底100，以实际器件需求设定，在本示例中，选择为N型掺杂衬底100，另外，在一示例中，可以为重掺杂衬底100，如可以是在所述衬底100中掺杂的第一掺杂类型离子的浓度大于等于1×10 19/cm 3。需要说明的，所述衬底100可以为硅衬底、锗硅衬底、碳化硅衬底等，在本示例中，所述衬底100选用为N++型掺杂的硅衬底，如可以是0.001-0.003ohm*cm。其中，第一掺杂类型与后续提到的第二掺杂类型(即第二导电类型)为相反的掺杂类型，当所述第一掺杂类型(第一导电类型)半导体为N型半导体、第二掺杂类型(第二导电类型)半导体为P型半导体时，本发明的屏蔽栅沟槽MOSFET器件为N型器件；反之，本发明屏蔽栅沟槽MOSFET器件为P型器件。
作为示例，所述外延层的掺杂浓度介于1E 16-9E 16cm -3之间。
具体的，所述外延层102的掺杂类型与所述衬底100的掺杂类型一致，在一示例中，所述外延层102的掺杂浓度低于所述衬底100的掺杂浓度，其中，可以先采用外延工艺在所述第一掺杂类型的所述衬底100的上表面形成本征外延层102，然后再通过离子注入工艺在所 述本征外延层102内注入第一掺杂类型的离子以形成所述第一掺杂类型的外延层102；在另一示例中，还可以采用外延工艺直接在所述第一掺杂类型的衬底100的上表面外延形成所述第一掺杂类型的外延层102。本示例中，所述外延层102选用为N-型单晶硅外延层102，另外，本发明的结构设计，同时基于第一屏蔽栅层及第二屏蔽栅层的布置，可提高同电压级别下外延层的浓度，在一示例中，本发明结构使用30V-300V SGT MOSFET电压级，可选地，外延层的掺杂浓度介于1E 16-9E 16cm -3之间，可以是6E 16cm -3。
如图1中的S2及图2-4所示，于所述外延层101中形成若干个器件沟槽102，于所述器件沟槽102的内壁形成第一屏蔽介质层105，并于所述第一屏蔽介质层105表面形成第一屏蔽栅层106，所述第一屏蔽栅层106至少填充所述器件沟槽102的底部，在一示例中，参见图3所示，可以是形成所述第一屏蔽栅层106的材料层(即所述第一屏蔽介质材料层103)至少填充于所述器件沟槽102的底部，从而使得所述第一屏蔽栅层106至少填充所述器件沟槽102的底部，且所述第一屏蔽介质层105的上表面低于所述第一屏蔽栅层106的上表面，所述第一屏蔽栅层106与所述第一屏蔽介质层105的上表面均低于所述外延层101的上表面。
作为示例，形成所述第一屏蔽介质层105及所述第一屏蔽栅层106的方法包括如下步骤：
于所述器件沟槽102的内壁沉积第一屏蔽介质材料层103，所述第一屏蔽介质材料层103延伸至所述器件沟槽102周围的所述外延层101上，如图3所示；
于所述第一屏蔽介质材料层103表面沉积第一屏蔽栅材料层104，所述第一屏蔽栅材料层104填充满所述器件沟槽并延伸至所述器件沟槽周围的所述第一屏蔽介质材料层104上，如图3所示；
对所述第一屏蔽介质材料层103及所述第一屏蔽栅材料层104进行回刻，以得到所述第一屏蔽介质层105及所述第一屏蔽栅层106，如图4所示。
作为示例，所述第一屏蔽介质层105的厚度介于1000埃-9000埃。
具体的，该步骤中，首先于所述外延层101中形成若干个器件沟槽102，所述器件沟槽102的个数及布置关系依据实际情况设定，可以采用光刻-刻蚀的工艺形成所述器件沟槽102，接着在所述器件沟槽102中制备所述第一屏蔽介质层105及所述第一屏蔽栅层106，在一示例中，基于所述第一屏蔽介质材料层103及所述第二屏蔽栅材料层104形成所述第一屏蔽介质层105及所述第一屏蔽栅层106，其中，可以采用热氧化工艺于所述器件沟槽102的底部、侧壁及器件沟槽周围的外延层102表面形成所述第一屏蔽介质材料层103，所述第一屏蔽材料层103可以包括但不限于氧化硅，在一可选示例中，所述屏蔽介质材料层103，也即得到的所述第一屏蔽介质层105的厚度不小于1000埃，以达到良好的屏蔽效果，例如，所述第一 屏蔽介质层105的厚度可以介于1000埃-9000埃之间。另外，可以采用物理气相沉积、化学气相沉积等工艺于所述第一屏蔽介质材料层103所形成的槽体中填充形成所述第一屏蔽栅材料层104，所述第一屏蔽栅材料层104的材料可以包括但不限于多晶硅，另外，还包括对所述第一屏蔽介质材料层103及所述第一屏蔽栅材料层104进行回刻的步骤，其中，可以采用湿法腐蚀或干法刻蚀的方式对二者进行回刻，也可以是干法刻蚀和湿法腐蚀相结合的方式对二者进行回刻，从而形成所述第一屏蔽介质层105及所述第一屏蔽栅层106，使得所述第一屏蔽栅层106凸出于所述第一屏蔽介质层105，例如，可以是采用对所述第一屏蔽介质材料层103及所述第一屏蔽栅材料层104具有不同腐蚀速率的两种腐蚀液对所述第一屏蔽介质材料层103及所述第一屏蔽栅材料层104进行回刻形成，如先采用一种腐蚀液对所述第一屏蔽栅材料层104进行湿法腐蚀形成所述第一屏蔽栅层106，再采用另外一种腐蚀液对所述第一屏蔽介质材料层103进行湿法腐蚀形成所述第一屏蔽介质层105；在另一示例中，还可以是采用对两种材料刻蚀比不同的气体进行干法刻蚀的工艺形成，如先采用一种刻蚀气体对所述第一屏蔽栅材料层104进行干法刻蚀形成所述第一屏蔽栅层106，再采用另外一种刻蚀气体对所述第一屏蔽介质材料层103进行干法刻蚀形成所述第一屏蔽介质层105。
作为示例，采用湿法刻蚀对所述第一屏蔽介质材料层103进行回刻，使所述第一屏蔽栅层106形成凸出于所述第一屏蔽介质层105的凸出部分，所述凸出部分的侧部基于所述第一屏蔽介质材料层的回刻形成侧边凹槽107，以使所述第一屏蔽介质层105的上表面低于所述第一屏蔽栅层106的上表面。
作为示例，所述侧边凹槽107的底部的形状包括弧形。
具体的，在一示例中，采用湿法腐蚀的方法形成所述第一屏蔽介质层105，基于所述湿法腐蚀工艺在所述第一屏蔽删层106的两侧形成侧边凹槽107，在一可选示例中，形成弧形底部的所述侧边凹槽107。
如图1中的S3及图5-6所示，于所述第一屏蔽栅层106上形成第二屏蔽介质层110，所述第二屏蔽介质层110至少覆盖所述第一屏蔽栅层106显露的表面，并于所述第二屏蔽介质层110上形成第二屏蔽栅层109。
具体的，该步骤中，形成所述第二屏蔽栅层109及所述第二屏蔽介质层110，其中，在一示例中，所述第二屏蔽介质层110将所述第一屏蔽栅层106与所述第二屏蔽栅层109相隔离，当然，在其他示例中，也可以是所述第二屏蔽介质层110和所述第一屏蔽介质层105共同将所述第一屏蔽栅层106及所述第二屏蔽栅层109相隔离，其中，所述第二屏蔽介质层110的材料包括但不限于氧化硅，所述第二屏蔽栅层109的材料包括但不限于多晶硅。
作为示例，形成所述第二屏蔽介质层110及所述第二屏蔽栅层109的方法包括如下步骤：
于形成有所述第一屏蔽介质层105及所述第一屏蔽栅层106的结构上形成第二屏蔽介质材料层108，所述第二屏蔽介质材料层108形成于所述第一屏蔽介质层105的上表面、所述第一屏蔽栅层106上表面并延伸至所述器件沟槽102的侧壁及所述器件沟槽102周围的所述外延层101表面；
于所述第二屏蔽介质材料层108表面形成所述第二屏蔽栅层109；以及
对所述第二屏蔽介质材料层108进行回刻，以形成所述第二屏蔽介质层110。
具体的，在一示例中，可以通过化学气相沉积在已经形成的所述第一屏蔽介质层105、所述第一屏蔽栅层106以及所述器件沟槽102显露的侧壁上形成连续的所述第二屏蔽材料层108，再在所述第二屏蔽介质材料层108表面进行沉积形成所述第二屏蔽栅材料层，如可以采用化学气相沉积的工艺，再通过干法刻蚀和湿法刻蚀回刻到目标深度的步骤，以形成所述第二屏蔽栅层109，另外，还包括对所述第二屏蔽介质材料层108进行回刻形成所述第二屏蔽介质层110的步骤，可以采用干法刻蚀或湿法刻蚀的工艺，在一可选示例中，所述第二屏蔽介质层110显露所述器件沟槽102的部分侧壁，在一示例中，所述第二屏蔽介质层110的上表面与所述第二屏蔽栅层109的上表面相平齐，从而可以有利于后续工艺的实施。
作为示例，所述第二屏蔽介质层110包括形成于所述第一屏蔽栅层106侧部的凹槽部，所述凹槽部基于所述第二屏蔽介质层110远离所述第一屏蔽栅层106的表面围成，其中，所述第二屏蔽栅层109包括与所述凹槽部对应的凸部109a以及形成于所述凸部109a上并与所述凸部109a连接的体部109b。
具体的，在一示例中，形成一种包括所述凸部109a及所述体部109b的所述第二屏蔽栅层109，其中，所述第一屏蔽栅层106凸出于所述第一屏蔽介质层105，例如，在所述第一屏蔽删层106的两侧形成侧边凹槽107，此时，形成所述第二屏蔽介质材料层108时控制所述第二屏蔽介质材料层108之间还保留有预留空间，即形成于所述侧边凹槽107中的所述第二屏蔽材料层108之间还留有所述预留空间，从而使得在进行所述第二屏蔽栅层109的材料沉积时可以沉积到所述预留空间中，形成所述凸部109a，进行形成所述体部109b，在一可选示例中，所述凸部109a的高度介于2000埃-5000埃之间，从而有利于器件纵向电场的改善。
作为示例，所述第二屏蔽介质层110的厚度介于所述第一屏蔽介质层105的厚度的30％-70％之间。
具体的，在一示例中，还控制所述第二屏蔽介质层110的厚度介于所述第一屏蔽介质层105的厚度的30％-70％之间，其中，这里的厚度指的是自所述器件沟槽的侧壁至所述器件沟 槽中心的距离，也即形成的所述第二屏蔽介质材料层108的厚度介于形成的所述第一屏蔽材料层103的厚度的30％-70％之间，如可以是35％、39.7％、40％、50％等，控制上述比例，从而可以基于其改善器件的击穿电压，有利于平衡击穿电压和器件击穿时电场分布，另外，在一示例中，设置所述第二屏蔽介质层110的厚度小于所述第一屏蔽介质层105的厚度的60％，从而有利于缓解器件内部电场分布的恶化。
作为示例，所述第二屏蔽栅层110的底部设置在所述器件沟槽深度102的30％-50％之间的位置。
作为示例，所述器件沟槽102的深度介于1.2um-9um之间。
具体的，在一示例中，控制所述第二屏蔽栅层110的底部在所述器件沟槽102深度的30％-50％处，即所述第二屏蔽栅层110的底部到所述器件沟槽102的顶部的距离是所述器件沟槽102的深度(纵向长度)的30％-50％，如可以是40％、43％、45％，控制上述比例，从而可以基于其改善器件的击穿电压，从而可以有利于平衡击穿电压和器件击穿时电场分布，另外，在一示例中，设置所述第二屏蔽栅层110的底部设置在大于所述器件沟槽深度102的30％处，从而有利于缓解器件内部电场分布的恶化，其中，当所述第二屏蔽栅层109包括所述体部109b及所述凸部109a时，所述第二屏蔽栅层110的底部是指所述体部109b的底部，即位于所述第一屏蔽栅层正上方的部分。
如图1中的S4及图7所示，于所述第二屏蔽栅层109上形成第三屏蔽介质层111，所述第三屏蔽介质层111至少覆盖所述第二屏蔽栅层109显露的表面。
作为示例，所述第三屏蔽介质层111的厚度介于2000埃-4000埃之间。
具体的，在一示例中，在制备得到第二屏蔽栅层109及第二屏蔽介质层110的结构上制备第三屏蔽介质层111，所述第三屏蔽介质层111的材料包括但不限于氧化硅，在一示例中，可以是在所述第二屏蔽栅层109及所述第二屏蔽介质层110的上表面沉积第三屏蔽介质材料层，可以是对所述第三屏蔽介质材料层进行回刻得到预设厚度的所述第三屏蔽介质层111，所述第三屏蔽介质层将所述第二屏蔽栅层与后续形成的栅极层隔离，在一示例中，所述第三屏蔽介质层111的厚度介于2000埃-4000埃之间，有利于器件屏蔽效果及材料层之间隔离效果的实现，这里的厚度指的是所述第三屏蔽介质层111的下表面与所述第二屏蔽栅层109上表面对应位置之间的竖直距离。
如图1中的S5及图8所示，于所述第三屏蔽介质层111表面形成栅介质层112，以于所述器件沟槽102中形成栅极沟槽，并在所述栅极沟槽中填充形成栅极层113。
作为示例，所述栅极介质层112形成于所述第三屏蔽介质层111表面并延伸至所述器件 沟槽102的内壁上，所述栅极层113的上表面低于所述外延层101的上表面，其中，形成所述栅极层113的步骤包括：于所述栅极沟槽中沉积栅极材料层，对所述栅极材料层进行回刻以形成所述栅极层113。
具体的，在形成有所述第三屏蔽介质层111的结构上制备栅介质层112，在一示例中，形成的所述第三屏蔽介质层111具有平齐的上表面，且显露所述器件沟槽102的侧壁，所述栅介质层102连续的形成在所述器件沟槽102的侧壁及所述第三屏蔽介质层111的上表面，所述栅介质层112围成所述栅极沟槽，接着，在所述栅极沟槽中形成所述栅极层113，在一示例中，形成的所述栅介质层112的上表面与所述外延层101的上表面平齐，形成的所述栅极层113的上表面低于所述栅介质层112的上表面，低于所述外延层101的上表面。其中，可以采用热氧化工艺形成所述栅介质层112，所述栅介质层112的材料可以是氧化硅层或高介电常数介质层，但不局限于此，所述栅极层113的材料包括但不限于多晶硅。
如图1中的S6及图9所示，于所述器件沟槽102两侧的所述外延层101中形成第二掺杂类型的体区114，并于所述体区114中形成所述第一掺杂类型的源极115。
具体的，所述第二掺杂类型表示与所述第一掺杂类型相反的掺杂类型，如所述第一掺杂类型为N型，则所述第二掺杂类型为P型，如所述第一掺杂类型为P型，则所述第二掺杂类型为N型，在一示例中，在所述外延层101中进行离子注入以形成体区114，其中，所述体区114的掺杂类型与所述外延层101及所述衬底100的掺杂类型相反。
在一示例中，所述体区114的深度小于所述栅极沟槽的深度，也就是说，所述体区114的底部距所述外延层101底部的距离大于所述栅极沟槽的底部距所述外延层101底部的距离，所述体区114的底部与所述栅极沟槽的底部具有一高度差，也即所述体区底部与所述栅极层底部之间具有一高度差，以进一步提高所述栅极层113对所述屏蔽栅沟槽场效应晶体管的沟道控制能力。本实施例中，所述体区选择为P-掺杂的体区。
接着还在所述体区114中形成源极115，可以采用离子注入的方式在所述体区中进行离子注入以形成所述源极115，所述源极115的离子掺杂类型与所述外延层101及所述衬底100的掺杂类型相同，与所述体区114的掺杂类型相反，本示例中，选择为N+型掺杂的硅。
如图1中的S7及图10所示，至少于所述外延层101中形成与所述体区114及所述源极115均电连接的上金属结构118，以及于所述衬底100远离所述外延层101的一侧形成与所述衬底100电连接的下金属结构119。
作为示例，形成所述上金属结构118的方法包括如下步骤：
于所述栅极层113及所述外延层101上沉积隔离介质层116，刻蚀所述隔离介质层116 及所述外延层101以形成源极接触孔以及栅极接触孔，其中，所述源极接触孔的底部显露所述体区114，侧壁显露所述源极115，所述栅极接触孔的底部显露所述栅极层113；以及
于所述隔离介质层116上以及所述源极接触孔和所述栅极接触孔中沉积导电材料，以形成所述上金属结构118，实现所述源极115及所述栅极层的电性引出。
具体的，形成上金属结构118以形成引出电极，在一示例中，先形成所述隔离介质层116，所述隔离介质层的材料包括但不限于氧化硅层，可以是采用化学气相沉积工艺先沉积材料层，再通过干法刻蚀或湿法刻蚀进行回刻至目标深度的方式形成，其中，所述隔离介质层116覆盖所述栅极层113、所述栅极介质层112以及与所述栅极介质层相接触的所述源极115的上表面，可选地，基于光刻-刻蚀工艺形成所述源极接触孔及所述栅极接触孔(图中未示出)，所述源极接触孔贯穿所述隔离介质层116延伸至所述外延层101中，与所述源极115接触，在一示例中，进一步延伸至所述体区114中，源极接触孔的底部显露所述体区，在一示例中，所述源极接触孔的底部低于所述源极的底部，所述体区114可以通过所述源极115共同引出，此外，所述栅极接触孔贯穿所述隔离介质层116并延伸并显露所述栅极层113，接着沉积导电材料以形成所述上金属结构，从而可以将源极、栅极层113引出，其中，上金属结构118的材料包括但不限于钨或多晶硅。另外，所述衬底100的底部还制备下金属结构，以将衬底100电性引出，作为金属漏极，所述下金属结构119的材料包括但不限于钨或多晶硅。
作为示例，沉积所述导电材料之前还包括步骤：基于所述源极接触孔于所述体区114中形成掺杂接触区117，所述掺杂接触区117的掺杂类型与所述体区114的掺杂类型一致，所述掺杂接触区117与所述上金属结构118相接触。
具体的，所述三维存储器结构的制备方法中还包括制备掺杂接触区117的步骤，可以采用离子注入的工艺对所述体区114中进行离子注入，在一示例中，基于所述源极接触孔进行离子注入，所述掺杂接触区117形成在所述体区114裸露于所述源极接触孔的表面，所述掺杂接触区117的掺杂类型与所述体区114的掺杂类型一致，在一示例中，所述掺杂接触区117的掺杂浓度大于所述体区的掺杂浓度，在本实施例中，选择为P+型掺杂，以降低接触电阻。
作为示例，所述第一屏蔽栅层106通过版图布局与所述源极115相电连接。
作为示例，所述第二屏蔽栅层109通过版图布局与所述源极115及所述栅极层113中的任意一种相电连接。
具体的，所述第一屏蔽栅层106通过版图布局与所述源极115相电连接，所述第二屏蔽栅层109通过版图布局与所述源极115及所述栅极层113中的任意一种相电连接，从而可以实现所述第一屏蔽栅层106及所述第二屏蔽栅层109的屏蔽功能。
需要说明的，基于本发明的方案，在漂移区内引入深沟槽屏蔽栅，在阻断条件下，深沟槽屏蔽栅提供移动电荷补偿横向漂移区施主，器件纵向电场从传统沟槽MOSFET三角形分布优化成了近似梯形分布，大幅提供了器件击穿电压；相同额定电压器件，屏蔽栅沟槽MOSFET可提高漂移区掺杂浓度，实现较低特征导通电阻(Rdson.sp)，改善击穿电压和特征导通电阻的矛盾关系。基于本发明的第一屏蔽栅106以及第二屏蔽栅109的设计，所述外延层101的掺杂浓度可以做到传统屏蔽栅沟槽MOSFET结构外延层掺杂浓度的1.3-1.6倍，有利于器件特征导通电阻的降低，在第一屏蔽栅层106和栅极层113之间设置第二屏蔽栅层109，同时设置了第二屏蔽介质层110，器件在阻断条件下，第二屏蔽栅层与第二屏蔽介质层的结构提供更多移动电荷横向补偿漂移区施主或受主，优化了器件沟槽表面纵向电场分布，例如，解决了常规屏蔽栅沟槽MOSFET结构在器件击穿时沟槽表面纵向电场呈两个峰值的悬挂式分布，电场峰值之间电场下降严重问题，从而进一步改善了器件击穿电压和特征导通电阻的矛盾关系。
实施例二：
如图10所示，并参见图1-9，本发明还提供一种沟槽型场效应晶体管结构，其中，所述场效应晶体管结构优选采用本发明实施例一所述的场效应晶体管结构的制备方法制备得到，相关结构描述可参见实施例一所述，所述沟槽型场效应晶体管结构包括：
第一掺杂类型的衬底100；
所述第一掺杂类型的外延层101，所述外延层101形成于所述衬底100上，所述外延层101中形成有若干个器件沟槽102；
第一屏蔽介质层105，形成于所述器件沟槽102的底部及部分侧壁；
第一屏蔽栅层106，至少形成于所述第一屏蔽介质层105表面，且所述第一屏蔽介质层105的上表面低于所述第一屏蔽栅层106的上表面，所述第一屏蔽栅层106与所述第一屏蔽介质层105的上表面均低于所述外延层101的上表面；
第二屏蔽介质层110，形成于所述第一屏蔽栅层106上，至少覆盖所述第一屏蔽栅层106显露的表面；
第二屏蔽栅层109，形成于所述第二屏蔽介质层110上；
第三屏蔽介质层111，形成于所述第二屏蔽栅层109上，至少覆盖所述第二屏蔽栅层109显露的表面；
栅介质层112，形成于所述器件沟槽102的侧壁及所述第三屏蔽介质层11表面，所述栅介质层112的表面围成栅极沟槽；
栅极层113，填充于所述栅极沟槽中；
第二掺杂类型的体区114，形成于所述器件沟槽102两侧的所述外延层101中；
所述第一掺杂类型的源极115，形成于所述体区114中；
上金属结构118，至少形成于所述外延层101中，并于所述体区114及所述源极115均电连接；以及
下金属结构119，形成于所述衬底100远离所述外延层的一侧，并与所述衬底电连接。
作为示例，所述外延层101的掺杂浓度介于1E 16-9E 16cm -3之间。
具体的，所述外延层102的掺杂类型与所述衬底100的掺杂类型一致，在一示例中，所述外延层102的掺杂浓度低于所述衬底100的掺杂浓度。在一示例中，本发明结构使用30V-300V SGT MOSFET电压级，可选地，外延层的掺杂浓度介于1E 16-9E 16cm -3之间，可以是6E 16cm -3。
作为示例，所述第一屏蔽介质层105的厚度介于1000埃-9000埃。
作为示例，所述第三屏蔽介质层111的厚度介于2000埃-4000埃之间。
在一示例中，形成的所述第三屏蔽介质层111具有平齐的上表面，且显露所述器件沟槽102的侧壁，所述栅介质层102连续的形成在所述器件沟槽102的侧壁及所述第三屏蔽介质层111的上表面，所述栅介质层112围成一栅极沟槽，在所述栅极沟槽中形成有所述栅极层113，在一示例中，形成的所述栅介质层112的上表面与所述外延层101的上表面平齐，所述栅极层113的上表面低于所述栅介质层112的上表面，低于所述外延层101的上表面。其中，可以采用热氧化工艺形成所述栅介质层112，所述栅介质层112的材料可以是氧化硅层或高介电常数介质层，但不局限于此，所述栅极层113的材料包括但不限于多晶硅。
作为示例，所述第二屏蔽介质层包括形成于所述第一屏蔽栅层侧部的凹槽部，所述凹槽部基于所述第二屏蔽介质层远离所述第一屏蔽栅层的表面围成，其中，所述第二屏蔽栅层包括与所述凹槽部对应的凸部以及形成于所述凸部上并与所述凸部连接的体部。
具体的，在一示例中，形成一种包括所述凸部109a及所述体部109b的所述第二屏蔽栅层109，其中，所述第一屏蔽栅层106凸出于所述第一屏蔽介质层105，例如，在所述第一屏蔽删层106的两侧形成侧边凹槽107，此时，形成所述第二屏蔽介质材料层108时控制所述第二屏蔽介质材料层108之间还保留有预留空间，即形成于所述侧边凹槽107中的所述第二屏蔽材料层108之间还留有所述预留空间，从而使得在进行所述第二屏蔽栅层109的材料沉积时可以沉积到所述预留空间中，形成所述凸部109a，进行形成所述体部109b，在一可选示例中，所述凸部109a的高度介于2000埃-5000埃之间，从而有利于器件纵向电场的改善。
作为示例，所述第二屏蔽介质层110的厚度介于所述第一屏蔽介质层105的厚度的30％-70％之间。
具体的，在一示例中，还控制所述第二屏蔽介质层110的厚度介于所述第一屏蔽介质层105的厚度的30％-70％之间，其中，这里的厚度指的是自所述器件沟槽的侧壁至所述器件沟槽中心的距离，也即形成的所述第二屏蔽介质材料层108的厚度介于形成的所述第一屏蔽材料层103的厚度的30％-70％之间，如可以是35％、39.7％、40％、50％等，控制上述比例，从而可以基于其改善器件的击穿电压，从而可以有利于平衡击穿电压和器件击穿时电场分布，另外，在一示例中，设置所述第二屏蔽介质层110的厚度小于所述第一屏蔽介质层105的厚度的60％，从而有利于缓解器件内部电场分布的恶化。
作为示例，所述第二屏蔽栅层110的底部设置在所述器件沟槽深度102的30％-50％之间的位置。作为示例，所述器件沟槽102的深度介于1.2um-9um之间。
具体的，在一示例中，控制所述第二屏蔽栅层110的底部在所述器件沟槽102深度的30％-50％处，即所述第二屏蔽栅层110的底部到所述器件沟槽102的顶部的距离是所述器件沟槽102的深度(纵向长度)的30％-50％，如可以是40％、43％、45％，控制上述比例，从而可以基于其改善器件的击穿电压，从而可以有利于平衡击穿电压和器件击穿时电场分布，另外，在一示例中，设置所述第二屏蔽栅层110的底部设置在大于所述器件沟槽深度102的30％处，从而有利于缓解器件内部电场分布的恶化。
具体的，所述第二掺杂类型表示与所述第一掺杂类型相反的掺杂类型，如所述第一掺杂类型为N型，则所述第二掺杂类型为P型，如所述第一掺杂类型为P型，则所述第二掺杂类型为N型，在一示例中，所述体区114的掺杂类型与所述外延层101及所述衬底100的掺杂类型相反，在一示例中，所述体区114的深度小于所述栅极沟槽的深度，也就是说，所述体区114的底部距所述外延层101底部的距离大于所述栅极沟槽的底部距所述外延层101底部的距离，所述体区114的底部与所述栅极沟槽的底部具有一高度差，也即所述体区底部与所述栅极层底部之间具有一高度差，以进一步提高所述栅极层113对所述屏蔽栅沟槽场效应晶体管的沟道控制能力。本实施例中，所述体区选择为P-掺杂的体区。所述源极115的离子掺杂类型与所述外延层101及所述衬底100的掺杂类型相同，与所述体区114的掺杂类型相反，本示例中，选择为N+型掺杂的硅。
作为示例，所述三维存储器结构中还包括掺杂接触区117，所述掺杂接触区117形成在所述体区114裸露于所述源极接触孔的表面，所述掺杂接触区117的掺杂类型与所述体区114的掺杂类型一致，在一示例中，所述掺杂接触区117的掺杂浓度大于所述体区的掺杂浓度， 在本实施例中，选择为P+型掺杂，以降低接触电阻。
作为示例，所述第一屏蔽栅层106通过版图布局与所述源极115相电连接。
作为示例，所述第二屏蔽栅层109通过版图布局与所述源极115及所述栅极层113中的任意一种相电连接。
具体的，所述第一屏蔽栅层106通过版图布局与所述源极115相电连接，所述第二屏蔽栅层109通过版图布局与所述源极115及所述栅极层113中的任意一种相电连接，从而可以实现所述第一屏蔽栅层106及所述第二屏蔽栅层109的屏蔽功能。
对比例：
本发明提供一对比例，该对比例中，如图11所示，已N型器件为例，元胞结构包括：轻掺杂N-型外延层201，形成于重掺杂N++型硅衬底200上，金属漏极212，形成于重掺杂N++型硅衬底200下；深沟槽202形成于轻掺杂N-型外延层201中，深沟槽202侧壁长有屏蔽氧化层203，深沟槽202中填充有屏蔽多晶硅204和栅极多晶硅205；屏蔽多晶硅204和栅极多晶硅205之间有氧化层206隔离；P型体区207形成于轻掺杂N-型外延层201表面，源区208形成在P型体区207中；接触孔穿过氧化介质层209和源区208进入P型体区207；金属源极210设置在接触孔和氧化介质层209上；栅极多晶硅205通过版图布局在沟槽202末端引出(未画出)，屏蔽多晶硅204通过版图布局使其与源极208相连，源极208和P型体区207通过金属源极210共同引出，还设置有接触掺杂区211。另外，还给出采用本发明实施例一制备得到的沟槽型场效应晶体管的一个示例，所述衬底100选择为重掺杂N++型硅衬底，所述外延层101选择为轻掺杂N-型外延层，所述体区选择为P型掺杂，所述第一屏蔽介质层105、第二屏蔽介质层110、第三屏蔽介质层111以及隔离介质层116均选择为氧化硅，所述第一屏蔽栅层106、第二屏蔽栅层109以及栅极层113均选择为多晶硅，其中，第一屏蔽栅层106通过版图布局使其与源极115相连，第二屏蔽栅层109与源极115等电位。
其中，采用TCAD仿真工具sentaurus对图11所示的屏蔽栅沟槽MOSFET器件进行了仿真模拟，图12是图11所示的屏蔽栅沟槽MOSFET结构在阻断条件下击穿时沟槽表面纵向电场分布图，可见，图11所示屏蔽栅沟槽MOSFET结构，在阻断条件器件击穿时，器件沟槽表面纵向电场如图12所示：呈两个峰值(一个位于P型体区/N-型外延结，另一个位于深沟槽底部)的悬挂式分布，特别是在两个电场峰值之间电场下降严重，相同额定电压器件，常规屏蔽栅沟槽MOSFET无法充分提高漂移区掺杂浓度，降低特征导通电阻(Rdson.sp)，导致该结构仅能一定程度上改善了击穿电压和特征导通电阻的矛盾关系。同时，对上面给出的采用本发明实施例一的方案制备的沟槽型场效应晶体管利用TCAD仿真工具sentaurus进行 模拟，模拟结构中，轻掺杂N型外延层101浓度是相同额定电压图11所示屏蔽栅沟槽MOSFET结构轻掺杂N-型外延层201浓度的1.45倍，第二屏蔽栅层109底部设置在器件沟槽102深度43％处；第二屏蔽介质层110厚度设置为第一屏蔽介质层105厚度的40％；第二屏蔽栅层109与源极115等电位，其他参数与图11器件结构一致。图13显示模拟结构在阻断条件下击穿时沟槽表面纵向电场分布，电场呈3个峰值分布，在设置的第二屏蔽栅层109与第二屏蔽介质层110结构处形成了第三个峰值电场，解决了图11屏蔽栅沟槽MOSFET结构两个电场峰值之间电场下降严重问题。
另外，图14为使用TCAD仿真工具sentaurus模拟的图11所示的屏蔽栅沟槽MOSFET结构和本发明实施例一示例的屏蔽栅沟槽MOSFET结构在阻断条件下的I-V曲线，其中，模拟结构中，轻掺杂N型外延层101浓度是相同额定电压图11所示屏蔽栅沟槽MOSFET结构轻掺杂N-型外延层201浓度的1.45倍，第二屏蔽栅层109底部设置在器件沟槽102深度43％处；第二屏蔽介质层110厚度设置为第一屏蔽介质层105厚度的39.7％；第二屏蔽栅层109与源极115等电位，其他参数与图11器件结构一致。从图14可知图11所示屏蔽栅沟槽MOSFET结构器件击穿电压114V，本发明实施例一示例提出的屏蔽栅沟槽MOSFET结构击穿电压116V，两种模拟结构击穿电压相当；但本发明提出的屏蔽栅沟槽MOSFET结构轻掺杂N型外延层浓度是图11屏蔽栅沟槽MOSFET结构轻掺杂N-型外延层浓度的1.45倍，意味着本发明提出的屏蔽栅沟槽MOSFET结构器件特征导通电阻(Rdson.sp)性能更优越，从仿真模拟数据得出：本发明提出的蔽栅沟槽MOSFET结构特征导通电阻(Rdson.sp)较常规屏蔽栅沟槽MOSFET结构降低19％，进一步改善了器件击穿电压和特征导通电阻的矛盾关系。
此外，图15是仿真模拟的图11所示屏蔽栅沟槽MOSFET结构和本发明实施例一示例的屏蔽栅沟槽MOSFET结构的轻掺杂外延层归一化浓度与器件击穿电压变化趋势图；由图可知，本发明提出的屏蔽栅沟槽MOSFET结构最大击穿电压的轻掺杂外延层浓度是图11的屏蔽栅沟槽MOSFET结构最大击穿电压的轻掺杂外延层浓度的1.5倍；那么相同额定电压器件，本发明提出的结构器件轻掺杂外延层104浓度可设置为图11屏蔽栅沟槽MOSFET结构轻掺杂外延层浓度的1.3-1.6倍。图16仿真模拟的本发明提出的屏蔽栅沟槽MOSFET结构中第二屏蔽栅层底部深度和器件沟槽深度比例与器件击穿电压变化趋势图；由图可知，随着第二屏蔽栅层底部深度和器件沟槽深度比例增加，器件击穿电压先增加后减小，且第二屏蔽栅层底部深度和器件沟槽深度比例大于50％后，器件击穿电压急剧减小，综合考虑击穿电压和器件击穿时电场分布，第二屏蔽栅层底部位置设置在器件沟槽深度30％-50％处。图17是仿真模拟的本发明提出的屏蔽栅沟槽MOSFET结构中第二屏蔽介质层厚度和第一屏蔽介质层厚度 比例与器件击穿电压变化趋势图；由图可知，随着第二屏蔽介质层厚度和第一屏蔽介质层厚度比例增加，器件击穿电压先增加后减小，且第二屏蔽介质层厚度和第一屏蔽介质层厚度比例大于70％后，击穿电压急剧下降；综合考虑击穿电压和器件击穿时电场分布，第二屏蔽介质层厚度设置为第一屏蔽介质层厚度的30％-70％，另外，本领域技术人员可以理解的，图16及图17的曲线关系主要与器件击穿电压有关，器件击穿电压主要与外延层的浓度厚度、第一屏蔽氧化层的厚度等等有关，所有不同击穿电压产品曲线稍有差异，但最优设计范围基本相当，不同类型器件曲线关系稍有差异，差异较小，可以认为基于一致。还需要说明的，N型MOSFET工作在阻断模式下时，器件源极和栅极接地，漏极接高压；第二屏蔽栅层和栅极层等电位时对器件阻断特性影响效果与其和源极等电位影响效果相当。P型器件反之亦然。
综上所述，本发明提供一种沟槽型场效应晶体管结构及其制备方法，基于第一屏蔽栅层及第二屏蔽栅层的设置，可以提高漂移区(外延层)的掺杂浓度，并优化了器件沟槽表面纵向电场分布，可以解决现有技术中器件击穿时沟槽表面纵向电场呈两个峰值的悬挂式分布，电场峰值之间电场下降严重问题，从而进一步改善了器件击穿电压和特征导通电阻的矛盾关系。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (11)

  1. 一种沟槽型场效应晶体管结构的制备方法，其特征在于，所述制备方法包括如下步骤：
    提供第一掺杂类型的衬底，所述衬底包括相对的第一表面和第二表面；
    于所述衬底的第一表面上形成所述第一掺杂类型的外延层；
    于所述外延层中形成若干个器件沟槽；
    于所述器件沟槽的内壁形成第一屏蔽介质层；
    于所述第一屏蔽介质层表面形成第一屏蔽栅层，所述第一屏蔽栅层至少填充所述器件沟槽的底部，且所述第一屏蔽介质层的上表面低于所述第一屏蔽栅层的上表面，所述第一屏蔽栅层与所述第一屏蔽介质层的上表面均低于所述外延层的上表面；
    于所述第一屏蔽栅层上形成第二屏蔽介质层，所述第二屏蔽介质层至少覆盖所述第一屏蔽栅层显露的表面，并于所述第二屏蔽介质层上形成第二屏蔽栅层；
    于所述第二屏蔽栅层上形成第三屏蔽介质层，所述第三屏蔽介质层至少覆盖所述第二屏蔽栅层显露的表面；
    于所述器件沟槽的侧壁及所述第三屏蔽介质层表面形成栅介质层，以于所述器件沟槽中形成栅极沟槽，并在所述栅极沟槽中填充形成栅极层；
    于所述器件沟槽两侧的所述外延层中形成第二掺杂类型的体区，并于所述体区中形成所述第一掺杂类型的源极；以及
    至少于所述外延层中形成与所述体区及所述源极均电连接的上金属结构，以及于所述衬底的第二表面上形成与所述衬底电连接的下金属结构。
  2. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，形成所述第一屏蔽介质层及所述第一屏蔽栅层的方法包括如下步骤：
    于所述器件沟槽的内壁沉积第一屏蔽介质材料层，所述第一屏蔽介质材料层延伸至所述器件沟槽周围的所述外延层上；
    于所述第一屏蔽介质材料层表面沉积第一屏蔽栅材料层，所述第一屏蔽栅材料层填充满所述器件沟槽并延伸至所述器件沟槽周围的所述第一屏蔽介质材料层上；以及
    对所述第一屏蔽介质材料层及所述第一屏蔽栅材料层进行回刻，以得到所述第一屏蔽介质层及所述第一屏蔽栅层。
  3. 根据权利要求2所述的沟槽型场效应晶体管结构的制备方法，其特征在于，采用湿法刻蚀对所述第一屏蔽介质材料层进行回刻，使所述第一屏蔽栅层形成凸出于所述第一屏蔽介质层的凸出部分，所述凸出部分的侧部基于所述第一屏蔽介质材料层的回刻形成侧边凹槽， 以使所述第一屏蔽介质层的上表面低于所述第一屏蔽栅层的上表面。
  4. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，所述第二屏蔽介质层包括形成于所述第一屏蔽栅层侧部的凹槽部，所述凹槽部基于所述第二屏蔽介质层远离所述第一屏蔽栅层的表面围成，其中，所述第二屏蔽栅层包括与所述凹槽部对应的凸部以及形成于所述凸部上并与所述凸部连接的体部。
  5. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，形成所述第二屏蔽介质层及所述第二屏蔽栅层的方法包括如下步骤：
    于形成有所述第一屏蔽介质层及所述第一屏蔽栅层的结构上形成第二屏蔽介质材料层，所述第二屏蔽介质材料层形成于所述第一屏蔽介质层的上表面、所述第一屏蔽栅层上表面并延伸至所述器件沟槽的侧壁及所述器件沟槽周围的所述外延层表面；
    于所述第二屏蔽介质材料层表面形成所述第二屏蔽栅层；以及
    对所述第二屏蔽介质材料层进行回刻，以形成所述第二屏蔽介质层。
  6. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，所述栅极介质层形成于所述第三屏蔽介质层表面并延伸至所述器件沟槽的内壁上，所述栅极层的上表面低于所述外延层的上表面，形成所述栅极层的步骤包括：于所述栅极沟槽中沉积栅极材料层，对所述栅极材料层进行回刻以形成所述栅极层。
  7. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，形成所述上金属结构的方法包括如下步骤：
    于所述栅极层及所述外延层上沉积隔离介质层，刻蚀所述隔离介质层及所述外延层以形成源极接触孔以及栅极接触孔，其中，所述源极接触孔的底部显露所述体区，侧壁显露所述源极，所述栅极接触孔的底部显露所述栅极层；以及
    于所述隔离介质层上以及所述源极接触孔和所述栅极接触孔中沉积导电材料，以形成所述上金属结构，实现所述源极及所述栅极层的电性引出。
  8. 根据权利要求7所述的沟槽型场效应晶体管结构的制备方法，其特征在于，沉积所述导电材料之前还包括步骤：基于所述源极接触孔于所述体区中形成掺杂接触区，所述掺杂接触区的掺杂类型与所述体区的掺杂类型一致，所述掺杂接触区与所述上金属结构相接触。
  9. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，所述第一屏蔽栅层通过版图布局与所述源极相电连接；所述第二屏蔽栅层通过版图布局与所述源极及所述栅极层中的任意一种相电连接。
  10. 一种沟槽型场效应晶体管结构，其特征在于，所述沟槽型场效应晶体管结构包括：
    衬底，具有第一掺杂类型，所述衬底具有相对的第一表面和第二表面；
    外延层，具有所述第一掺杂类型，，所述外延层形成于所述衬底的第一表面上，所述外延层中形成有若干个器件沟槽；
    第一屏蔽介质层，形成于所述器件沟槽的底部及部分侧壁；
    第一屏蔽栅层，形成于所述第一屏蔽介质层表面，至少填充所述器件沟槽的底部，且所述第一屏蔽介质层的上表面低于所述第一屏蔽栅层的上表面，所述第一屏蔽栅层与所述第一屏蔽介质层的上表面均低于所述外延层的上表面；
    第二屏蔽介质层，形成于所述第一屏蔽栅层上，至少覆盖所述第一屏蔽栅层显露的表面；
    第二屏蔽栅层，形成于所述第二屏蔽介质层上；
    第三屏蔽介质层，形成于所述第二屏蔽栅层上，至少覆盖所述第二屏蔽栅层显露的表面；
    栅介质层，形成于所述器件沟槽的侧壁及所述第三屏蔽介质层表面，所述栅介质层的表面围成栅极沟槽；
    栅极层，填充于所述栅极沟槽中；
    体区，具有第二掺杂类型，所述体区形成于所述器件沟槽两侧的所述外延层中；
    源极，具有所述第一掺杂类型，所述源极形成于所述体区中；
    上金属结构，至少形成于所述外延层中，并与所述体区及所述源极均电连接；以及
    下金属结构，形成于所述衬底的第二表面，并与所述衬底电连接。
  11. 根据权利要求10所述的沟槽型场效应晶体管结构，其特征在于，所述第二屏蔽介质层包括形成于所述第一屏蔽栅层侧部的凹槽部，所述凹槽部基于所述第二屏蔽介质层远离所述第一屏蔽栅层的表面围成，其中，所述第二屏蔽栅层包括与所述凹槽部对应的凸部以及形成于所述凸部上并与所述凸部连接的体部。
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