WO2021114437A1 - 沟槽型场效应晶体管结构及其制备方法 - Google Patents

沟槽型场效应晶体管结构及其制备方法 Download PDF

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WO2021114437A1
WO2021114437A1 PCT/CN2019/130508 CN2019130508W WO2021114437A1 WO 2021114437 A1 WO2021114437 A1 WO 2021114437A1 CN 2019130508 W CN2019130508 W CN 2019130508W WO 2021114437 A1 WO2021114437 A1 WO 2021114437A1
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trench
gate
lead
region
body region
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PCT/CN2019/130508
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English (en)
French (fr)
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陈茜
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华润微电子（重庆）有限公司
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Priority to JP2021559613A priority Critical patent/JP7368493B2/ja
Priority to US17/600,113 priority patent/US11652170B2/en
Priority to KR1020217026145A priority patent/KR102548225B1/ko
Priority to EP19955525.1A priority patent/EP3933895B1/en
Publication of WO2021114437A1 publication Critical patent/WO2021114437A1/zh

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Definitions

  • the invention relates to the technical field of integrated circuit design and manufacturing, in particular to a trench field effect transistor structure and a preparation method thereof.
  • Trench devices such as square layout trench MOS as an important power device have a wide range of applications. They have low on-resistance, low on-resistance, and faster switching speeds. And good resistance to avalanche impact. The requirements of energy saving, emission reduction and market competition can further reduce the on-resistance of the device while ensuring that other performance parameters of the device remain unchanged. As we all know, reducing the lateral spacing of trench-type device cells and increasing the cell density is a very effective way to reduce the source-drain on-resistance. However, it is limited by the capabilities of the photolithography and etching machines. The lateral spacing of cells cannot be continuously reduced.
  • the Square layout is The closed-loop structure has a higher channel density than strip layout (strip layout) devices, and a lower Ron (on resistance) than strip layout devices.
  • Ron on resistance
  • the traditional square layout requires sufficient area to form contact holes, so that the closed-loop structure formed independent body region (body region) domain and source The source is electrically drawn. As the size of the cell decreases, it is no longer sufficient to form a contact hole in the form of an opening to connect the body region and the source, and it is difficult to achieve the equipotential extraction of the two.
  • the purpose of the present invention is to provide a trench field-effect transistor structure and manufacturing method, which is used to solve the problem of the difficulty of continuing to reduce the cell size and the difficulty of effective body region and source in the prior art. Leads to other questions.
  • the present invention provides a method for fabricating a trench field effect transistor structure.
  • the fabricating method includes the following steps:
  • a plurality of first trenches arranged at parallel intervals and a plurality of second grooves arranged at parallel intervals are formed in the epitaxial layer, wherein the first grooves and the second grooves are arranged to intersect each other to A plurality of injection regions are enclosed based on the adjacent first trench and the second trench;
  • a first gate dielectric layer is formed on the inner wall of the first trench, a first gate structure is formed on the first gate dielectric layer, the first gate structure is filled in the first trench, and Forming a second gate dielectric layer on the inner wall of the second trench, forming a second gate structure on the second gate dielectric layer, and filling the second gate structure in the second trench;
  • a source implantation mask is formed on the epitaxial layer, the source implantation mask includes a plurality of spaced implant mask units, and the implantation mask unit covers the boundary between the first trench and the second trench Locating and extending to cover the injection area around the junction, so as to form at least one shielding area on the body area;
  • the shielding region constitutes a body region lead-out region
  • a source electrode structure that is in contact with the upper surface of the source electrode and the upper surface of the body region lead-out region is formed on the epitaxial layer to electrically lead the source electrode and the body region.
  • the present invention also provides a trench field effect transistor structure, which is preferably prepared by the method for preparing the trench field effect transistor structure of the present invention. Of course, it can also be prepared by other methods.
  • the trench field effect transistor structure includes :
  • the groove and the second groove are intersected and arranged to form a plurality of junctions, and the adjacent first groove and the second groove surround a plurality of injection regions;
  • a first gate dielectric layer and a second gate dielectric layer are formed on the inner walls of the first trench and the second trench, respectively;
  • a first gate and a second gate are respectively formed on the surfaces of the first gate dielectric layer and the second gate dielectric layer, and the first gate is filled in the first trench, and the first gate is Two gates are filled in the second trench;
  • a body region formed in the implantation region is adjacent to the first trench and the second trench, the body region includes at least one body region lead-out region, and the body region leads The area is adjacent to the junction around the body area;
  • a source electrode formed in the body region the source electrode is adjacent to the body region lead-out region, and the upper surface of the source electrode is flush with the upper surface of the body region lead-out region;
  • the source electrode structure is in contact with the upper surface of the source electrode and the upper surface of the body region lead-out region, so as to electrically lead the source electrode and the body region.
  • source self-aligned implantation is performed by designing a source injection mask, forming a body lead-out area at the same time as the source, and directly connecting the source and The body region is connected.
  • the present invention adopts self-alignment technology to continue to reduce the cell size, without the need to set source contact holes to draw out the source and body regions with equipotential electrical potential, aiming at the square trench field effect.
  • the closed-loop structure of the transistor solves the problem of the shrinking of the cell size and the connection of the body region from the process and layout, so as to avoid the problem of device breakdown in advance.
  • Fig. 1 shows a process flow diagram of the preparation of a trench field effect transistor of the present invention.
  • FIG. 2 is a schematic diagram of the structure of the epitaxial layer formed in the preparation of the trench field effect transistor of the present invention.
  • FIG. 3 is a schematic top view of the formation of the first trench and the second trench during the preparation of the trench field effect transistor of the present invention.
  • Fig. 4 is a schematic cross-sectional view of position A-B in Fig. 3.
  • FIG. 5 is a diagram showing the formation of the first gate dielectric layer and the first gate structure in the preparation of the trench field effect transistor of the present invention.
  • FIG. 6 is a schematic diagram of the formation of a body region in the preparation of a trench field effect transistor of the present invention.
  • FIG. 7 is a schematic top view showing the formation of a source implantation mask in the preparation of a trench field effect transistor of the present invention.
  • Fig. 8 is a schematic cross-sectional view of position A-B in Fig. 7.
  • Fig. 9 is a schematic cross-sectional view of the position C-D in Fig. 7.
  • FIG. 10 is a schematic cross-sectional view showing the positions A-B of the source electrode structure formed by the trench field effect transistor of the present invention.
  • FIG. 11 is a schematic cross-sectional view of the C-D position of the source electrode structure formed by the trench field effect transistor of the present invention.
  • FIG. 12 is a schematic cross-sectional view showing the positions A-B of the lead-out gate structure formed by the trench field effect transistor of the present invention.
  • FIG. 13 is a schematic cross-sectional view showing the positions A-B of the lead-out gate structure formed by the trench field effect transistor of the present invention.
  • FIG. 14 shows a top view of a trench field effect transistor of a comparative example of the present invention.
  • Fig. 15 is a schematic cross-sectional view of the position M-N in Fig. 14.
  • the present invention provides a method for manufacturing a trench field effect transistor structure, which includes the following steps:
  • a plurality of first trenches arranged at parallel intervals and a plurality of second grooves arranged at parallel intervals are formed in the epitaxial layer, wherein the first grooves and the second grooves are arranged to intersect each other to A plurality of injection regions are enclosed based on the adjacent first trench and the second trench;
  • a first gate dielectric layer is formed on the inner wall of the first trench, a first gate structure is formed on the first gate dielectric layer, the first gate structure is filled in the first trench, and Forming a second gate dielectric layer on the inner wall of the second trench, forming a second gate structure on the second gate dielectric layer, and filling the second gate structure in the second trench;
  • a source implantation mask is formed on the epitaxial layer, the source implantation mask includes a plurality of spaced implant mask units, and the implantation mask unit covers the boundary between the first trench and the second trench Locating and extending to cover the injection area around the junction, so as to form at least one shielding area on the body area;
  • the shielding region constitutes a body region lead-out region, and the upper surface of the source electrode and the body region lead out The upper surface of the zone is flush;
  • a source electrode structure that is in contact with the upper surface of the source electrode and the upper surface of the body region lead-out region is formed on the epitaxial layer to electrically lead the source electrode and the body region.
  • a semiconductor substrate 100 is provided, and an epitaxial layer 101 is formed on the semiconductor substrate 100.
  • the semiconductor substrate 100 may be a substrate of a first doping type, where the first doping type (ie, the first conductivity type) may be P-type doping or N-type doping.
  • the semiconductor substrate 100 may be formed by implanting ions of the first doping type (P-type or N-type) into the intrinsic semiconductor substrate using an ion implantation process.
  • the specific type is set according to actual device requirements.
  • an N-type doped substrate is selected.
  • it may be a heavily doped substrate, for example, the semiconductor substrate 100 may be doped with ions of the first doping type.
  • the concentration is greater than or equal to 1 ⁇ 10 19 /cm 3 .
  • the semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc.
  • the semiconductor substrate 100 is selected as an N ++ type doped silicon substrate. , Such as 0.001-0.003ohm*cm.
  • the first doping type and the second doping type (ie, the second conductivity type) mentioned later are opposite doping (conductivity) types, and when the first doping type (first conductivity type) semiconductor is When the N-type semiconductor and the second doping type (second conductivity type) semiconductor are P-type semiconductors, the trench MOSFET device of the present invention is an N-type device; conversely, the trench MOSFET device of the present invention is a P-type device.
  • the doping type of the epitaxial layer 101 is consistent with the doping type of the semiconductor substrate 100.
  • the doping concentration of the epitaxial layer 101 is lower than that of the semiconductor substrate.
  • the doping concentration of the substrate 100 wherein an epitaxial process may be used to form an intrinsic epitaxial layer on the upper surface of the semiconductor substrate 100 of the first doping type, and then an intrinsic epitaxial layer may be formed on the upper surface of the semiconductor substrate 100 through an ion implantation process. Ions of the first doping type are implanted into the epitaxial layer to form the epitaxial layer 101 of the first doping type; in another example, an epitaxial process can also be used to directly apply ions to the first doping type.
  • the epitaxial layer 101 of the first doping type is epitaxially formed on the upper surface of the semiconductor substrate 100.
  • the epitaxial layer 101 is selected as an N-type monocrystalline silicon epitaxial layer.
  • a plurality of first trenches 102 arranged in parallel and a plurality of second grooves 103 arranged in parallel are formed in the epitaxial layer 101, wherein, The first trench 102 and the second trench 103 are arranged to intersect each other to form a plurality of injection regions 104 based on the adjacent first trench 102 and the second trench 103.
  • the first trench 102 and the second trench 103 may be realized by a photolithography etching process.
  • Figures 3 and 4 show a specific alternative example of the present invention.
  • Figure 4 shows a cross-sectional view of the position AB in Figure 3.
  • the figure only illustrates the relevant structures and their positional relationships. The number of structures should not be excessively limited.
  • the first trench 102 and the second trench 103 are perpendicular to each other, the shape of the injection region 104 formed is a square, two adjacent first trenches 102 and two adjacent first trenches 102
  • the second trench 103 encloses the implanted region 104 with a quadrilateral structure to form a square layout trench MOS, so that the first trench 102 and the implanted region 104 can be formed in a square layout trench MOS.
  • the second trench 103 is arranged to form a gate to prepare a device structure, increase the channel density of the device, and reduce the on-resistance of the device.
  • the spacing between the first trenches 102 is equal to
  • the distances between the second trenches 103 are equal, so that several square injection regions 104 of equal size can be obtained.
  • the shape of the injection regions 104 can also be rectangular or other based on the first trench 102.
  • the shape obtained with the second groove 103 is not limited to this, and can be set according to actual requirements.
  • a first gate dielectric layer 105 is formed on the inner wall of the first trench 102, and a first gate structure 106 is formed on the first gate dielectric layer 105.
  • the first gate structure 106 is filled in the first trench 102, and a second gate dielectric layer (not shown in the figure) is formed on the inner wall of the second trench 103.
  • a second gate structure (not shown in the figure) is formed thereon, and the second gate structure is filled in the second trench 103;
  • the continuous first gate dielectric layer 105 is formed on the bottom and sidewalls of the first trench 102, and the upper surface of the first gate dielectric layer 105 is connected to the epitaxial layer 101
  • the upper surface of the first trench 102 is flush, and the formation process may be to form the continuous first gate dielectric on the bottom and sidewalls of the first trench 102 and the epitaxial layer 101 around the first trench 102 Material layer, and remove the first gate dielectric material layer above the epitaxial layer 101 to obtain the first gate dielectric layer 105 on the bottom and sidewalls of the first trench 102.
  • the first gate dielectric material layer on the epitaxial layer 101 is first reserved for subsequent processes.
  • the first gate dielectric material layer is used as the first gate dielectric layer 105, where thermal oxidation or The first gate dielectric layer 105 is formed by a chemical vapor deposition process. In the same way, the formation process and structure of the second gate dielectric layer and the first gate dielectric layer 105 are similar, and will not be repeated here. In addition, in an example, after the first trench 102 and the second trench 103 are formed, the first gate dielectric layer 105 and the second gate dielectric layer are formed based on the same process.
  • the method before forming the first gate dielectric layer 105 and the second gate dielectric layer, the method further includes the step of forming a sacrificial oxide on the side and bottom surfaces of the first trench 102 and the second trench 103 Layer and remove the sacrificial oxide layer to repair the inner wall of the first trench 102 and the inner wall of the second trench 103 based on the sacrificial oxide layer, repair the damage caused by the etching process, optionally
  • the sacrificial layer may be formed by a thermal oxidation process. In one example, the sacrificial oxide layer may be removed by a wet etching process.
  • the surface of the first gate dielectric layer 105 formed on the inner wall of the first trench 102 forms a gate groove, and the first gate structure 106 is filled in the gate groove, wherein,
  • the first gate structure 106 may be used as a gate of a device, and its material includes but is not limited to polysilicon.
  • the first gate structure 106 is lower than the surface of the epitaxial layer 101, and the gate trench There is also a space for forming an insulating layer on the upper surface of the first gate structure 106 to finally form a field-effect trench transistor structure.
  • the gate is used, and it needs to be etched to obtain the gate of the device in the follow-up process to facilitate the protection of the gate in the subsequent process.
  • the formation process and structure of the second gate structure are similar to those of the first gate structure 106.
  • the first gate structure 106 and the second gate structure are formed based on the same process.
  • ion implantation is performed on the epitaxial layer 101 to form a body region 107 in the implanted region 104.
  • the body region 107 is located between adjacent trenches.
  • the body region 107 is adjacent to the first trench 102 and the second trench 103.
  • the doping type of the body region 107 is the same as that of the epitaxial layer 101 and the semiconductor substrate.
  • the doping type of 100 is opposite, and the body region 107 has the second doping type.
  • the body region 107 is selected to be P-type lightly doped.
  • the first gate dielectric layer 105 may also be formed on the epitaxial layer that needs to be implanted to form the body region 107.
  • the first gate structure 106 is formed, it is deposited The material layer is also formed above the epitaxial layer and formed on the surface of the corresponding part of the first gate dielectric layer 105.
  • the top part of the epitaxial layer can be removed for use
  • the material layer of the first gate structure 106 is formed and the corresponding part of the first gate dielectric layer 105 is exposed.
  • ion implantation is performed.
  • part of the first gate dielectric layer can protect the epitaxial layer during ion implantation.
  • the first gate structure 106 and the second gate structure need to be further processed. Etch to form the device gate.
  • the lower surface of the body region 107 is higher than the bottoms of the first trench 102 and the second trench 103, and the bottom of the body region 107 is between the bottoms of the two types of trenches. It has a height difference.
  • it further includes a step of performing high-temperature annealing after ion implantation to form the body region 107.
  • the threshold voltage, breakdown voltage, etc. of the device may be used. The performance parameters need to adjust the injection dosage.
  • a source implantation mask 108 is formed on the epitaxial layer 101, and the source implantation mask 108 includes a plurality of implantation masks Unit 108a, and the adjacent injection mask units 108a have a distance between them, and the injection mask unit 108a covers the junction of the first trench 102 and the second trench 103 and extends to cover the junction
  • the surrounding injection region 104 forms at least one shielding region in the body region 107.
  • the injection mask unit 108a extends to cover the four adjacent injection regions 104 around it, wherein ,
  • the shielding region is the part of the body region 107 that is shielded by the implantation mask unit 108a, so that under the shielding of the source implantation mask, the body region of this part of the region does not undergo ion implantation, It is still part of the body region, where the feature size of the source implant mask can be relatively large, which is beneficial to the implementation of the process.
  • the feature size (CD) of the source implant mask 108 It is between 0.3-0.5 microns, which can be 0.35 microns, 0.4 microns or 0.45 microns. In addition, it can be achieved with an I-line machine.
  • ion implantation is performed on the epitaxial layer 101 based on the source implantation mask 108 to form a source 109 in the body region 107, the The shielding area constitutes the body lead-out area 110, so that the upper surface of the source electrode 109 is flush with the upper surface of the body lead-out area 109.
  • the upper surface of the source electrode 109 refers to the opposite body area 107.
  • the upper surface after implantation that is, the upper surface of the epitaxial layer 101, the upper surface of the body lead-out region 110 at this time refers to the upper surface where the source implantation mask 108 has not been implanted.
  • the present invention performs ion implantation of the source 109 under the cover of the source implantation mask 108 to form the source 109
  • the lead-out area of the body region 107 is formed, that is, the body lead-out region 110 is defined at the same time, so that the source 109 and the body region 107 are electrically connected without preparing the source 109 contact hole. It is concluded that in the traditional device structure, the distance between the source contact hole and the device trench needs to be strictly controlled. As the device feature size (pitch) decreases, different source contact holes and device trenches need to be strictly controlled.
  • the asymmetry of the overlap between them will bring about the problem of VT (threshold voltage) or ID (drain leakage).
  • the self-aligned process of the present invention does not have this problem, as long as the source electrode structure (metal) is active
  • the area contact is good, the overlap between the device trench and the source electrode is symmetrical.
  • the upper surface of the source electrode 109 and the body area 107 are flush, so that the source electrode 109 and the source electrode 109 can be flush with each other.
  • the equipotential electrical extraction of the body region 107 is beneficial to prevent the device from premature breakdown and to prevent floating in the body region (the body region is not connected to the source equivalent potential, which is likely to produce a potential difference during operation, which will cause ID In the case of abnormal), the closed-loop structure is likely to accumulate charge during the working process, which will cause breakdown.
  • the above-mentioned solution of the present invention can continue to reduce the cell size, further reduce the pitch size to less than 0.9um, and further improve the trench of the device. Density, reduce on-resistance, reduce device consumption, and improve switching response speed.
  • the source 109 and body region 107 can be drawn out of the same potential without making contact holes, and the device will not In the case of premature breakdown, stable device electrical properties are obtained, and it is also easy to realize and mass produce in process manufacturing.
  • the injection mask unit 108a covers the junction of the first trench 102 and the second trench 103 and extends to cover the four injection regions 104 around the junction, so that Each of the body regions 107 forms four body region lead-out regions 110, that is, the part of the body region 107 shielded by the injection mask unit 108a constitutes the body region lead-out region 110.
  • the four body region lead-out regions 110 are spaced apart and are located at the four corners of the injection region 104, respectively, and are formed around the source electrode 109.
  • the four body regions 110 are formed around the source electrode 109.
  • the body region lead-out regions 110 are symmetrically distributed in the body region 107, thereby helping to improve electrical uniformity.
  • the first trench 102 and the second trench 103 are perpendicular to each other, and the shape of the injection region 104 formed includes a square, wherein the shape of the injection mask unit 108a includes a square, and The intersection area of each of the injection regions 104 intersected by the injection mask unit 108a is the same, the shape of the injection region 104 is selected to form a square, and the injection mask unit 108a is also selected to be a square, thereby forming a square.
  • the body region lead-out region 110 is also square, and is symmetrically distributed in the body region 107 to obtain the source electrode 109 with a symmetrical structure, which is beneficial to improve the electrical uniformity.
  • the first gate structure 106, the second gate structure, the first gate dielectric layer 105, and the second gate dielectric layer formed in the foregoing steps The upper surface is flush, where the first gate dielectric layer 105 and the second gate dielectric layer may only be formed in the first trench 102 and the second trench 103, and It may be that the first gate dielectric layer 105 and the second gate dielectric layer are formed between the first trench 102 and the second trench 103 and are also extended on the surface of the epitaxial layer 101, among them:
  • This example further includes the steps of forming the source electrode 109 after etching the first gate structure 106 to obtain a first gate electrode 111, and forming a first insulating layer 112 on the first gate electrode 111, The first insulating layer 112 is filled in the first trench 102.
  • the second gate structure is etched back to obtain a second gate, and a second insulating layer is formed on the second gate.
  • the second insulating layer is filled in the second trench 103, preferably, the first insulating layer 112, the second insulating layer, the body region 107 and the source electrode 109 are The surfaces are flush, and the source electrode structure 114 is also extended and formed on the upper surfaces of the first insulating layer 112 and the second insulating layer.
  • the first gate 111 is formed And the upper surface of the second gate electrode 109 is higher than the lower surface of the source electrode 109.
  • a high-density plasma process HDP may be used to deposit a high-density plasma oxide layer to form a first insulating material layer and CMP is performed on the first insulating material layer and the second insulating material layer, that is, CMP is performed on the deposited high-density plasma oxide layer to obtain the first insulating layer 112 and the second insulating material layer.
  • HDP high-density plasma process
  • the insulating layer in an example, the heights of the first insulating material layer and the second insulating material layer are higher than the upper surface of the epitaxial layer 101, that is, protruding from the first trench 102 and the In the second trench 103, CMP is performed on the first insulating material layer and the second insulating material layer to obtain the first insulating layer 112 and the second insulating layer, so that the quality of the formed insulating layer can be improved
  • the etch-back depth of the first gate structure 106 and the second gate structure is between 2000A-3000A, which can be understood as the first gate 111 and the second gate
  • the distance between the upper surface of the gate and the upper surface of the epitaxial layer 101 is between 2000A and 3000A, which can be 2500A in this example.
  • the first insulating material layer and the second insulating material layer are deposited The thickness of is between 3000A-4000A. In this example, corresponding to the 2500A etched away, the deposited HDP oxide layer can
  • the method further includes the step of: at least on the upper surface of the source electrode 109 and the body lead-out region 110
  • a metal silicide layer (silicide) on the source 109 is formed on the surface of the surface.
  • it may be Ti silicide, but it is not limited to this.
  • the source electrode structure 114 is formed on the source 109.
  • the surface of the silicide layer, wherein the formation process of the metal silicide may be at least forming metal titanium on the upper surface of the body region 107 and the source electrode 109, and then performing RTP (Rapid Thermal Processing), To form the metal silicide layer to reduce contact resistance.
  • RTP Rapid Thermal Processing
  • a source electrode structure 114 that is in contact with the upper surface of the source electrode 109 and the upper surface of the body lead-out region 110 is formed on the epitaxial layer 101,
  • the material of the source electrode structure 114 may be aluminum but is not limited thereto.
  • the method for preparing the trench field effect transistor structure further includes the step of preparing a lead-out gate structure, wherein the epitaxial layer 101 defines a device region B and a terminal region A, in an example
  • the first trench 102 and the second trench 103 are formed in the device region B, and the first trench 102 and the second trench 103 are formed in the terminal region at the same time.
  • a lead-out gate trench 200 is prepared in A, and a lead-out gate dielectric layer 201 is formed on the inner wall of the lead-out gate trench 200, and a lead-out gate 202 is formed on the surface of the lead-out gate dielectric layer 201, and on the terminal area A
  • An extraction gate electrode structure 203 electrically connected to the extraction gate 202 is also formed, wherein the extraction gate dielectric layer 201, the first gate dielectric layer 105 and the second gate dielectric layer are formed based on the same process, The extraction gate 202 is formed based on the same process as the first gate structure 106 and the second gate structure shown.
  • the extraction gate 202 in the extraction gate trench 200 is retained, so that when the extraction gate electrode structure is subsequently formed, it is electrically connected to the extraction gate electrode structure for electrical operation. Sexual elicitation.
  • the first gate 111 and the second gate may be led out to a gate pad through a trench on the periphery.
  • the first gate 111 and the second gate The second gate pulls out the first trench and the second trench to the edge of the die, and then uses a large trench to string all the trenches at the edge of the die into the gate pad.
  • the first gate and the second gate are electrically drawn through the lead-out gate structure of the terminal region A.
  • the extraction gate electrode structure 203 and the source electrode structure 114 are prepared based on the same process, for example, a monolithic metal material layer may be formed, and then etching may be performed, for example, a photomask may be used for etching. Etching. The source electrode structure 114 and the extraction gate electrode structure 203 are etched apart to insulate the two.
  • forming the extraction gate 202 further includes preparing the extraction gate The step of the metal silicide layer 204, and the extraction gate electrode structure 203 is formed on the surface of the metal silicide layer 204 on the extraction gate to reduce the contact resistance.
  • the extraction gate 202 The upper surface of the source electrode 109 is flush with the upper surface of the source electrode 109, and the extraction gate electrode structure 204 is insulated from the source electrode structure 114, and both are prepared based on the same process.
  • the present invention also provides a trench field effect transistor structure.
  • the field effect transistor structure preferably adopts the trench field effect transistor structure of the first embodiment of the present invention.
  • the trench field effect transistor structure includes: a semiconductor substrate 100, an epitaxial layer 101, a first trench 102 formed in the epitaxial layer 101, and a first trench 102 formed in the epitaxial layer 101.
  • the semiconductor substrate 100 may be a substrate of the first doping type.
  • an N-type doped substrate is selected.
  • it may be a heavily doped substrate.
  • the concentration of the first doping type ions doped in the semiconductor substrate 100 is greater than or equal to 1 ⁇ 10 19 /cm 3 .
  • the semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc.
  • the semiconductor substrate 100 is selected as an N ++ type doped silicon substrate. , Such as 0.001-0.003ohm*cm.
  • the doping type of the epitaxial layer 101 is consistent with the doping type of the semiconductor substrate 100.
  • the doping concentration of the epitaxial layer 101 is lower than that of the semiconductor substrate.
  • the epitaxial layer 101 is selected as an N-type monocrystalline silicon epitaxial layer.
  • a plurality of first trenches 102 arranged in parallel and spaced apart and a plurality of second trenches 103 arranged in parallel and spaced apart are formed in the epitaxial layer 101, wherein, the first groove 102 and the first groove 102 are arranged in parallel and spaced apart.
  • the two trenches 103 intersect to form a plurality of junctions, and the adjacent first trench 102 and the second trench 103 enclose a plurality of injection regions 104.
  • the first trench 102 and the second trench 103 are perpendicular to each other, the shape of the injection region 104 formed is a square, two adjacent first trenches 102 and two adjacent second trenches 103
  • the implantation area 104 with a quadrilateral structure is enclosed to form a square layout trench MOS (square layout trench MOS), so that the first trench 102 and the second trench 103
  • the distance between the first trench 102 and the second trench 102 is the same as that of the second trench 102.
  • the gate is arranged to prepare the device structure, increase the channel density of the device, and reduce the on-resistance of the device.
  • the spacing between 103 is equal, so that several square injection regions 104 of equal size can be obtained.
  • the shape of the injection region 104 can also be rectangular or other based on the first trench 102 and the second trench 103. The shape obtained is not limited to this, and can be set according to actual needs.
  • the first gate dielectric layer 105 is continuously formed on the bottom and sidewalls of the first trench 102, and the upper surface of the first gate dielectric layer 105 is flush with the upper surface of the epitaxial layer 101, and The first gate dielectric layer 105 may be continuously formed on the bottom and sidewalls of the first trench 102 and the surface of the epitaxial layer 101 around the first trench 102.
  • the structure of the second gate dielectric layer is similar to that of the first gate dielectric layer 105, which will not be repeated here.
  • the first gate 111 is formed on the surface of the first gate dielectric layer 105, and the first gate 111 is filled in the first trench 102, and the upper surface of the first gate 111 is low
  • the material includes but is not limited to polysilicon.
  • the distance between the upper surface of the first gate 111 and the upper surface of the epitaxial layer 101 is between 2000A and 3000A. In this example, it may be 2500A.
  • the structure of the second gate is similar to that of the first gate 111, which will not be repeated here.
  • the trench field effect transistor structure further includes a first insulating layer 112 formed on the first gate 111 and filled in the first trench 102, and a first insulating layer 112 formed on the second gate.
  • the second insulating dielectric layer above and filling in the second trench, and the source electrode structure 114 is also extended and formed on the upper surfaces of the first insulating layer 112 and the second insulating layer, wherein,
  • the materials of the first insulating layer and the second insulating layer include but are not limited to silicon oxide.
  • the body region 107 is formed in the injection region 104, the body region 107 is adjacent to the first trench 102 and the second trench 103, and the body region 107 includes at least one body region lead Region 110, the body region lead-out region 110 is adjacent to the junction immediately around the body region 107; in an example, the doping type of the body region 107 is the same as that of the epitaxial layer 101 and the The doping type of the semiconductor substrate 100 is opposite, and the body region 107 has the second doping type. In this example, the body region 107 is selected to be P-type lightly doped. In addition, the lower surface of the body region 107 is higher than the bottoms of the first trench 102 and the second trench 103, and there is a height difference between the bottom of the body region 107 and the bottoms of the two types of trenches.
  • the source electrode 109 is formed in the body region 107, the source electrode 109 is adjacent to the body region lead-out region 110, and the upper surface of the source electrode 109 is connected to the upper surface of the body region lead-out region 110.
  • the surface is flush, the present invention is based on the body region 107 is electrically drawn out from the body region 110, and the upper surfaces of the source electrode 109 and the body region 107 are flush, so that the source electrode can be realized.
  • the equipotential extraction of 109 and the body region 107 is beneficial to prevent the device from premature breakdown.
  • the present invention does not need to prepare contact holes to extract the source electrode 109 and the body region 107 with the same potential, which can continue to reduce the original cell.
  • the source electrode 109 and the body region 107 are equal in potential without making contact holes. Lead out, and can prevent the device from breaking down in advance, and obtain stable device electrical properties.
  • the first trench 102 and the second trench 103 are perpendicular to each other, and the shape of the injection region 104 formed includes a square, for example, a square may be selected, and each body region 107 includes four
  • the body region lead-out regions 110 may be selected as a square shape, and the area of each body region lead-out region 110 is equal, and the adjacent body region lead-out regions 110 are spaced apart from each other, which are respectively located in the four injection regions 104.
  • the corners are formed around the source electrode 109.
  • the four body region lead-out regions 110 are symmetrically distributed in the body region 107.
  • the body region lead-out regions 110 are in the body region. 107 is symmetrically distributed, and the source electrode 109 with a symmetrical structure is obtained, which is beneficial to improve the electrical uniformity.
  • the source electrode structure 114 is in contact with both the upper surface of the source electrode 109 and the upper surface of the body region lead-out region 110 to electrically lead the source electrode 109 and the body region 107, wherein,
  • the material of the source electrode structure 114 may be aluminum but is not limited to this
  • the trench field effect transistor structure further includes a metal silicide layer 113 on the source electrode, and the metal silicide layer 113 on the source electrode is formed at least on the upper surface of the source electrode 109 and the body lead-out area 110, and the source electrode structure 114 is formed on the surface of the metal silicide layer 113 on the source to reduce contact resistance.
  • the metal silicide layer 113 on the source electrode is formed at least on the upper surface of the source electrode 109 and the body lead-out area 110, and the source electrode structure 114 is formed on the surface of the metal silicide layer 113 on the source to reduce contact resistance.
  • it may be Ti silicide, but it is not limited thereto.
  • the trench field effect transistor structure further includes an extraction gate structure, wherein the epitaxial layer 101 defines a device region B and a terminal region A.
  • the first trench 102 and the second trench 103 are formed in the device region B
  • the extraction gate structure is formed in the terminal region A
  • the extraction gate structure includes: an extraction gate trench 200
  • the extraction gate dielectric layer 201 formed on the inner wall of the extraction gate trench 200 is formed on the surface of the extraction gate dielectric layer 201 to form an extraction gate 202, and is formed on the terminal region and the extraction gate 202
  • the extraction gate electrode structure 203 is electrically connected, and the extraction gate electrode structure 203 is insulated from the source electrode structure 114.
  • a metal silicide layer 204 on the lead gate is further formed on the lead gate 202, and the lead gate electrode structure 203 is formed on the surface of the metal silicide layer 204 on the lead gate.
  • the first gate 111 and the second gate may be led out to a gate pad through a trench on the periphery.
  • the first gate 111 and the second gate The second gate pulls out the first trench and the second trench to the edge of the die, and then uses a large trench to string all the trenches at the edge of the die into the gate pad.
  • the first gate and the second gate are electrically drawn through the lead-out gate structure of the terminal region A.
  • the present invention also provides a pair of comparisons.
  • the trench field effect transistor provided by the comparison includes a semiconductor substrate 300, an epitaxial layer 301, a body region 302, a source 303, and a source contact hole. 304 and the source electrode structure 305.
  • the source 303 and the body region 302 are electrically led out based on the source contact hole 304.
  • a source contact hole needs to be prepared, which occupies a certain device space and is limited Due to the limitations of the photolithography process, in addition, the device structure of this example is further reduced with the pitch size, the source area is reduced, and the process difficulty of the source contact hole increases.
  • the OL margin (overlay photo) is aligned with the two layers. Measurement), when the source contact hole is filled with Ti/W to form the source electrode structure, the feature size CD of the device becomes smaller, which leads to the limitation of Ti process, etc. Ti cannot be sputtered into the contact hole uniformly, and a uniform silicide cannot be formed. , Ti/W in the hole cannot form a good metal contact, and the body region is prone to floating, the source and body region cannot form an equipotential lead, and the device has an early breakdown during the working process. Based on the implementation of the present invention The solutions of Example 1 and Example 2 can effectively solve the above-mentioned problems.
  • the present invention uses self-alignment technology to continue to reduce the cell size, without the need to set source contact holes to draw out the source and body regions with equipotential electrical potential, aiming at the square trench field
  • the closed-loop structure of the effect transistor solves the problem of the shrinkage of the cell size and the connection of the body area from the process and layout, thereby avoiding the problem of the device's premature breakdown. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial value.

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Abstract

本发明提供一种沟槽型场效应晶体管结构及制备方法，所述制备方法包括：提供半导体衬底，形成外延层、第一沟槽、第二沟槽、第一栅介质层、第一栅结构、第二栅介质层、第二栅结构、体区，形成源极注入掩膜，并基于其进行离子注入形成源极，形成源极电极结构。通过设计源极注入掩膜进行源极自对准注入，在形成源极的同时形成体区引出区，直接将源极和体区接出，本发明采用自对准技术，得以继续减小元胞尺寸，无需通过设置源极接触孔的方式将源极和体区进行等电势电性引出，针对方形沟槽型场效应晶体管闭环结构，从工艺和布局上解决随着元胞尺寸的缩小及体区的接出问题，从而避免出现器件提前击穿的问题。

Description

沟槽型场效应晶体管结构及其制备方法 技术领域
本发明涉及集成电路设计及制造技术领域，特别是涉及一种沟槽型场效应晶体管结构及其制备方法。
背景技术
沟槽型器件(如方块形布局的沟槽型场效应晶体管，square layout trench MOS)作为一种重要的功率器件具有很广泛的应用，其具有较低的导通电阻低、较快的开关速度和良好的抗雪崩冲击能力等。节能减排及市场竞争的要求在保证器件其它性能参数不变的条件下，进一步降低器件的导通电阻。众所周知，减小沟槽型器件元胞的横向间距，增加元胞密度是一种很有效的降低源漏极导通电阻的方法，然而，受光刻机台和刻蚀机台的能力限制，元胞的横向间距不可能一直减小下去，传统需要制备一定的空间制备接触孔以将器件的体区和源极进行电性引出，对于方块形布局的沟槽型场效应晶体管，Square layout为闭环结构，有比strip layout(条形布局)器件更高的沟道密度，相比strip layout的有较低的Ron(导通电阻)，但是随着沟槽型场效应晶体管的发展，需要更高密度的沟槽以降低导通电阻，降低器件损耗和提高开关速度，但是传统的square layout要足够的区域为形成接触孔，以便将闭环结构形成的独立的体区(body区)域与源极(source)电性引出，随着原胞尺寸的降低，已经无法满足通过开孔的形式形成接触孔将体区和源极接出，且二者难以实现等电势引出。
因此，如何提供一种沟槽型场效应晶体管结构及其制备方法以解决现有技术中的上述问题实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种沟槽型场效应晶体管结构及制备方法，用于解决现有技术中原胞尺寸难以继续减小及体区和源极难以有效引出等问题。
为实现上述目的及其他相关目的，本发明提供一种沟槽型场效应晶体管结构的制备方法，所述制备方法包括如下步骤：
提供半导体衬底，并于所述半导体衬底上形成外延层；
于所述外延层中形成若干个平行间隔排布的第一沟槽以及若干个平行间隔排布的第二沟槽，其中，所述第一沟槽与所述第二沟槽相交设置，以基于相邻的所述第一沟槽及所述第二沟槽围成若干个注入区；
于所述第一沟槽的内壁上形成第一栅介质层，于所述第一栅介质层上形成第一栅结构，所述第一栅结构填充于所述第一沟槽内，并于所述第二沟槽的内壁上形成第二栅介质层，于所述第二栅介质层上形成第二栅结构，所述第二栅结构填充于所述第二沟槽内；
对所述外延层进行离子注入以于所述注入区中形成体区，所述体区与所述第一沟槽及所述第二沟槽均相邻接；
于所述外延层上形成源极注入掩膜，所述源极注入掩膜包括若干个间隔的注入掩膜单元，所述注入掩膜单元覆盖所述第一沟槽与第二沟槽的交界处并延伸覆盖所述交界处周围的所述注入区，以于所述体区上形成至少一个遮挡区；
基于所述源极注入掩膜对所述外延层进行离子注入以于所述体区中形成源极，所述遮挡区构成体区引出区；以及
于所述外延层上形成与所述源极上表面及所述体区引出区的上表面均相接触的源极电极结构，以将所述源极及所述体区电性引出。
本发明还提供一种沟槽型场效应晶体管结构，优选采用本发明的沟槽型场效应晶体管结构的制备方法制备得到，当然也可是其他方法制备得到，所述沟槽型场效应晶体管结构包括：
半导体衬底；
形成于所述半导体衬底上的外延层，所述外延层中形成有若干个平行间隔排布的第一沟槽以及若干个平行间隔排布的第二沟槽，其中，所述第一沟槽与所述第二沟槽相交设置形成若干个交界处，且相邻的所述第一沟槽及所述第二沟槽围成若干个注入区；
第一栅介质层及第二栅介质层，分别形成于所述第一沟槽及所述第二沟槽内壁上；
第一栅极及第二栅极，分别形成于所述第一栅介质层及所述第二栅介质层表面，且所述第一栅极填充于所述第一沟槽内，所述第二栅极填充于所述第二沟槽内；
形成于所述注入区中的体区，所述体区与所述第一沟槽及所述第二沟槽相邻接，所述体区包括至少一个体区引出区，所述体区引出区与所述体区周围的所述交界处相邻接；
形成于所述体区中的源极，所述源极与所述体区引出区相邻接，且所述源极的上表面与所述体区引出区的上表面相平齐；以及
源极电极结构，所述源极电极结构与所述源极的上表面及所述体区引出区的上表面均相接触，以将所述源极及所述体区电性引出。
如上所述，本发明的沟槽型场效应晶体管结构及制备方法，通过设计源极注入掩膜进行源极自对准注入，在形成源极的同时形成体区引出区，直接将源极和体区接出，本发明采用自对准技术，得以继续减小元胞尺寸，无需通过设置源极接触孔的方式将源极和体区进行等 电势电性引出，针对方形沟槽型场效应晶体管闭环结构，从工艺和布局上解决随着元胞尺寸的缩小以及体区的接出问题，从而避免出现器件提前击穿的问题。
附图说明
图1显示为本发明沟槽型场效应晶体管制备的工艺流程图。
图2显示为本发明沟槽型场效应晶体管制备中形成外延层的结构示意图。
图3显示为本发明沟槽型场效应晶体管制备中形成第一沟槽及第二沟槽的俯视示意图。
图4显示为图3中A-B位置的截面示意图。
图5显示为本发明沟槽型场效应晶体管制备中形成第一栅介质层及第一栅结构的图示。
图6显示为本发明沟槽型场效应晶体管制备中形成体区的示意图。
图7显示为本发明沟槽型场效应晶体管制备中形成源极注入掩膜的俯视示意图。
图8显示为图7中A-B位置的截面示意图。
图9显示为图7中C-D位置的截面示意图。
图10显示为本发明沟槽型场效应晶体管制备形成源极电极结构A-B位置的截面示意图。
图11显示为本发明沟槽型场效应晶体管制备形成源极电极结构C-D位置的截面示意图。
图12显示为本发明沟槽型场效应晶体管制备形成引出栅结构A-B位置的截面示意图。
图13显示为本发明沟槽型场效应晶体管制备形成引出栅结构A-B位置的截面示意图。
图14显示为本发明对比例沟槽型场效应晶体管的俯视图。
图15显示为图14中M-N位置的截面示意图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
实施例一：
如图1所示，本发明提供一种沟槽型场效应晶体管结构的制备方法，包括如下步骤：
提供半导体衬底，并于所述半导体衬底上形成外延层；
于所述外延层中形成若干个平行间隔排布的第一沟槽以及若干个平行间隔排布的第二沟槽，其中，所述第一沟槽与所述第二沟槽相交设置，以基于相邻的所述第一沟槽及所述第二沟槽围成若干个注入区；
于所述第一沟槽的内壁上形成第一栅介质层，于所述第一栅介质层上形成第一栅结构，所述第一栅结构填充于所述第一沟槽内，并于所述第二沟槽的内壁上形成第二栅介质层，于所述第二栅介质层上形成第二栅结构，所述第二栅结构填充于所述第二沟槽内；
对所述外延层进行离子注入以于所述注入区中形成体区，所述体区与所述第一沟槽及所述第二沟槽均相邻接；
于所述外延层上形成源极注入掩膜，所述源极注入掩膜包括若干个间隔的注入掩膜单元，所述注入掩膜单元覆盖所述第一沟槽与第二沟槽的交界处并延伸覆盖所述交界处周围的所述注入区，以于所述体区上形成至少一个遮挡区；
基于所述源极注入掩膜对所述外延层进行离子注入以于所述体区中形成源极，所述遮挡区构成体区引出区，所述源极的上表面与所述体区引出区的上表面相平齐；以及
于所述外延层上形成与所述源极上表面及所述体区引出区的上表面均相接触的源极电极结构，以将所述源极及所述体区电性引出。
下面将结合具体附图详细说明本发明的半导体测试结构的制备方法。
如图1中的S1及图2所示，提供半导体衬底100，并于所述半导体衬底100上形成外延层101。
具体的，所述半导体衬底100可以为第一掺杂类型的衬底，其中，所述第一掺杂类型(即第一导电类型)可以是P型掺杂，也可以是N型掺杂，可以为采用离子注入工艺在本征半导体衬底中注入第一掺杂类型(P型或N型)的离子而形成的所述半导体衬底100，具体类型依实际器件需求设定，在本示例中，选择为N型掺杂衬底，另外，在一示例中，可以为重掺杂衬底，如可以是在所述半导体衬底100中掺杂的所述第一掺杂类型离子的浓度大于等于1×10 19/cm 3。需要说明的，所述半导体衬底100可以为硅衬底、锗硅衬底、碳化硅衬底等，在本示例中，所述半导体衬底100选用为N ++型掺杂的硅衬底，如可以是0.001-0.003ohm*cm。其中，第一掺杂类型与后续提到的第二掺杂类型(即第二导电类型)为相反的掺杂(导电)类型，当所述第一掺杂类型(第一导电类型)半导体为N型半导体、第二掺杂类型(第二导电类型)半导体为P型半导体时，本发明的沟槽MOSFET器件为N型器件；反之，本发明的沟槽MOSFET器件为P型器件。
另外，在一示例中，所述外延层101的掺杂类型与所述半导体衬底100的掺杂类型一致，在一可选示例中，所述外延层101的掺杂浓度低于所述半导体衬底100的掺杂浓度，其中，可以先采用外延工艺在所述第一掺杂类型的所述半导体衬底100的上表面形成本征外延层，然后再通过离子注入工艺在所述本征外延层内注入第一掺杂类型的离子以形成所述第一掺杂 类型的所述外延层101；在另一示例中，还可以采用外延工艺直接在所述第一掺杂类型的所述半导体衬底100的上表面外延形成所述第一掺杂类型的所述外延层101。本示例中，所述外延层101选用为N-型单晶硅外延层。
如图1中的S2及图3-4所示，于所述外延层101中形成若干个平行间隔排布的第一沟槽102以及若干个平行间隔排布的第二沟槽103，其中，所述第一沟槽102与所述第二沟槽103相交设置，以基于相邻的所述第一沟槽102及所述第二沟槽103围成若干个注入区104。所述第一沟槽102及所述第二沟槽103可以通过光刻刻蚀的工艺实现。
其中，图3和图4显示本发明一具体可选示例，图4显示为图3中A-B位置的截面图，图中仅示意出相关结构及其位置关系，各结构数量不应过分限制，其中，所述第一沟槽102与所述第二沟槽103相互垂直，形成的所述注入区104的形状为方形，两个相邻的所述第一沟槽102以及两个相邻的所述第二沟槽103围成一具有四边形结构的所述注入区104，构成一方块形布局的沟槽型场效应晶体管(square layout trench MOS)，从而可以在所述第一沟槽102及所述第二沟槽103中布置形成栅极，以制备器件结构，提高器件的沟道密度，降低器件的导通电阻，在一可选示例中，所述第一沟槽102之间的间距与所述第二沟槽103之间的间距相等，从而可以得到若干个大小相等的正方形的所述注入区104，当然，所述注入区104的形状还可以是长方形或者其他基于第一沟槽102和第二沟槽103得到的形状，并不以此为限，可以依据实际需求设定。
如图1中的S3及图5所示，于所述第一沟槽102的内壁上形成第一栅介质层105，于所述第一栅介质层105上形成第一栅结构106，所述第一栅结构106填充于所述第一沟槽102内，并于所述第二沟槽103的内壁上形成第二栅介质层(图中未示出)，于所述第二栅介质层上形成第二栅结构(图中未示出)，所述第二栅结构填充于所述第二沟槽103内；
具体的，在一示例中，于所述第一沟槽102的底部、侧壁形成连续的所述第一栅介质层105，所述第一栅介质层105的上表面与所述外延层101的上表面相平齐，其形成工艺可以是在所述第一沟槽102的底部、侧壁以及所述第一沟槽102周围的所述外延层101上形成连续的所述第一栅介质材料层，并去除所述外延层101上方的所述第一栅介质材料层，得到位于所述第一沟槽102的底部及侧壁上的第一栅介质层105，可选地，还可以先保留所述外延层101上的所述第一栅介质材料层，共同作为后续工艺之用，所述第一栅介质材料层作为所述第一栅介质层105，其中，可以采用热氧化或化学气相沉积工艺形成所述第一栅介质层105。同理，对于所述第二栅介质层与所述第一栅介质层105的形成工艺及结构类似，在此不再赘述。另外，在一示例中，所述第一沟槽102及所述第二沟槽103形成之后，基于同一工艺形 成所述第一栅介质层105及所述第二栅介质层。
作为示例，形成所述第一栅介质层105及所述第二栅介质层之前还包括步骤：于所述第一沟槽102及所述第二沟槽103的侧部及底部表面形成牺牲氧化层，并去除所述牺牲氧化层，以基于所述牺牲氧化层对所述第一沟槽102内壁及所述第二沟槽103内壁进行修复，对刻蚀过程的损伤进行修复，可选地，可以通过热氧化工艺形成所述牺牲层，在一示例中，可以采用湿法刻蚀工艺去除所述牺牲氧化层。
另外，形成于所述第一沟槽102内壁上的所述第一栅介质层105的表面构成一栅极凹槽，所述第一栅结构106填充于所述栅极凹槽中，其中，所述第一栅结构106可以是作为器件的栅极使用，其材料包括但不限于多晶硅，此时，所述第一栅结构106低于所述外延层101的表面，所述栅极沟槽中还留有在所述第一栅结构106的上表面形成绝缘层的空间，以最终形成场效应沟槽晶体管结构，在另外示例中，所述第一栅结构106可以是不是直接作为器件的栅极使用，后续还需要对其进行刻蚀得到器件的栅极，以利于在后续工艺中对栅极的保护。同理，所述第二栅结构与所述第一栅结构106的形成工艺及结构类似。另外，在一示例中，所述第一栅介质层105及所述第二栅介质层形成之后，基于同一工艺形成所述第一栅结构106及所述第二栅结构。
如图1中的S4及图6所示，对所述外延层101进行离子注入以于所述注入区104中形成体区107，所述体区107位于相邻的沟槽之间，所述体区107与所述第一沟槽102及所述第二沟槽103均相邻接，在一示例中，所述体区107的掺杂类型与所述外延层101及所述半导体衬底100的掺杂类型相反，所述体区107具有所述第二掺杂类型，在本示例中，所述体区107选择为P型轻掺杂。另外，在一示例中，在形成所述第一栅结构106和所述第二栅结构之后，可以直接进行离子注入以形成所述体区107，从而无需制备掩膜层，注入离子可以进入所述第一栅结构106中，另外，还可以是所述第一栅介质层105形成在需要注入形成体区107的外延层上，同时，在形成所述第一栅结构106时，其沉积的材料层也形成在了所述外延层上方，形成在对应部分的第一栅介质层105表面，此时，在进行离子注入形成所述体区107时，可以去除这一部分外延层顶部的用于形成第一栅结构106的材料层并露出对应部分的第一栅介质层105，此时再进行离子注入，这里部分第一栅介质层可以在离子注入时保护所述外延层。在另一优选示例中，在进行离子注入形成所述体区107和后续的所述源极109之后的后续工艺中，还需要进一步对所述第一栅结构106和所述第二栅结构进行刻蚀以形成器件栅极。在一可选示例中，所述体区107的下表面高于所述第一沟槽102及所述第二沟槽103的底部，所述体区107底部与两种沟槽的底部之间具有一高度差，另外，在一示例中， 还包括在离子注入后进行高温退火的步骤，以形成所述体区107，其中，在一示例中，可以根据器件的阈值电压、击穿电压等性能参数需求调整注入剂量。
如图1中的S5及图7所示，在所述体区107形成之后，于所述外延层101上形成源极注入掩膜108，所述源极注入掩膜108包括若干个注入掩膜单元108a，且相邻的所述注入掩膜单元108a之间具有间距，所述注入掩膜单元108a覆盖所述第一沟槽102与第二沟槽103的交界处并延伸覆盖所述交界处周围的所述注入区104，以于所述体区107中形成至少一个遮挡区，在一示例中，所述注入掩膜单元108a延伸覆盖其周围最近邻的四个所述注入区104，其中，所述遮挡区即所述注入掩膜单元108a所遮挡的所述体区107的那一部分区域，从而在所述源极注入掩膜的遮挡下，这一部分区域的体区不进行离子注入，仍然是作为体区的部分，其中，所述源极注入掩膜的特征尺寸可以相对较大，有利于工艺的实施，在一示例中，所述源极注入掩膜108的特征尺寸(CD)介于0.3-0.5微米之间，可以是0.35微米、0.4微米或者0.45微米，另外，其可以采用I line机台即可实现。
接着，如图1中的S6及图7-9所示，基于所述源极注入掩膜108对所述外延层101进行离子注入，以于所述体区107中形成源极109，所述遮挡区构成体区引出区110，从而所述源极109的上表面与所述体区引出区109的上表面相平齐，此时，所述源极109的上表面是指对体区107进行注入后的上表面，也即外延层101的上表面，此时的体区引出区110的上表面是指被所述源极注入掩膜108遮挡的部分未进行源极109注入的上表面，也即所述体区107的上表面，也即外延层101的上表面，基于上述工艺，本发明在所述源极注入掩膜108的遮挡下进行源极109离子注入，形成源极109的同时形成了将体区107的引出区域，即同时定义出了所述体区引出区110，从而无需制备源极109接触孔便将所述源极109和所述体区107进行了电性引出，传统器件结构中源极接触孔和器件沟槽之间需要严格控制两层之间的距离(overlap)，随着器件特征尺寸(pitch)的减小，不同源极接触孔与器件沟槽之间的overlap的不对称就会带来VT(阈值电压)或者ID(漏极漏电)的问题，本发明采用自对准工艺就不存在这个问题，只要源极电极结构(metal)在有源区接触好，器件沟槽和源极之间的overlap就是对称的，本发明的方案中所述源极109和所述体区107的上表面相平齐，可以实现所述源极109和所述体区107的等电势电性引出，有利于防止器件出现提前击穿的情况，有利于防止在体区floating(体区没有接出于source等电势，容易在工作中产生电势差，从而引起ID异常)情况下，闭环结构工作过程中容易累计电荷从而造成击穿的问题，本发明的上述方案可以继续减小原胞尺寸，将pitch size进一步缩小到小于0.9um以下，进一步提高器件的沟槽密度，降低导通电阻，降低器件消耗，提高开关响应速度，同时，在原胞尺寸减小的趋势下， 无需制备接触孔便将源极109和体区107等电势引出，且能够使器件不会出现提前击穿的情况，得到稳定的器件电性，在工艺制造上也易于实现和量产。
其中，在一示例中，所述注入掩膜单元108a覆盖所述第一沟槽102与第二沟槽103的交界处并延伸覆盖所述交界处周围的四个所述注入区104，以使每一所述体区107中形成四个所述体区引出区110，即所述注入掩膜单元108a所遮挡的所述体区107的部分构成所述体区引出区110，在所述注入掩膜单元108a的作用下，四个所述体区引出区110之间具有间距并分别位于所述注入区104的四个角落，形成于所述源极109的周围，优选地，四个所述体区引出区110在所述体区107中呈对称分布，从而有利于提高电性均匀性。
在一示例中，所述第一沟槽102与所述第二沟槽103相互垂直，形成的所述注入区104的形状包括方形，其中，所述注入掩膜单元108a的形状包括方形，且所述注入掩膜单元108a所相交的各所述注入区104的相交区域面积相同，所述注入区104的形状选择为形成正方形，所述注入掩膜单元108a也选择为正方形，从而形成的所述体区引出区110也为正方形，在所述体区107中呈对称分布，得到了对称结构的所述源极109，有利于提高电性均匀性。
如图10及图11所示，作为一示例，前述步骤中所形成的所述第一栅结构106、所述第二栅结构、所述第一栅介质层105及所述第二栅介质层的上表面相平齐，其中，可以是所述第一栅极介质层105及所述第二栅极介质层只形成在所述第一沟槽102和所述第二沟槽103当中，还可以是所述第一栅极介质层105和所述第二栅极介质层形成在所述第一沟槽102和所述第二沟槽103当中还延伸形成在所述外延层101的表面，其中：
该示例在形成所述源极109后还包括步骤：对所述第一栅结构106进行回刻以得到第一栅极111，并于所述第一栅极111上形成第一绝缘层112，所述第一绝缘层112填充于所述第一沟槽102内，同样，对所述第二栅结构进行回刻以得到第二栅极，并于所述第二栅极上形成第二绝缘层，所述第二绝缘层填充于所述第二沟槽103内，优选地，所述第一绝缘层112、所述第二绝缘层、所述体区107及所述源极109的上表面相平齐，所述源极电极结构114还延伸形成于所述第一绝缘层112及所述第二绝缘层的上表面，其中，在一示例中，形成的所述第一栅极111及所述第二栅极的上表面高于所述源极109的下表面，另外，可以采用高密度电浆工艺(HDP)淀积高密度等离子体氧化层，即形成第一绝缘材料层及第二绝缘材料层，再对第一绝缘材料层及第二绝缘材料层进行CMP，即对淀积的高密度等离子体氧化层进行CMP，以得到所述第一绝缘层112及所述第二绝缘层，在一示例中，所述第一绝缘材料层及所述第二绝缘材料层的高度高于所述外延层101的上表面，即凸出于所述第一沟槽102及所述第二沟槽103，再对所述第一绝缘材料层及所述第二绝缘材料层进行CMP得到所述第一绝 缘层112及所述第二绝缘层，从而可以提高形成的绝缘层的质量，在一示例中，对所述第一栅结构106及所述第二栅极结构的回刻深度介于2000A-3000A之间，即可以理解为所述第一栅极111及所述第二栅极的上表面与所述外延层101的上表面之间的距离介于2000A-3000A之间，本示例中可以是2500A，沉积的所述第一绝缘材料层及所述第二绝缘材料层的厚度介于3000A-4000A之间，本示例中，对应刻蚀掉的2500A，沉积的HDP氧化层可以是3000A。
作为示例，参见图10和图11所示，形成所述第一绝缘层112及所述第二绝缘层之后还包括步骤：至少于所述源极109上表面及所述体区引出区110上表面的表面形成源极109上金属硅化物层(silicide)，在一示例中，可以是Ti silicide，但并不以此为限，所述源极电极结构114形成于所述源极109上金属硅化物层表面，其中，所述金属硅化物的形成工艺可以是，至少在所述体区107及所述源极109的上表面形成金属钛，再进行RTP(Rapid Thermal Processing，快速热处理)，以形成所述金属硅化物层，以降低接触电阻。
如图1中的S7及图10-11所示，于所述外延层101上形成与所述源极109上表面及所述体区引出区110上表面均相接触的源极电极结构114，以将所述源极109及所述体区107电性引出，其中，所述源极电极结构114的材料可以是铝但不局限于此。
如图12-13所示，所述沟槽型场效应晶体管结构的制备方法还包括制备引出栅结构的步骤，其中，所述外延层101中定义有器件区B和终端区A，在一示例中，所述第一沟槽102及所述第二沟槽103形成于所述器件区B中，形成所述第一沟槽102及所述第二沟槽103的同时还于所述终端区A中制备引出栅沟槽200，并于所述引出栅沟槽200的内壁上形成引出栅介质层201，于所述引出栅介质层201表面形成引出栅极202，且所述终端区A上还形成有与所述引出栅极202电连接的引出栅电极结构203，其中，所述引出栅介质层201与所述第一栅介质层105及所述第二栅介质层基于同一工艺形成，所述引出栅极202与所示第一栅结构106及所述第二栅极结构基于同一工艺形成，在一示例中，当刻蚀所述第一栅结构106及所述第二栅结构形成第一栅极111及所述第二栅极时，保留所述引出栅沟槽200内的所述引出栅极202，使得在后续形成引出栅电极结构时与引出栅电极结构电连接，进行电性引出。另外，所述第一栅极111及所述第二栅极可以通过外围的沟槽引出到栅极焊垫(gate pad)，在一示例中，将所述第一栅极111及所述第二栅极拉出所述第一沟槽及所述第二沟槽到晶粒(die)边缘，再用大沟槽把所有晶粒边缘的沟槽串起来引入到栅极焊垫，在一可选示例中，通过所述终端区A的所述引出栅结构将所述第一栅极及所述第二栅极电性引出。
在一示例中，所述引出栅电极结构203与所述源极电极结构114基于同一工艺制备，例如可以是形成一整块的金属材料层，之后再进行刻蚀，如可以利用光罩进行刻蚀，刻蚀开所 述源极电极结构114与所述引出栅电极结构203，使二者相绝缘，在另一可选示例中，形成所述引出栅极202后还包括制备引出栅极上金属硅化物层204的步骤，且所述引出栅电极结构203形成于所述引出栅上金属硅化物层204的表面，以降低接触电阻，在一可选示例中，，所述引出栅极202的上表面与所述源极109的上表面相平齐，所述引出栅电极结构204与所述源极电极结构114绝缘且二者基于同一工艺制备。
实施例二：
如图10-13所示，并参阅图1-9，本发明还提供一种沟槽型场效应晶体管结构，所述场效应晶体管结构优选采用本发明实施例一的沟槽型场效应晶体管结构的制备方法制备得到，当然也可是其他方法制备得到，所述沟槽型场效应晶体管结构包括：半导体衬底100、外延层101、形成于所述外延层101中的第一沟槽102及第二沟槽103、第一栅介质层105、第二栅介质层(图中未示出)、第一栅极111、第二栅极(图中未示出)、体区107、源极109以及源极电极结构114，其中：
所述半导体衬底100可以为第一掺杂类型的衬底，在本示例中，选择为N型掺杂衬底，另外，在一示例中，可以为重掺杂衬底，如可以是在所述半导体衬底100中掺杂的所述第一掺杂类型离子的浓度大于等于1×10 19/cm 3。需要说明的，所述半导体衬底100可以为硅衬底、锗硅衬底、碳化硅衬底等，在本示例中，所述半导体衬底100选用为N ++型掺杂的硅衬底，如可以是0.001-0.003ohm*cm。
另外，在一示例中，所述外延层101的掺杂类型与所述半导体衬底100的掺杂类型一致，在一可选示例中，所述外延层101的掺杂浓度低于所述半导体衬底100的掺杂浓度，本示例中，所述外延层101选用为N-型单晶硅外延层。
具体的，所述外延层101中形成有若干个平行间隔排布的第一沟槽102以及若干个平行间隔排布的第二沟槽103，其中，所述第一沟槽102与所述第二沟槽103相交设置形成若干个交界处，且相邻的所述第一沟槽102及所述第二沟槽103围成若干个注入区104，在一示例中，所述第一沟槽102与所述第二沟槽103相互垂直，形成的所述注入区104的形状为括方形，两个相邻的所述第一沟槽102以及两个相邻的所述第二沟槽103围成一具有四边形结构的所述注入区104，构成一方块形布局的沟槽型场效应晶体管(square layout trench MOS)，从而可以在所述第一沟槽102及所述第二沟槽103中布置形成栅极，以制备器件结构，提高器件的沟道密度，降低器件的导通电阻，在一可选示例中，所述第一沟槽102之间的间距与所述第二沟槽103之间的间距相等，从而可以得到若干个大小相等的正方形的所述注入区104，当然，所述注入区104的形状还可以是长方形或者其他基于第一沟槽102和第二沟槽 103得到的形状，并不以此为限，可以依据实际需求设定。
所述第一栅介质层105连续的形成于所述第一沟槽102的底部及侧壁，所述第一栅介质层105的上表面与所述外延层101的上表面相平齐，还可以是所述第一栅介质层105连续地形成于所述第一沟槽102的底部、侧壁以及所述第一沟槽102周围的所述外延层101表面。同理，对于所述第二栅介质层与所述第一栅介质层105的结构类似，在此不再赘述。
所述第一栅极111形成于所述第一栅介质层105表面，且所述第一栅极111填充于所述第一沟槽102内，且所述第一栅极111的上表面低于所述外延层101的上表面，其材料包括但不限于多晶硅，在一示例中，所述第一栅极111的上表面与所述外延层101的上表面之间的间距2000A-3000A之间，本示例中可以是2500A，同理，所述第二栅极与所述第一栅极111的结构类似，在此不再赘述。
作为示例，所述沟槽型场效应晶体管结构还包括形成于所述第一栅极111上且填充于所述第一沟槽102内的第一绝缘层112以及形成于所述第二栅极上且填充于所述第二沟槽内的第二绝缘介质层，且所述源极电极结构114还延伸形成于所述第一绝缘层112及所述第二绝缘层的上表面，其中，所述第一绝缘层及所述第二绝缘层的材料包括但不限于氧化硅。
所述体区107形成于所述注入区104中，所述体区107与所述第一沟槽102及所述第二沟槽103相邻接，所述体区107包括至少一个体区引出区110，所述体区引出区110与所述体区107周围紧邻的所述交界处相邻接；在一示例中，所述体区107的掺杂类型与所述外延层101及所述半导体衬底100的掺杂类型相反，所述体区107具有所述第二掺杂类型，在本示例中，所述体区107选择为P型轻掺杂。另外，所述体区107的下表面高于所述第一沟槽102及所述第二沟槽103的底部，所述体区107底部与两种沟槽的底部之间具有一高度差。
所述源极109形成于所述体区107中，所述源极109与所述体区引出区110相邻接，且所述源极109的上表面与所述体区引出区110的上表面相平齐，本发明基于所述体区引出区110将所述体区107电性引出，并且所述源极109和所述体区107的上表面相平齐，可以实现所述源极109和所述体区107的等电势电性引出，有利于防止器件出现提前击穿的情况，本发明无需制备接触孔便将源极109和体区107等电势引出，可以继续减小原胞尺寸，进一步提高器件的沟槽密度，降低导通电阻，降低器件消耗，提高开关响应速度，同时，在原胞尺寸减小的趋势下，无需制备接触孔便将源极109和体区107等电势引出，且能够使器件不会出现提前击穿的情况，得到稳定的器件电性。
作为示例，所述第一沟槽102与所述第二沟槽103相互垂直，形成的所述注入区104的形状包括方形，例如，可以选择为正方形，每一所述体区107包括四个所述体区引出区110， 可以选择为正方形，各所述体区引出区110的面积相等且相邻的所述体区引出区110之间具有间距，分别位于所述注入区104的四个角落，形成于所述源极109的周围，优选地，四个所述体区引出区110在所述体区107中呈对称分布，优选地，所述体区引出区110在所述体区107中呈对称分布，得到了对称结构的所述源极109，有利于提高电性均匀性。
所述源极电极结构114与所述源极109的上表面及所述体区引出区110的上表面均相接触，以将所述源极109及所述体区107电性引出，其中，所述源极电极结构114的材料可以是铝但不局限于此
作为示例，所述沟槽型场效应晶体管结构还包括源极上金属硅化物层113，所述源极上金属硅化物层113至少形成于所述源极109上表面和所述体区引出区110上表面，且所述源极电极结构114形成于所述源极上金属硅化物层113表面，以降低接触电阻，在一示例中，可以是Ti silicide，但并不以此为限。
作为示例，如图12及13所示，所述沟槽型场效应晶体管结构还包括引出栅结构，其中，所述外延层101中定义有器件区B和终端区A，在一示例中，所述第一沟槽102及所述第二沟槽103形成于所述器件区B中，所述引出栅结构形成于所述终端区A中，所述引出栅结构包括：引出栅沟槽200，形成于所述引出栅沟槽200的内壁上的引出栅介质层201，形成于所述引出栅介质层201表面形成引出栅极202，以及形成于所述终端区上与所述引出栅极202电连接的引出栅电极结构203，且所述引出栅电极结构203与所述源极电极结构114相绝缘。在另一可选示例中，所述引出栅极202上还形成有引出栅极上金属硅化物层204，且所述引出栅电极结构203形成于所述引出栅上金属硅化物层204的表面，以降低接触电阻。另外，所述第一栅极111及所述第二栅极可以通过外围的沟槽引出到栅极焊垫(gate pad)，在一示例中，将所述第一栅极111及所述第二栅极拉出所述第一沟槽及所述第二沟槽到晶粒(die)边缘，再用大沟槽把所有晶粒边缘的沟槽串起来引入到栅极焊垫，在一可选示例中，通过所述终端区A的所述引出栅结构将所述第一栅极及所述第二栅极电性引出。
对比例：
如图14-15所示，本发明还提供一对比例，该对比例提供的沟槽型场效应晶体管包括半导体衬底300,、外延层301、体区302、源极303、源极接触孔304以及源极电极结构305，该对比例中基于源极接触孔304实现源极303和体区302电性引出，该对比例中需要制备源极接触孔，占据一定的器件空间，且受限于光刻工艺的限制，另外，该示例的器件结构随着特征尺寸(pitch size)进一步降低，源极区域缩小，源极接触孔的工艺难度增加，O.L margin(over lay photo两层对准的量测)，源极接触孔内填充Ti/W形成源极电极结构时，器件特 征尺寸CD变小，导致Ti工艺等受限，Ti不能均匀的溅射到接触孔中，不能形成均匀的silicide，孔内Ti/W无法形成较好的金属接触，且体区容易出现floating的情况，源极和体区不能形成等电势引出，器件在工作过程中出现提前击穿现象，而基于本发明实施例一和实施例二的方案可以有效解决上述问题。
综上所述，本发明的沟槽型场效应晶体管结构及制备方法，通过设计源极注入掩膜进行源极自对准注入，在形成源极的同时形成体区引出区，直接将源极和体区接出，本发明采用自对准技术，得以继续减小元胞尺寸，无需通过设置源极接触孔的方式将源极和体区进行等电势电性引出，针对方形沟槽型场效应晶体管闭环结构，从工艺和布局上解决随着元胞尺寸的缩小以及体区的接出问题，从而避免出现器件提前击穿的问题。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (13)

  1. 一种沟槽型场效应晶体管结构的制备方法，其特征在于，所述制备方法包括如下步骤：
    提供半导体衬底，并于所述半导体衬底上形成外延层；
    于所述外延层中形成若干个平行间隔排布的第一沟槽以及若干个平行间隔排布的第二沟槽，其中，所述第一沟槽与所述第二沟槽相交设置，以基于相邻的所述第一沟槽及所述第二沟槽围成若干个注入区；
    于所述第一沟槽的内壁上形成第一栅介质层，于所述第一栅介质层上形成第一栅结构，所述第一栅结构填充于所述第一沟槽内，并于所述第二沟槽的内壁上形成第二栅介质层，于所述第二栅介质层上形成第二栅结构，所述第二栅结构填充于所述第二沟槽内；
    对所述外延层进行离子注入以于所述注入区中形成体区，所述体区与所述第一沟槽及所述第二沟槽均相邻接；
    于所述外延层上形成源极注入掩膜，所述源极注入掩膜包括若干个间隔的注入掩膜单元，所述注入掩膜单元覆盖所述第一沟槽与第二沟槽的交界处并延伸覆盖所述交界处周围的所述注入区，以于所述体区上形成至少一个遮挡区；
    基于所述源极注入掩膜对所述外延层进行离子注入以于所述体区中形成源极，所述遮挡区构成体区引出区；以及
    于所述外延层上形成与所述源极上表面及所述体区引出区的上表面均相接触的源极电极结构，以将所述源极及所述体区电性引出。
  2. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，形成所述源极之后还包括步骤：对所述第一栅结构进行回刻以得到第一栅极，并于所述第一栅极上形成第一绝缘层，所述第一绝缘层填充于所述第一沟槽内，对所述第二栅结构进行回刻以得到第二栅极，并于所述第二栅极上形成第二绝缘层，所述第二绝缘层填充于所述第二沟槽内，且所述源极电极结构还延伸形成于所述第一绝缘层及所述第二绝缘层的上表面。
  3. 根据权利要求2所述的沟槽型场效应晶体管结构的制备方法，其特征在于，形成所述第一绝缘层及所述第二绝缘层后还包括步骤：至少于所述源极上表面及所述体区引出区上表面形成源极上金属硅化物层，所述源极电极结构形成于所述源极上金属硅化物层表面。
  4. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，形成所述第一栅介质层及所述第二栅介质层之前还包括于所述第一沟槽及所述第二沟槽的内壁表面形成牺牲氧化层并去除所述牺牲氧化层以进行沟槽内壁修复的步骤。
  5. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，所述注入掩膜单元覆盖所述第一沟槽与第二沟槽的交界处并延伸覆盖所述交界处周围的四个所述注入区，以使每一所述体区中形成四个所述体区引出区。
  6. 根据权利要求5所述的沟槽型场效应晶体管结构的制备方法，其特征在于，所述第一沟槽与所述第二沟槽相互垂直，形成的所述注入区的形状包括方形，其中，所述注入掩膜单元的形状包括方形，且所述注入掩膜单元与各所述注入区相交区域的面积相同。
  7. 根据权利要求1所述的沟槽型场效应晶体管结构的制备方法，其特征在于，所述沟槽型场效应晶体管结构的制备中还包括制备引出栅结构的步骤，其中，所述外延层中定义有器件区及终端区，所述第一沟槽及所述第二沟槽形成于所述器件区中，制备所述引出栅结构的步骤包括：形成所述第一沟槽及所述第二沟槽的同时于所述终端区中制备引出栅沟槽，于所述引出栅沟槽的内壁上形成引出栅介质层，于所述引出栅介质层表面形成引出栅极，于所述终端区上形成与所述引出栅极电连接的引出栅电极结构，且所述引出栅电极结构与所述源极电极结构相绝缘。
  8. 根据权利要求7所述的沟槽型场效应晶体管结构的制备方法，其特征在于，所述引出栅极的上表面与所述源极的上表面相平齐，其中，形成所述引出栅极后还包括于所述引出栅极上表面制备引出栅极上金属硅化物层的步骤，且所述引出栅电极结构形成于所述引出栅上金属硅化物层的表面。
  9. 一种沟槽型场效应晶体管结构，其特征在于，所述沟槽型场效应晶体管结构包括：
    半导体衬底；
    外延层，形成于所述半导体衬底上，所述外延层中形成有若干个平行间隔排布的第一沟槽以及若干个平行间隔排布的第二沟槽，其中，所述第一沟槽与所述第二沟槽相交设置形成若干个交界处，且相邻的所述第一沟槽及所述第二沟槽围成若干个注入区；
    第一栅介质层及第二栅介质层，分别形成于所述第一沟槽及所述第二沟槽内壁上；
    第一栅极及第二栅极，分别形成于所述第一栅介质层及所述第二栅介质层表面，且所述第一栅极填充于所述第一沟槽内，所述第二栅极填充于所述第二沟槽内；
    体区，形成于所述注入区中，所述体区与所述第一沟槽及所述第二沟槽相邻接，所述 体区包括至少一个体区引出区，所述体区引出区与所述体区周围的所述交界处相邻接；
    源极，形成于所述体区中，所述源极与所述体区引出区相邻接，且所述源极的上表面与所述体区引出区的上表面相平齐；以及
    源极电极结构，所述源极电极结构与所述源极的上表面及所述体区引出区的上表面均相接触，以将所述源极及所述体区电性引出。
  10. 根据权利要求9所述的沟槽型场效应晶体管结构，其特征在于，所述沟槽型场效应晶体管结构还包括形成于所述第一栅极上且填充于所述第一沟槽内的第一绝缘层以及形成于所述第二栅极上且填充于所述第二沟槽内的第二绝缘介质层，且所述源极电极结构还延伸形成于所述第一绝缘层及所述第二绝缘层的上表面。
  11. 根据权利要求9所述的沟槽型场效应晶体管结构，其特征在于，所述沟槽型场效应晶体管结构还包括源极上金属硅化物层，所述源极上金属硅化物层至少形成于所述源极上表面和所述体区上表面，且所述源极电极结构形成于所述源极上金属硅化物层表面。
  12. 根据权利要求9所述的沟槽型场效应晶体管结构，其特征在于，所述第一沟槽与所述第二沟槽相互垂直，所述注入区的形状包括方形，每一所述体区包括四个所述体区引出区，各所述体区引出区的面积相等且相邻的所述体区引出区之间具有间距。
  13. 根据权利要求9所述的沟槽型场效应晶体管结构，其特征在于，所述沟槽型场效应晶体管结构还包括引出栅结构，其中，所述外延层中定义有器件区及终端区，所述第一沟槽及所述第二沟槽形成于所述器件区中，所述引出栅结构形成于所述终端区中，所述引出栅结构包括：引出栅沟槽，形成于所述引出栅沟槽的内壁上的引出栅介质层，形成于所述引出栅介质层表面形成引出栅极，以及形成于所述终端区上与所述引出栅极电连接的引出栅电极结构，且所述引出栅电极结构与所述源极电极结构相绝缘。
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