WO2019157819A1 - 一种具有三维沟道的复合栅igbt芯片 - Google Patents

一种具有三维沟道的复合栅igbt芯片 Download PDF

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WO2019157819A1
WO2019157819A1 PCT/CN2018/106113 CN2018106113W WO2019157819A1 WO 2019157819 A1 WO2019157819 A1 WO 2019157819A1 CN 2018106113 W CN2018106113 W CN 2018106113W WO 2019157819 A1 WO2019157819 A1 WO 2019157819A1
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region
igbt chip
doped
gate electrode
trench
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PCT/CN2018/106113
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English (en)
French (fr)
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刘国友
朱春林
朱利恒
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株洲中车时代电气股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a composite gate IGBT chip having a three-dimensional channel.
  • IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal-Oxide-Semiconductor Field
  • the substrate mainly includes a substrate 101, an N well region 102, a P well region 103, an N+ doping region 104, a P+ doping region 105, a planar gate electrode 106, a gate oxide layer 107, a passivation layer 108, and Metal layer 109.
  • the main advantage of the IGBT chip with planar gate structure shown in FIG. 1 is that the process is simple in fabrication, low in equipment requirements, and the planar grid has good withstand voltage performance and high skin solidness, and thus can be used in a place where the working environment is relatively harsh.
  • the channel region is on the surface, the channel density is limited by the surface area of the chip, resulting in a weaker conductance modulation effect in the IGBT chip body and a higher conduction voltage drop.
  • the substrate mainly includes a substrate 201, an N well region 202, a P well region 203, an N+ doping region 204, a P+ doping region 205, a trench gate 206, a gate oxide layer 207, and a passivation layer 208. And a metal layer 209.
  • a trench gate structure as shown in FIG. 2 is used instead of the planar gate structure. As shown in FIG.
  • the trench gate is formed by an etching process, so that the channel enters the substrate body, and the channel is converted from the lateral direction to the longitudinal direction, thereby realizing the one-dimensional current channel, effectively eliminating the JFET effect in the planar gate channel.
  • the cell size is reduced, so that the channel density is no longer limited by the chip surface area, which greatly increases the cell density and greatly increases the chip current density.
  • the saturation current of the chip is too large, which weakens the short-circuit performance of the chip, thereby affecting the safe working area of the chip.
  • FIG. 3 is a schematic cross-sectional view of a half cell of an IGBT chip having a cascode and a trench gate structure in the prior art.
  • the method mainly includes: a substrate 301, an N well region 302, a P well region 303, an N+ doping region 304, a P+ doping region 305, a trench gate 306, a gate 307, a gate oxide layer 308, A passivation layer 309 and a metal layer 310.
  • a trench gate structure as shown in FIG. 2 is replaced by a structure in which the gate and trench gates coexist as shown in FIG.
  • the bottom of the trench gate in Figures 2 and 3 has some limitations on the resistance of the IGBT chip. Compared with the IGBT chip with planar gate structure shown in FIG. 1, it improves the performance of the IGBT chip while sacrificing the withstand voltage and skin properties of the planar gate portion.
  • the present invention provides a composite gate IGBT chip having a three-dimensional channel, including a plurality of cells, the cells including:
  • Two P-well regions formed by implanting P-type impurities into the cells on both side regions of the trench, wherein a depth of the P-well region is less than a depth of the trench;
  • the impurity region includes an adjacent N++ doped region doped with an N-type impurity and a P++ doped region doped with a P-type impurity;
  • the P well region is not provided with a surface of the doped region and a portion of the second oxide layer of the doped region;
  • the cell further includes an N-well region under the P-well region and in contact with a lower surface and a side of the P-well region, the N-well region having a width greater than the P-well The width of the area.
  • the second oxide layer includes a first oxidation region adjacent to the doped region, a second oxidation region away from the doped region, and a smooth connection between the first oxidation region and the second oxidation region a third oxidized region, the first oxidized region covering at least a surface of the P-well region where the doped region is not disposed, and a portion of the doped region, the second oxidized region having a thickness greater than the first oxidized region Thickness of the zone;
  • planar polysilicon gate electrode is uniformly disposed in thickness.
  • a plurality of the N++ doped regions and P++ doped regions are periodically spaced apart in a direction in which the trenches extend along the surface of the cell.
  • planar polysilicon gate electrode is not electrically connected to the trench polysilicon gate electrode.
  • planar polysilicon gate electrode and the trench polysilicon gate electrode are electrically connected through an external gate trace.
  • the cell further comprises:
  • the thickness of the third oxide layer is uniformly set, and the thickness of the passivation layer is uniformly set.
  • the doped region has a junction depth that is less than a junction depth of the P-well region.
  • the cell is a strip cell structure, a square cell structure, or a hexagonal cell structure.
  • a portion of the first oxide layer that is in the channel region has a thickness greater than or equal to a thickness of a portion of the second oxide layer that is in the channel region.
  • a portion of the first oxide layer that is in the channel region has a thickness greater than or equal to a thickness of a portion of the second oxide layer that is in the channel region.
  • the IGBT chip provided by the invention has a composite gate structure of a planar polysilicon gate electrode and a trench polysilicon gate electrode, which utilizes the characteristics of high channel and channel density in the trench polysilicon gate electrode, and utilizes a planar polysilicon gate electrode.
  • the small parasitic capacitance characteristics greatly increase the density of the IGBT chip, and retain the characteristics of low pass rate, high current density and wide safe working area of the planar polysilicon gate electrode of the trench polysilicon gate electrode.
  • the trench polysilicon gate electrode and the planar polysilicon gate electrode of the present invention share the same active region to form a three-dimensional channel surrounding the N++ region, which can increase the channel density of the IGBT chip, thereby improving the on-current capability of the IGBT chip. Reduce its conduction voltage drop.
  • the present invention provides a thick gate oxide layer in the non-channel region to form a planar polysilicon gate electrode with a step structure, which can reduce the output capacitance of the IGBT chip, thereby reducing the parasitic capacitance effect when the IGBT chip is switched.
  • the N++ doped region and the P++ doped region of the IGBT chip provided by the present invention are periodically arranged at intervals, which not only can fully utilize the channel area, but also reduce the parasitic resistance of the IGBT chip base region, thereby improving the resistance of the IGBT chip. Latching ability.
  • FIG. 1 is a cross-sectional view showing a half cell of an IGBT chip having a planar gate structure in the prior art
  • FIG. 2 is a cross-sectional view showing a half cell of an IGBT chip having a trench polysilicon gate electrode structure in the prior art
  • FIG. 3 is a cross-sectional view showing a half cell of an IGBT chip having a cascode and a trench polysilicon gate electrode structure in the prior art
  • FIG. 4 is a schematic structural view showing a composite gate IGBT chip having a three-dimensional channel in a first embodiment of the present invention
  • Fig. 5 is a view showing the structure of a composite gate IGBT chip having a three-dimensional channel in a second embodiment of the present invention.
  • the composite gate IGBT chip of this embodiment includes a plurality of cells.
  • a structural schematic diagram of a single strip cell shown in FIG. 4 will be described in detail below as an example.
  • FIG. 4 is a schematic structural view of a composite gate IGBT chip having a three-dimensional channel in a first embodiment of the present invention.
  • a substrate 1 a cell disposed on the substrate 1, and an N-type buffer layer 2, a P-type layer 3, and an anode metal layer 4 disposed under the substrate 1 are included.
  • the cell mainly comprises: a trench polysilicon gate electrode 5, a first oxide layer 6, two P well regions 7, two doped regions (the doped region includes an N++ doped region 8 and a P++ doped region 9), Two second oxide layers 10, two planar polysilicon gate electrodes 11, two third oxide layers 12, a passivation layer 13, and a cathode metal layer 14.
  • the trench polysilicon gate electrode 5 is disposed in the trench of the intermediate region of the cell, and the first oxide layer 2 surrounds the trench polysilicon gate electrode 5.
  • the trench is formed by etching down in the middle region of the cell, the gate oxide layer is disposed on the inner surface of the trench, and the trench provided with the gate oxide layer is filled with polysilicon to form the trench polysilicon gate electrode 5, the trench
  • the upper surface of the polysilicon gate electrode 5 covers the gate oxide layer.
  • the gate oxide layer surrounding the trench polysilicon gate electrode 5 is the first oxide layer 2.
  • the two P well regions 7 are formed by injecting P-type impurities into the cells on both side regions of the trench, and the junction depth of the P well region 7 is smaller than the depth of the trench.
  • the P-type impurity may be a boron impurity.
  • the two doped regions are formed by implanting impurities into the two P well regions 7 on both sides of the trench, wherein the width of the doped region is smaller than the width of the P well region 7, and the junction depth of the doped region is less than P The junction depth of the well region 7.
  • the doped region includes an N++ doped region 8 doped with an N-type impurity and a P++ doped region 9 doped with a P-type impurity.
  • the N-type impurity may be a phosphorus impurity
  • the P-type impurity may be a boron impurity.
  • the doped region includes a plurality of N++ doped regions 8 and P++ doped regions 9, and the N++ doped regions 8 and the P++ doped regions 9 are periodically spaced along the direction of the cell surface. .
  • a plurality of N++ doped regions 8 and P++ doped regions 9 may be separately formed through a mask, and the N++ doped regions 8 and the P++ doped regions 9 are arranged side by side in parallel. In the three-dimensional coordinate system of xyz shown in FIG.
  • the direction in which the groove extends along the surface of the cell is the z-axis
  • the N++ doped region 8 and the P++ doped region 9 extend in the direction in which the groove extends along the surface of the cell (ie, The z-axis direction is periodically spaced to ensure that the source N++ doped region 8 and the P++ doped region 9 are sufficiently short-circuited, thereby ensuring sufficient channel density and improving the latch-up resistance of the IGBT chip.
  • the two second oxide layers 10 cover the surface of the substrate 1 at the side regions of the two P well regions 7, the surface of the P well region 1 where the doped regions are not provided, and the partially doped regions.
  • Two planar polysilicon gate electrodes 11 are respectively located on the two second oxide layers 10.
  • the two third oxide layers 12 cover the two planar polysilicon gate electrodes 11, respectively.
  • the planar polysilicon gate electrode 11 is formed using polysilicon.
  • the second oxide layer 10 includes a first oxidation region adjacent to the doped region, a second oxidation region away from the doped region, and a third layer that smoothly connects the first oxidation region and the second oxidation region.
  • the oxidized region, the first oxidized region covers at least a surface of the P well region 7 where the doped region is not disposed, and a partially doped region, and the thickness of the second oxidized region is greater than the thickness of the first oxidized region.
  • the two planar polysilicon gate electrodes 11 are uniformly disposed to form a planar polysilicon gate electrode 11 having a stepped structure.
  • the first oxidation region near the doped region herein means that the distance between the first oxidation region and the doped region is less than a first predetermined threshold, “the second oxidation away from the doped region”.
  • the “region” means that the distance between the second oxidation zone and the doped region is greater than a second predetermined threshold, and the second predetermined threshold is greater than the first predetermined threshold.
  • the first preset threshold and the second preset threshold may be determined according to actual product requirements.
  • the thickness of the portion of the first oxide layer 6 in the channel region is greater than or equal to the thickness of the portion of the second oxide layer 10 that is in the channel region.
  • the thickness of the portion of the first oxide layer 6 at the channel region is in the range of 1 to 3 times the thickness of the portion of the second oxide layer 10 at the channel region. The Miller capacitance can be lowered to increase the reverse breakdown voltage.
  • the IGBT chip can be formed under the planar polysilicon gate electrode and the trench polysilicon gate electrode sidewall simultaneously, forming a channel.
  • the starting point of the channel controlled by the planar polysilicon gate electrode 11 is located at the laterally outermost side of the N++ doping region 8, and the end point of the channel controlled by the planar polysilicon gate electrode 11 is located at the lateral maximum of the P well region 7. Outside.
  • the start of the channel controlled by the trench polysilicon gate electrode 5 is located on the lower surface of the N++ doped region 8, and the end of the channel controlled by the trench polysilicon gate electrode 5 is located on the lower surface of the P well region 7.
  • the planar polysilicon gate electrode 11 can be electrically connected to the trench polysilicon gate electrode 5 to form a common composite gate electrode.
  • the planar polysilicon gate electrode 11 and the trench polysilicon gate electrode 5 may be electrically connected through an external gate trace.
  • the planar polysilicon gate electrode 11 and the trench polysilicon gate electrode 5 are synchronously controlled, that is, simultaneously turned on and turned off simultaneously. It should be noted that as long as the threshold voltage controlled by the planar polysilicon gate electrode 11 and the channel controlled by the trench polysilicon gate electrode 5 are in a relatively close range, simultaneous opening and simultaneous shutdown of the two channels can be realized. .
  • the planar polysilicon gate electrode 11 may not be electrically connected to the trench polysilicon gate electrode 5, and the IGBT chip is commonly controlled as two independent gate electrodes.
  • the planar polysilicon gate electrode 11 is used as the main control gate, and the trench polysilicon gate electrode 5 is used as the auxiliary control gate.
  • the trench polysilicon gate electrode 5 can be delayed after the planar polysilicon gate electrode 11 is turned on for a while, and the planar polysilicon gate electrode 11 is turned off for a while.
  • the channel controlled by the trench polysilicon gate electrode 5 can inject electrons when the IGBT chip is turned on, enhance the conductance modulation effect of the IGBT chip, and reduce the conduction voltage drop of the IGBT chip.
  • the channel controlled by the trench polysilicon gate electrode 5 is pinched off before the IGBT chip is turned off, the electron injection is reduced, and the unbalanced carrier concentration in the IGBT chip body is lowered in advance, thereby shortening the turn-off of the IGBT chip, thereby reducing the turn-off of the IGBT chip. Time and power down.
  • the trench polysilicon gate electrode 5 is used as the main control gate
  • the planar polysilicon gate electrode 11 is used as the auxiliary control gate.
  • the planar polysilicon gate electrode 11 can be delayed after the trench polysilicon gate electrode 5 is turned on for a while, and the trench polysilicon gate electrode 5 is turned off for a while.
  • the channel controlled by the planar polysilicon gate electrode 11 can inject electrons when the IGBT chip is turned on, enhance the conductance modulation effect of the IGBT chip, and reduce the conduction voltage drop of the IGBT chip.
  • the channel controlled by the planar polysilicon gate electrode 11 is pinched off before the IGBT chip is turned off, the electron injection is reduced, and the unbalanced carrier concentration in the IGBT chip body is lowered in advance, thereby shortening the turn-off of the IGBT chip, thereby reducing the turn-off time of the IGBT chip. And turn off power consumption.
  • the passivation layer 13 covers the two third oxide layers 12, respectively, and the cathode metal layer 14 is located on the passivation layer 13 and the region of the doped region that does not cover the third oxide layer 12.
  • the thickness of the third oxide layer 12 is uniformly set, and the thickness of the passivation layer 13 is uniformly set.
  • the N-type buffer layer 2 is located on the lower surface of the substrate 1
  • the P-type layer 3 is located on the lower surface of the N-type buffer layer 2
  • the anode metal layer 4 is located on the lower surface of the P-type layer 3.
  • the cell in this embodiment adopts a strip cell structure.
  • the square cell structure and the hexagonal cell structure can also be realized by adjusting the P well region 7 and the source region layout.
  • the composite gate IGBT chip with three-dimensional channel provided by the invention has both a surface channel controlled by a planar polysilicon gate electrode and a body channel controlled by a trench gate, and constitutes an N++ doped region.
  • the three-dimensional channel greatly increases the channel density of the IGBT chip, thereby increasing the current density of the IGBT chip.
  • a thick gate oxide layer is disposed in the non-channel region, and a planar polysilicon gate electrode is formed in the step structure, which can reduce the output capacitance of the IGBT chip, thereby reducing Parasitic capacitance effect when IGBT chip is switched.
  • the N++ doped region and the P++ doped region in the composite gate IGBT chip with three-dimensional channel provided by the invention are periodically arranged, which not only can fully utilize the channel area, but also reduce the parasitic resistance of the IGBT chip base region. , thereby improving the latch-up resistance of the IGBT chip.
  • This embodiment is a further optimization of the first embodiment.
  • FIG. 5 is a schematic structural view of a composite gate IGBT chip having a three-dimensional channel in a second embodiment of the present invention.
  • the N well region 15 is added to the cells shown in FIG.
  • the N well region 15 is located below the P well region 7 and is in contact with the lower surface and side portions of the P well region 7, and the width of the N well region 15 is larger than the width of the P well region 7.
  • an N-well region is added at the periphery of the P-well region to further increase the conductance modulation effect of the IGBT chip in the drift region.

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Abstract

一种具有三维沟道的复合栅IGBT芯片，包括沟槽多晶硅栅电极；第一氧化层；P阱区；包括N++掺杂区和P++掺杂区的掺杂区域；用以覆盖P阱区两侧区域的表面、P阱区未设置掺杂区域的表面和部分掺杂区域的第二氧化层；平面多晶硅栅电极；第三氧化层，可提升IGBT芯片的电流密度，以降低其导通压降。

Description

一种具有三维沟道的复合栅IGBT芯片
本申请要求享有2018年02月13日提交的名称为“一种具有三维沟道的复合栅IGBT芯片”的中国专利申请CN201810148909.X的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及半导体器件技术领域，尤其涉及一种具有三维沟道的复合栅IGBT芯片。
背景技术
自1980年前后IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)器件问世以来，由于其既具有双极晶体管通态压降低、电流密度大的特点，又具有MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物半导体场效应晶体管)管输入阻抗高、响应速度快等特点，被广泛应用于轨道交通、智能电网、工业变频及新能源开发等领域。
图1为现有技术中的具有平面栅结构的IGBT芯片的半元胞的剖面示意图。如图1所示，主要包括：衬底101、N阱区102、P阱区103、N+掺杂区104、P+掺杂区105、平面栅极106、栅氧化层107、钝化层108以及金属层109。图1所示的具有平面栅结构的IGBT芯片的主要优点是工艺制作简单，对设备要求低，而且平面栅耐压性能好，皮实度高，因而能用于工作环境比较恶劣的场所。但是，由于其沟道区在表面，沟道密度受到芯片表面积大小限制，导致IGBT芯片体内的电导调制效应较弱，导通压降较高。
图2为现有技术中的具有沟槽栅结构的IGBT芯片的半元胞的剖面示意图。如图2所示，主要包括：衬底201、N阱区202、P阱区203、N+掺杂区204、P+掺杂区205、沟槽栅极206、栅氧化层207、钝化层208以及金属层209。为了降低IGBT芯片的导通压降，采用如图2所示的沟槽栅结构取代平面栅结构。如图2所示，通过刻蚀工艺形成沟槽栅极，使得沟道进入衬底体内，实现将沟道由横向转化为纵向，从而实现一维电流通道，有效消除平面栅沟道中的JFET效应，同时缩小了元胞尺寸，使沟道密度不再受芯片表面积限制，大大提高元胞密度从而大幅度提升芯片电流密度。但是，随着沟槽栅密度的增加，芯片饱和电流过大，弱化了芯片的短路性能，从而影响了芯片的安全工作区。
图3为现有技术中的具有陪栅和沟槽栅结构的IGBT芯片的半元胞的剖面示意图。如图3所示，主要包括：衬底301、N阱区302、P阱区303、N+掺杂区304、P+掺杂区305、沟槽栅极306、陪栅307、栅氧化层308、钝化层309以及金属层310。为了平衡短路性能和电流密度之间的折中关系，采用如图3所示的陪栅和沟槽栅极共存的结构取代如图2所示的沟槽栅结构。
图2和图3中的沟槽栅极的底部对IGBT芯片的阻压能力有一定的限制。其与图1所示的具有平面栅结构的IGBT芯片相比，在提升IGBT芯片性能的同时也牺牲了平面栅部分耐压和皮实的性能。
发明内容
针对上述技术问题，本发明提供了一种具有三维沟道的复合栅IGBT芯片，包括多个元胞，所述元胞包括：
在所述元胞的中间区域向下刻蚀而成的沟槽，所述沟槽内设置多晶硅形成沟槽多晶硅栅电极；
包围所述沟槽多晶硅栅电极的第一氧化层；
通过向所述元胞在所述沟槽的两侧区域注入P型杂质而形成的两个P阱区，其中所述P阱区的结深小于所述沟槽的深度；
通过向所述两个P阱区在所述沟槽的两侧区域分别注入杂质而形成的两个掺杂区域，其中所述掺杂区域的宽度小于所述P阱区的宽度，所述掺杂区域包括邻接的掺杂N型杂质的N++掺杂区和掺杂P型杂质的P++掺杂区；
覆盖所述两个P阱区的两侧区域的表面、所述P阱区未设置所述掺杂区域的表面和部分所述掺杂区域的两个第二氧化层；
在所述两个第二氧化层上分别设置多晶硅形成的两个平面多晶硅栅电极；
分别覆盖两个所述平面多晶硅栅电极的两个第三氧化层。
在一个实施例中，所述元胞还包括位于所述P阱区下方且与所述P阱区的下表面和侧部接触的N阱区，所述N阱区的宽度大于所述P阱区的宽度。
在一个实施例中，所述第二氧化层包括靠近所述掺杂区域的第一氧化区、背离所述掺杂区域的第二氧化区以及平滑连接所述第一氧化区和第二氧化区的第三氧化区，所述第一氧化区至少覆盖所述P阱区未设置所述掺杂区域的表面和部分所述掺杂区域，所述第二 氧化区的厚度大于所述第一氧化区的厚度；
所述平面多晶硅栅电极厚度均匀设置。
在一个实施例中，多个所述N++掺杂区和P++掺杂区在所述沟槽沿所述元胞表面延伸的方向上周期性间隔排布。
在一个实施例中，所述平面多晶硅栅电极不与所述沟槽多晶硅栅电极电性连接。
在一个实施例中，所述平面多晶硅栅电极与所述沟槽多晶硅栅电极通过外部栅极走线电性连接。
在一个实施例中，所述元胞还包括：
分别覆盖两个所述第三氧化层的两个钝化层；
在所述两个钝化层和所述掺杂区域中未覆盖所述第三氧化层和钝化层的区域上形成的金属层。
在一个实施例中，所述第三氧化层厚度均匀设置，所述钝化层厚度均匀设置。
在一个实施例中，所述掺杂区域的结深小于所述P阱区的结深。
在一个实施例中，所述元胞为条形元胞结构、方形元胞结构或者六角形元胞结构。
在一个实施例中，所述第一氧化层中处于沟道区的部分的厚度大于等于所述第二氧化层中处于沟道区的部分的厚度。
在一个实施例中，所述第一氧化层中处于沟道区的部分的厚度大于等于所述第二氧化层中处于沟道区的部分的厚度。
与现有技术相比，本发明的一个或多个实施例可以具有如下优点：
1)本发明提供的IGBT芯片具有平面多晶硅栅电极和沟槽多晶硅栅电极的复合栅结构，既利用了沟槽多晶硅栅电极体内沟道和沟道密度高的特点，又利用了平面多晶硅栅电极寄生电容小的特点，从而大幅度提升IGBT芯片密度，并保留沟槽多晶硅栅电极低通耗、高电流密度和平面多晶硅栅电极宽安全工作区的特性。
2)本发明的沟槽多晶硅栅电极和平面多晶硅栅电极共用同一有源区，形成围绕N++区的三维沟道，可以提升IGBT芯片的沟道密度，从而提升IGBT芯片的导通电流能力，以降低其导通压降。
3)本发明在非沟道区域设置较厚的栅氧化层，形成台阶结构的平面多晶硅栅电极， 可以降低IGBT芯片的输出电容，从而减小IGBT芯片开关时的寄生电容效应。
4)本发明提供的IGBT芯片中N++掺杂区和P++掺杂区周期性间隔排布，不仅可以充分利用沟道面积，还降低了IGBT芯片基区的寄生电阻，从而提高了IGBT芯片的抗闩锁能力。
本发明的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1示出了现有技术中的具有平面栅结构的IGBT芯片的半元胞的剖面示意图；
图2示出了现有技术中的具有沟槽多晶硅栅电极结构的IGBT芯片的半元胞的剖面示意图；
图3示出了现有技术中的具有陪栅和沟槽多晶硅栅电极结构的IGBT芯片的半元胞的剖面示意图；
图4示出了本发明第一实施例中的具有三维沟道的复合栅IGBT芯片的结构示意图；
图5示出了本发明第二实施例中的具有三维沟道的复合栅IGBT芯片的结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
第一实施例
本实施例的复合栅IGBT芯片包括多个元胞。为了更清楚地说明本实施例的复合栅IGBT芯片，下面以图4所示的单个条形元胞的结构示意图为例进行详细说明。
图4为本发明第一实施例中的具有三维沟道的复合栅IGBT芯片的结构示意图。如图4所示，包括衬底1、设置于衬底1上的元胞以及设置于衬底1下方的N型缓冲层2、P 型层3和阳极金属层4。其中，元胞主要包括：沟槽多晶硅栅电极5、第一氧化层6、两个P阱区7、两个掺杂区域(掺杂区域包括N++掺杂区8和P++掺杂区9)、两个第二氧化层10、两个平面多晶硅栅电极11、两个第三氧化层12、钝化层13和阴极金属层14。
具体地，沟槽多晶硅栅电极5设置于元胞中间区域的沟槽内，第一氧化层2包围沟槽多晶硅栅电极5。其中，沟槽是在元胞的中间区域向下刻蚀形成的，沟槽内表面设置栅氧化层，设置有栅氧化层的沟槽内填充有多晶硅，形成沟槽多晶硅栅电极5，沟槽多晶硅栅电极5的上表面覆盖栅氧化层。该处包围沟槽多晶硅栅电极5的栅氧化层即为第一氧化层2。
两个P阱区7是通过向元胞在沟槽的两侧区域注入P型杂质而形成的，P阱区7的结深小于沟槽的深度。在本实施例中，P型杂质可以为硼杂质。
两个掺杂区域是通过向两个P阱区7在沟槽的两侧区域分别注入杂质而形成的，其中掺杂区域的宽度小于P阱区7的宽度，掺杂区域的结深小于P阱区7的结深。掺杂区域包括掺杂N型杂质的N++掺杂区8和掺杂P型杂质的P++掺杂区9。在本实施例中，N型杂质可以为磷杂质，P型杂质可以为硼杂质。
在本发明一优选的实施例中，掺杂区域包括多个N++掺杂区8和P++掺杂区9，N++掺杂区8和P++掺杂区9沿元胞表面的方向周期性间隔排布。具体地，可以通过掩膜分别形成多个N++掺杂区8和P++掺杂区9，N++掺杂区8和P++掺杂区9平行并排设置。如图4所示的xyz的三维坐标系中，设沟槽沿元胞表面延伸的方向为z轴，N++掺杂区8和P++掺杂区9在沟槽沿元胞表面延伸的方向(即z轴方向)上周期性间隔排布，可以保证源极N++掺杂区8和P++掺杂区9充分短路，从而可以保证足够的沟道密度，同时提升IGBT芯片的抗闩锁能力。
两个第二氧化层10覆盖衬底1在两个P阱区7的两侧区域的表面、P阱区1未设置掺杂区域的表面和部分掺杂区域。两个平面多晶硅栅电极11分别位于两个第二氧化层10上。两个第三氧化层12分别覆盖两个平面多晶硅栅电极11。在本实施例中，平面多晶硅栅电极11采用多晶硅形成。
在本发明一优选的实施例中，第二氧化层10包括靠近掺杂区域的第一氧化区、背离掺杂区域的第二氧化区以及平滑连接第一氧化区和第二氧化区的第三氧化区，第一氧化区至少覆盖P阱区7未设置掺杂区域的表面和部分掺杂区域，第二氧化区的厚度大于第一氧化区的厚度。两个平面多晶硅栅电极11厚度均匀设置，形成台阶结构的平面多晶硅栅电极11。由于在非沟道区域设置较厚的栅氧化层，形成台阶结构的平面多晶硅栅电极， 可以降低IGBT芯片的输出电容，从而减小IGBT芯片开关时的寄生电容效应。需要说明的是，此处“靠近掺杂区域的第一氧化区”指的是的第一氧化区与掺杂区域之间的距离小于第一预设阈值，“背离掺杂区域的第二氧化区”指的是第二氧化区与掺杂区域之间的距离大于第二预设阈值，第二预设阈值大于第一预设阈值。第一预设阈值和第二预设阈值可根据实际产品需求而定。
在本发明一优选的实施例中，第一氧化层6中处于沟道区的部分的厚度大于等于第二氧化层10中处于沟道区的部分的厚度。具体地，第一氧化层6中处于沟道区的部分的厚度处于第二氧化层10中处于沟道区的部分的厚度的1倍至3倍的范围内。可以降低米勒电容，提高反向击穿电压。
特别地，通过合理地控制P阱区7和N++掺杂区8的注入剂量和扩散结深，可以实现该IGBT芯片在平面多晶硅栅电极下方和沟槽多晶硅栅电极侧壁同时形成沟道，构成围绕N++掺杂区8的三维沟道。具体地，如图4所示，平面多晶硅栅电极11控制的沟道的起点位于N++掺杂区8的横向最外侧，平面多晶硅栅电极11控制的沟道的终点位于P阱区7的横向最外侧。沟槽多晶硅栅电极5控制的沟道的起点位于N++掺杂区8的下表面，沟槽多晶硅栅电极5控制的沟道的终点位于P阱区7的下表面。
在本发明一优选的实施例中，平面多晶硅栅电极11可以和沟槽多晶硅栅电极5电性连接形成共同的复合栅电极。具体地，平面多晶硅栅电极11与沟槽多晶硅栅电极5可以通过外部栅极走线电性连接。平面多晶硅栅电极11与沟槽多晶硅栅电极5采取同步控制，即同时开启同时关断。需要注意的是，只要平面多晶硅栅电极11控制的沟道和沟槽多晶硅栅电极5控制的沟道的阈值电压处在比较接近的范围，就可以实现两处沟道的同时开启和同时关断。
在本发明一优选的实施例中，平面多晶硅栅电极11还可以不与沟槽多晶硅栅电极5电性连接，分别作为两个独立的栅电极共同控制该IGBT芯片。在本实施例中，以平面多晶硅栅电极11作为主控栅，以沟槽多晶硅栅电极5作为辅助控制栅。沟槽多晶硅栅电极5可以延迟于平面多晶硅栅电极11一段时间后开启，提前平面多晶硅栅电极11一段时间关断。在此过程中，沟槽多晶硅栅电极5控制的沟道可以在IGBT芯片开启时注入电子，增强IGBT芯片的电导调制效应，降低IGBT芯片的导通压降。沟槽多晶硅栅电极5控制的沟道在IGBT芯片关断前夹断，减小电子注入，提前降低IGBT芯片体内非平衡载流子浓度，从而加快IGBT芯片关断，进而减少IGBT芯片的关断时间和关断功耗。
或者，以沟槽多晶硅栅电极5作为主控栅，以平面多晶硅栅电极11作为辅助控制栅。 平面多晶硅栅电极11可以延迟于沟槽多晶硅栅电极5一段时间后开启，提前沟槽多晶硅栅电极5一段时间关断。在此过程中，平面多晶硅栅电极11控制的沟道可以在IGBT芯片开启时注入电子，增强IGBT芯片的电导调制效应，降低IGBT芯片的导通压降。平面多晶硅栅电极11控制的沟道在IGBT芯片关断前夹断，减小电子注入，提前降低IGBT芯片体内非平衡载流子浓度，从而加快IGBT芯片关断，进而减少IGBT芯片的关断时间和关断功耗。
钝化层13分别覆盖两个第三氧化层12，阴极金属层14位于钝化层13和掺杂区域中未覆盖第三氧化层12的区域上。在本发明一优选的实施例中，第三氧化层12厚度均匀设置，钝化层13厚度均匀设置。
N型缓冲层2位于衬底1的下表面，P型层3位于N型缓冲层2的下表面，阳极金属层4位于P型层3的下表面。
本实施例中的元胞采用条形元胞结构。当然，也可以通过调整P阱区7和源区版图实现方形元胞结构以及六角形元胞结构。
综上所述，第一，本发明提供的具有三维沟道的复合栅IGBT芯片既具备平面多晶硅栅电极控制的表面沟道也具备沟槽栅控制的体内沟道，构成了围绕N++掺杂区的三维沟道，极大地增大了IGBT芯片的沟道密度，从而提升了IGBT芯片的电流密度。第二，本发明提供的具有三维沟道的复合栅IGBT芯片中在非沟道区域设置较厚的栅氧化层，形成台阶结构的平面多晶硅栅电极，可以降低IGBT芯片的输出电容，从而减小IGBT芯片开关时的寄生电容效应。第三，本发明提供的具有三维沟道的复合栅IGBT芯片中N++掺杂区和P++掺杂区周期性间隔排布，不仅可以充分利用沟道面积，还降低了IGBT芯片基区的寄生电阻，从而提高了IGBT芯片的抗闩锁能力。
第二实施例
本实施例是对第一实施例的进一步优化。
图5为本发明第二实施例中的具有三维沟道的复合栅IGBT芯片的结构示意图。如图5所示，在图4所示的元胞中增加N阱区15。N阱区15位于P阱区7下方且与P阱区7的下表面和侧部接触，N阱区15的宽度大于P阱区7的宽度。
在本实施例中，在P阱区的外围增加了N阱区，进一步增加IGBT芯片在漂移区的电导调制效应。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种具有三维沟道的复合栅IGBT芯片，包括多个元胞，所述元胞包括：
    在所述元胞的中间区域向下刻蚀而成的沟槽，所述沟槽内设置多晶硅形成沟槽多晶硅栅电极；
    包围所述沟槽多晶硅栅电极的第一氧化层；
    通过向所述元胞在所述沟槽的两侧区域注入P型杂质而形成的两个P阱区，其中所述P阱区的结深小于所述沟槽的深度；
    通过向所述两个P阱区在所述沟槽的两侧区域分别注入杂质而形成的两个掺杂区域，其中所述掺杂区域的宽度小于所述P阱区的宽度，所述掺杂区域包括邻接的掺杂N型杂质的N++掺杂区和掺杂P型杂质的P++掺杂区；
    覆盖所述两个P阱区的两侧区域的表面、所述P阱区未设置所述掺杂区域的表面和部分所述掺杂区域的两个第二氧化层；
    在所述两个第二氧化层上分别设置多晶硅形成的两个平面多晶硅栅电极；
    分别覆盖两个所述平面多晶硅栅电极的两个第三氧化层。
  2. 根据权利要求1所述的复合栅IGBT芯片，其中，所述元胞还包括位于所述P阱区下方且与所述P阱区的下表面和侧部接触的N阱区，所述N阱区的宽度大于所述P阱区的宽度。
  3. 根据权利要求1所述的复合栅IGBT芯片，其中：
    所述第二氧化层包括靠近所述掺杂区域的第一氧化区、背离所述掺杂区域的第二氧化区以及平滑连接所述第一氧化区和第二氧化区的第三氧化区，所述第一氧化区至少覆盖所述P阱区未设置所述掺杂区域的表面和部分所述掺杂区域，所述第二氧化区的厚度大于所述第一氧化区的厚度；
    所述平面多晶硅栅电极厚度均匀设置。
  4. 根据权利要求2所述的复合栅IGBT芯片，其中：
    所述第二氧化层包括靠近所述掺杂区域的第一氧化区、背离所述掺杂区域的第二氧化区以及平滑连接所述第一氧化区和第二氧化区的第三氧化区，所述第一氧化区至少覆盖所述P阱区未设置所述掺杂区域的表面和部分所述掺杂区域，所述第二氧化区的厚度大于所述第一氧化区的厚度；
    所述平面多晶硅栅电极厚度均匀设置。
  5. 根据权利要求1所述的复合栅IGBT芯片，其中，多个所述N++掺杂区和P++掺杂区在所述沟槽沿所述元胞表面延伸的方向上周期性间隔排布。
  6. 根据权利要求2所述的复合栅IGBT芯片，其中，多个所述N++掺杂区和P++掺杂区在所述沟槽沿所述元胞表面延伸的方向上周期性间隔排布。
  7. 根据权利要求1所述的复合栅IGBT芯片，其中，所述平面多晶硅栅电极不与所述沟槽多晶硅栅电极电性连接。
  8. 根据权利要求2所述的复合栅IGBT芯片，其中，所述平面多晶硅栅电极不与所述沟槽多晶硅栅电极电性连接。
  9. 根据权利要求1所述的复合栅IGBT芯片，其中，所述平面多晶硅栅电极与所述沟槽多晶硅栅电极通过外部栅极走线电性连接。
  10. 根据权利要求2所述的复合栅IGBT芯片，其中，所述平面多晶硅栅电极与所述沟槽多晶硅栅电极通过外部栅极走线电性连接。
  11. 根据权利要求3所述的复合栅IGBT芯片，其中，所述元胞还包括：
    分别覆盖两个所述第三氧化层的两个钝化层；
    在所述两个钝化层和所述掺杂区域中未覆盖所述第三氧化层和钝化层的区域上形成的金属层。
  12. 根据权利要求4所述的复合栅IGBT芯片，其中，所述元胞还包括：
    分别覆盖两个所述第三氧化层的两个钝化层；
    在所述两个钝化层和所述掺杂区域中未覆盖所述第三氧化层和钝化层的区域上形成的金属层。
  13. 根据权利要求1所述的复合栅IGBT芯片，其中，所述掺杂区域的结深小于所述P阱区的结深。
  14. 根据权利要求2所述的复合栅IGBT芯片，其中，所述掺杂区域的结深小于所述P阱区的结深。
  15. 根据权利要求1所述的复合栅IGBT芯片，其中，所述元胞为条形元胞结构、方形元胞结构或者六角形元胞结构。
  16. 根据权利要求2所述的复合栅IGBT芯片，其中，所述元胞为条形元胞结构、方形元胞结构或者六角形元胞结构。
  17. 根据权利要求1所述的复合栅IGBT芯片，其中，所述第一氧化层中处于沟道区的部分的厚度大于等于所述第二氧化层中处于沟道区的部分的厚度。
  18. 根据权利要求17所述的复合栅IGBT芯片，其中，所述第一氧化层中处于沟道区的部分的厚度处于所述第二氧化层中处于沟道区的部分的厚度的1倍至3倍的范围内。
  19. 根据权利要求2所述的复合栅IGBT芯片，其中，所述第一氧化层中处于沟道区的部分的厚度大于等于所述第二氧化层中处于沟道区的部分的厚度。
  20. 根据权利要求19所述的复合栅IGBT芯片，其中，所述第一氧化层中处于沟道区的部分的厚度处于所述第二氧化层中处于沟道区的部分的厚度的1倍至3倍的范围内。
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