CN107093625B - 双扩散漏nmos器件及制造方法 - Google Patents

双扩散漏nmos器件及制造方法 Download PDF

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CN107093625B
CN107093625B CN201710249497.4A CN201710249497A CN107093625B CN 107093625 B CN107093625 B CN 107093625B CN 201710249497 A CN201710249497 A CN 201710249497A CN 107093625 B CN107093625 B CN 107093625B
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段文婷
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors

Abstract

本发明公开了一种双扩散漏NMOS器件，在P型衬底上有N型埋层，N型埋层之上为N型外延；N型外延中有P阱及漂移区，两者之间为双扩散漏NMOS器件的沟道区，沟道区之上的硅表面为双扩散漏NMOS器件的栅氧化层及多晶硅栅极；P阱中具有中掺杂P型区及双扩散漏NMOS器件的源区，漂移区中具有双扩散漏NMOS器件的漏区；P阱及漂移区中，还分别具有一P型掺杂层，分别位于源区及漏区的正下方。P型掺杂层有助于漂移区耗尽，提高击穿电压；位于源区下方的P型掺杂层对器件影响很小，阈值电压几乎不变。同时，由于电流通路中的漂移区浓度没有降低，保证了器件的导通电阻不会增加。本发明所述的工艺方法在没有增加掩模版的情况下有效的提高了击穿电压，没有成本增加。

Description

双扩散漏NMOS器件及制造方法
技术领域
本发明涉及半导体领域，特别是指一种双扩散漏NMOS器件，本发明还涉及所述双扩散漏NMOS器件的制造方法。
背景技术
DDD MOS(Double Diffused Drain MOSFET)高压双扩散漏器件广泛的应用于电路输出接口、LCD驱动电路等，其工作电压在10～20V左右。DDD MOS容易与传统COMS工艺兼容，工艺较LD MOS简单，制造成本更低。
击穿电压作为衡量DDD MOS器件的关键参数而显得尤为重要。
原双扩散漏NMOS器件结构如图1所示，P型衬底1上为N型埋层2，其上再为N型外延3。漂移区4和P阱5位于外延3中。器件的漂移区浓度决定了器件的击穿电压和导通电阻。通常漂移区不能完全耗尽导致击穿电压较低，但若通过降低漂移区浓度提高击穿电压，导通电阻又会增大。因此通常两者不能兼顾，只能做取舍，取得一个较为平衡的值。
发明内容
本发明所要解决的技术问题是提供一种双扩散漏NMOS器件，具有较高的击穿电压的同时还具有较低的导通电阻。
本发明所要解决的另一技术问题在于提供所述双扩散漏NMOS器件的制造工艺方法。
为解决上述问题，本发明所述的双扩散漏NMOS器件在P型衬底上有N型埋层，N型埋层之上为N型外延；
N型外延中，具有P阱及漂移区，两者之间为双扩散漏NMOS器件的沟道区，沟道区之上的硅表面为双扩散漏NMOS器件的栅氧化层及多晶硅栅极；
所述P阱中具有中掺杂P型区及双扩散漏NMOS器件的源区，所述漂移区中具有双扩散漏NMOS器件的漏区；
所述P阱及漂移区中，还分别具有一P型掺杂层。
所述的P型掺杂层，分别位于源区及漏区的正下方。
所述的P型掺杂层辅助漂移区耗尽。
为解决上述问题，本发明所述的双扩散漏NMOS器件的工艺方法，包含如下的工艺步骤：
步骤1，在P型衬底上形成N型埋层；
步骤2，在N型埋层上形成N型外延；
步骤3，光刻定义出P阱及漂移区，离子注入形成P阱及漂移区；
步骤4，硅片表面形成栅氧化层及多晶硅，光刻及刻蚀形成多晶硅栅极；
步骤5，进行源漏注入形成器件的源区及漏区；再次利用源漏注入的掩膜版进行一次P型注入；
步骤6，进行P型杂质注入，形成P阱的重掺杂引出区。
进一步地，所述步骤4中，采用热氧化法生成栅氧化层。
进一步地，所述步骤5中，P型注入的杂质为硼，注入能量为100～300keV,注入剂量为1E12～1E14CM-2
本发明所述的双扩散漏NMOS器件，在源区及漏区的下方增加一个P型掺杂层，有助于漂移区耗尽，提高击穿电压；位于源区下方的P型掺杂层对器件影响很小，阈值电压几乎不变。同时，由于电流通路中的漂移区浓度没有降低，保证了器件的导通电阻不会增加。本发明所述的工艺方法在没有增加掩模版的情况下有效的提高了击穿电压，没有成本增加。
附图说明
图1是现有的双扩散漏NMOS结构示意图。
图2～7是本发明工艺方法步骤图。
图8是本发明工艺步骤流程图。
附图标记说明
1是衬底，2是N型埋层，3是N型外延，4是N型漂移区，5是P阱，6是栅氧化层，7是多晶硅栅极，8是重掺杂N型区(源、漏区)，9是P型掺杂区，10是重掺杂P型区。
具体实施方式
本发明所述的的双扩散漏NMOS器件如图6所示，在P型衬底1上有N型埋层2，N型埋层2之上为N型外延3；N型外延3中，具有P阱5及漂移区4，两者之间为双扩散漏NMOS器件的沟道区，沟道区之上的硅表面为双扩散漏NMOS器件的栅氧化层6及多晶硅栅极7。
所述P阱5中具有重掺杂P型区10及双扩散漏NMOS器件的源区8，所述漂移区4中具有双扩散漏NMOS器件的漏区8。
所述P阱5漂移区4中，还分别具有一P型掺杂层9，分别位于源区及漏区的正下方。
本发明所述的双扩散漏NMOS器件，在源区及漏区的下方增加一个P型掺杂层，有助于N型的漂移区4耗尽，提高击穿电压.而位于源区下方的P型掺杂层9对器件影响很小，阈值电压几乎不变。同时，由于电流通路中的漂移区浓度没有降低，保证了器件的导通电阻不会增加。
本发明所述的双扩散漏NMOS器件的工艺方法，包含如下的工艺步骤，各步骤分别对应图2至图7：
步骤1，在P型衬底1上形成N型埋层2；
步骤2，在N型埋层2上形成N型外延3；
步骤3，光刻定义出P阱及漂移区，离子注入形成P阱5及漂移区4；
步骤4，硅片表面采用热氧化法形成栅氧化层6及多晶硅，光刻及刻蚀形成多晶硅栅极7；
步骤5，进行N型杂质注入形成重掺杂N型区8作为器件的源区及漏区；再次利用源漏注入的掩膜版进行一次P型注入；P型注入的杂质为硼，注入能量为100～300keV,注入剂量为1E12～1E14CM-2。
步骤6，进行P型杂质注入，形成P阱的重掺杂引出区10。器件制作完成，如图7所示。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (3)

1.一种双扩散漏NMOS器件的工艺方法，其特征在于：包含如下的工艺步骤：
步骤1，在P型衬底上形成N型埋层；
步骤2，在N型埋层上形成N型外延；
步骤3，光刻定义出P阱及漂移区，离子注入形成P阱及漂移区；
步骤4，硅片表面形成栅氧化层及多晶硅，光刻及刻蚀形成多晶硅栅极；
步骤5，进行源漏注入形成器件的源区及漏区；再次利用源漏注入的掩膜版进行一次P型注入形成P型掺杂层；所述P型掺杂层分别位于P阱及漂移区中，且分别位于源区、漏区的正下方，用于辅助漂移区耗尽；
步骤6，进行P型杂质注入，形成重掺杂P型区作为P阱的引出区。
2.如权利要求1所述的双扩散漏NMOS器件的工艺方法，其特征在于：所述步骤4中，采用热氧化法生成栅氧化层。
3.如权利要求1所述的双扩散漏NMOS器件的工艺方法，其特征在于：所述步骤5中，P型注入的杂质为硼，注入能量为100～300keV,注入剂量为1E12～1E14cm-2。
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