CN101969074B - 一种高压ldmos器件 - Google Patents

一种高压ldmos器件 Download PDF

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CN101969074B
CN101969074B CN201010523281.0A CN201010523281A CN101969074B CN 101969074 B CN101969074 B CN 101969074B CN 201010523281 A CN201010523281 A CN 201010523281A CN 101969074 B CN101969074 B CN 101969074B
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ldmos device
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CN101969074A (zh
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方健
陈吕赟
李文昌
管超
吴琼乐
柏文斌
王泽华
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University of Electronic Science and Technology of China
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular

Abstract

本发明涉及一种高压LDMOS器件，包括衬底、位于衬底之上的外延层，位于外延层之上的漂移区，位于LDMOS器件两端的漏区和源区，其特征在于，在衬底和外延层的交界面上紧贴漂移区的下表面具有交替排列的至少一对n型半导体区和p型半导体区，所述n型半导体区和p型半导体区紧贴排列相互形成横向的PN结，同时p型半导体区与漂移区形成纵向的PN结。本发明的有益效果是：本发明中的n型半导体区和p型半导体区也被合称为体内降低表面电场(RESURF)层，这种具有体内降低表面电场层的LDMOS器件有效的解决了现有的LDMOS器件提高反向耐压和降低正向导通电阻的矛盾。

Description

一种高压LDMOS器件
技术领域
本发明涉及电子技术领域内的半导体高压低阻器件，尤其涉及在体硅上制造的高压功率器件。
背景技术
随着半导体行业的迅猛发展，PIC(Power Integrated Circuit，功率集成电路)不断在多个领域中使用，如电机控制、平板显示驱动控制、电脑外设的驱动控制等等，PIC电路中所使用的功率器件中，LDMOS(Lateral DoubleDiffused MOSFET，横向双扩散金属氧化物半导体场效应管)高压器件具有工作电压高、工艺简单、易于同低压CMOS(Complementary Metal OxideSemiconductor，互补金属氧化物半导体)电路在工艺上兼容等特点而受到广泛关注。但是对于用Si(硅)材料制成的半导体高压功率器件，LDMOS器件的正向导通电阻相比于VDMOS(Vertical Double Diffused MOSFET，垂直双扩散金属氧化物半导体场效应晶体管)的大，而较大的正向导通电阻导致了器件尺寸的增大，从而增加了制造成本。图1是常规LDMOS器件结构示意图，图中，LDMOS器件包括衬底1、外延层2、漂移区3、漏区4、阱区5、源区6、氧化层7、源极8、栅极9、漏极10、衬底电极15。当LDMOS器件为n型时，衬底1、阱区5为p型，外延层2为n型，漂移区3为n-型，漏区4、源区6为n+型；反之，当LDMOS器件为p型时，衬底1、阱区5为n型，外延层2为p型，漂移区3为p-型，漏区4、源区6为p+型。该LDMOS器件中用于承担耐压的漂移区3需要用低浓度掺杂，但另一方面，要降低LDMOS器件正向导通时的导通电阻，又要求作为电流通道的漂移区3具有高掺杂浓度，这就形成了击穿电压BV与导通电阻Ron之间的矛盾。以常见MOS(Metal-Oxide-Semiconductor，金属-氧化物-半导体)器件为例，其具体关系式如下：
R on = L D qμ n N D = 5.39 × 10 - 9 ( BV ) 2.5 (对于N型MOS)
R on = L D qμ p N D = 1.63 × 10 - 8 ( BV ) 2.5 (对于P型MOS)
其中，LD是漂移区长度，ND为漂移区浓度，μn和μp分别为电子和空穴的迁移率，q为电子电量。由此可见，MOS器件的导通电阻与漂移区长度成正比，与其浓度成反比。长度越短，浓度越高，则导通电阻越小，由于LDMOS器件是MOS器件中的一种，因此LDMOS器件具有MOS器件的通用特性。因此为了保证一定的耐压，LDMOS器件的漂移区3的长度不能做得太短；其浓度也不能做得太高，否则会在栅极9下阱区5的PN结附近发生击穿，使LDMOS器件的反向耐压降低。
发明内容
本发明的目的是为了解决现有的LDMOS器件提高反向耐压和降低正向导通电阻的矛盾，提供了一种高压LDMOS器件。
为了实现上述目的，本发明的技术方案是一种高压LDMOS器件，包括衬底、位于衬底之上的外延层，位于外延层之上的漂移区，位于LDMOS器件两端的漏区和源区，其特征在于，在衬底和外延层的交界面上紧贴漂移区的下表面具有交替排列的至少一对n型半导体区和p型半导体区，所述n型半导体区和p型半导体区紧贴排列相互形成横向的PN结，同时p型半导体区与漂移区形成纵向的PN结。
为了防止n型半导体区和p型半导体区形成的PN结影响漏区的电场，在漂移区对应于漏区的部分向下扩展迈过衬底和外延层的交界面。
为了调节LDMOS器件反向耐压时n型半导体区和p型半导体区与漂移区的电荷平衡，在n型半导体区和p型半导体区与漂移区的交界面上添加埋层，所述埋层的掺杂特性与漂移区相反。
为了进一步调节LDMOS器件反向耐压时n型半导体区和p型半导体区与漂移区的电荷平衡，在漂移区的上表面添加顶埋层(top)，所述顶埋层的掺杂特性与漂移区相反。
本发明的有益效果是：本发明中的n型半导体区11和p型半导体区12也被合称为体内降低表面电场(RESURF)层，这种具有体内降低表面电场层的LDMOS器件有效的解决了现有的LDMOS器件提高反向耐压和降低正向导通电阻的矛盾，从而在相同反向耐压的情况下可以有效降低正向导通电阻，或者在相同正向导通电阻的情况下可以有效提高反向耐压。本发明中的体内降低表面电场层的结构不仅可以应用于横向双扩散场效应晶体管(LDMOS)，还可以扩展到横向绝缘栅双极型功率晶体管(LIGBT)、静电诱导晶体管(SIT)、横向晶闸管、PN二极管等常见功率器件中。随着半导体器件技术的发展，采用本发明还可以制作更多的高压、低导通电阻功率器件。
附图说明
图1是常规的LDMOS器件结构示意图。
图2是本发明实施例一的LDMOS器件结构示意图。
图3是本发明实施例二的LDMOS器件结构示意图。
图4是本发明实施例三的LDMOS器件结构示意图。
图5是本发明实施例四的LDMOS器件结构示意图。
附图标记说明：衬底1、外延层2、漂移区3、漏区4、阱区5、源区6、氧化层7、源极8、栅极9、漏极10、n型半导体区11、p型半导体区12、埋层13、顶埋层14、衬底电极15。
具体实施方式
下面结合附图和具体实施例对本发明做进一步的说明。
实施例一：如图2所示，LDMOS器件包括衬底1、外延层2、漂移区3、漏区4、阱区5、源区6、氧化层7、源极8、栅极9、漏极10和衬底电极15，本实施例中LDMOS器件为n型，所以衬底1、阱区5为p型，外延层2为n型，漂移区3为n-型，漏区4、源区6为n+型，外延层2位于衬底1之上，漂移区3位于外延层2之上，漏区4和源区6位于LDMOS器件两端，在衬底1和外延层2的交界面上紧贴漂移区3的下表面具有交替排列的四对n型半导体区11和p型半导体区12，n型半导体区11和p型半导体区12紧贴排列相互形成横向的PN结，同时p型半导体区12与漂移区3形成纵向的PN结。
本实施例中n型半导体区11和p型半导体区12可以根据需要任意设定对数、形状、大小和掺杂浓度，实施例中的具体对数、形状、大小不能被理解为对本发明的限定。
以本实施例为例说明本发明的工作原理：
首先，本实施例中的n型半导体区11和p型半导体区12也被合称为体内降低表面电场(RESURF)层，LDMOS器件正向导通时，与漂移区3掺杂特性相同的降低表面电场层的半导体区构成一个与漂移区3并联的等效电阻，因此可以有效降低LDMOS器件整体的导通电阻，从而达到降低导通损耗的目的。如公式：Ron＝Rcontact+Rsource+Rchannel+Rdrain+RdriftRresurf/(Rdrift+Rresurf)所示，式中，Ron为导通电阻，Rcontact是接触电阻，Rsource是源电阻，Rchannel是沟道电阻，Rdrift＝ρd·Ldrift是漂移区电阻，Rdrain是漏区电阻，Rresurf是降低表面电场层的电阻，ρd是外延层电阻率，Ldrift是漂移区长度。
LDMOS器件反向耐压时，降低表面电场层中掺杂特性相反的n型半导体区11和p型半导体区12形成的横向PN结在横向上相互耗尽，p型半导体区12与漂移区3形成的纵向PN结在纵向上与漂移区3相互耗尽。横向上每一个n型半导体区11与p型半导体区12形成的PN结都会使表面电场在PN结对应得表面形成尖峰，分散LDMOS器件横向的表面电场，使表面耐压更高。同时纵向上，n型半导体区11及p型半导体区12使得纵向电场变得更为平坦，提高了纵向击穿电压。在常规LDMOS器件中，体内纵向击穿电压BV＝EC*tepi，体内纵向击穿电压BV由纵向临界电场EC(位于外延层2和衬底1之间)与外延层2厚度tepi决定。增加了降低表面电场层后，若要维持相同的纵向击穿电压，则外延层厚度tepi可以大大降低。在降低表面电场层实现时，外延层2的掺杂浓度Nepi与厚度tepi满足公式Nepi*tepi＝ε*Ec/q*sqrt(Nsub/(Nepi+Nsub))，式中ε为介电常数，q为电子电量，Nsub为衬底1的掺杂浓度。当纵向临界电场EC确定时，Nepi*tepi可视为常数，所以当外延层2厚度tepi降低时，外延层2掺杂浓度Nepi就会提高。可见，本实施例提供的结构在引入降低表面电场层后，可以大幅度降低正向导通电阻，使器件的导通损耗减小，在相同正向导通电阻的情况下提高LDMOS器件的耐压效果；并且在保证耐压的同时可以减小外延层2厚度，增加漂移区浓度，降低漂移区的正向导通电阻。
实施例二：如图3所示，在实施例一的基础上，为了防止n型半导体区11和p型半导体区12形成的PN结影响上方漏区4的电场，漂移区3对应于漏区4的部分向下扩展迈过衬底1和外延层2的交界面。
实施例三：如图4所示，在实施例一或实施例二的基础上，为了调节LDMOS器件反向耐压时n型半导体区11和p型半导体区12与漂移区3的电荷平衡，在n型半导体区11和p型半导体区12与漂移区3的交界面上增加埋层13，所述埋层13的掺杂特性与漂移区3相反，埋层13的掺杂浓度可以根据实际需要设定。
实施例四：如图5所示，在实施例一或实施例二或实施例三的基础上，为了进一步调节LDMOS器件反向耐压时n型半导体区11和p型半导体区12与漂移区3的电荷平衡，在漂移区3的上表面添加顶埋层(top)14，所述顶埋层14的掺杂特性与漂移区3相反，顶埋层14的掺杂浓度可以根据实际需要设定。
本领域的普通技术人员将会意识到，这里所述的实施例是为了帮助读者理解本发明的原理，应被理解为本发明的保护范围并不局限于这样的特别陈述和实施例。本领域的普通技术人员可以根据本发明公开的这些技术启示做出各种不脱离本发明实质的其它各种具体变形和组合，这些变形和组合仍然在本发明的保护范围内。

Claims (4)

1.一种高压LDMOS器件，包括衬底、位于衬底之上的外延层，位于外延层之上的漂移区，位于LDMOS器件两端的漏区和源区，其特征在于，在衬底和外延层的交界面上紧贴漂移区的下表面具有交替排列的至少一对n型半导体区和p型半导体区，所述n型半导体区和p型半导体区紧贴排列相互形成横向的PN结，同时p型半导体区与漂移区形成纵向的PN结。
2.根据权利要求1所述的一种高压LDMOS器件，其特征在于，在漂移区对应于漏区的部分向下扩展迈过衬底和外延层的交界面。
3.根据权利要求1或2所述的一种高压LDMOS器件，其特征在于，在n型半导体区和p型半导体区与漂移区的交界面上添加埋层，所述埋层的掺杂特性与漂移区相反。
4.根据权利要求1或2所述的一种高压LDMOS器件，其特征在于，在漂移区的上表面添加顶埋层，所述顶埋层的掺杂特性与漂移区相反。
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