CN101840935B - Soi横向mosfet器件 - Google Patents

Soi横向mosfet器件 Download PDF

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CN101840935B
CN101840935B CN201010173833XA CN201010173833A CN101840935B CN 101840935 B CN101840935 B CN 101840935B CN 201010173833X A CN201010173833X A CN 201010173833XA CN 201010173833 A CN201010173833 A CN 201010173833A CN 101840935 B CN101840935 B CN 101840935B
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soi
insulator
silicon
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CN101840935A (zh
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罗小蓉
弗罗林.乌德雷亚
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University of Electronic Science and Technology of China
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Abstract

本发明涉及半导体功率器件和功率集成电路。本发明公开一种SOI横向MOSFET器件。其技术方案是：采用纵向延伸至介质埋层的槽栅；在漂移区引入介质槽，其介质的介电系数小于有源层的介电系数，并在介质槽中形成埋栅，从而构成本发明的SOI横向MOSFET器件。本发明一方面使器件耐压大大提高并缩小器件横向尺寸，起主要作用的是介质槽；另一方面，槽栅增大了器件有效纵向导电区域；同时，槽栅和埋栅使沟道密度和电流密度增加；使比导通电阻降低，进而降低功耗。再者，介质槽降低了栅-漏电容，提高器件的频率和输出功率。本发明的器件具有高压、高速、低功耗，低成本和便于集成的优点，特别适合用于功率集成电路和射频功率集成电路。

Description

SOI横向MOSFET器件
技术领域
本发明涉及半导体功率器件和功率集成电路，确切地说涉及一种用于功率集成电路或射频功率集成电路的SOI(Semiconductor On Insulator，绝缘衬底上半导体)横向MOSFET(Metal-Oxide-Semiconductor Field-Effect-Transistor，金属-氧化物-半导体场效应晶体管)器件，特别涉及一种高耐压、低功耗的横向MOSFET器件。
背景技术
SOI是在顶层半导体(称为有源层)和衬底层(可以为半导体或绝缘介质)之间引入介质埋层，将半导体器件或电路制作在有源层中。集成电路中高压器件、低压电路之间通常采用隔离槽30进行隔离，有源层3与衬底层1之间则由介质层2进行隔离(如图1所示)。因此，与体硅(半导体)技术相比，SOI技术具有寄生效应小，泄漏电流小，集成度高、抗辐射能力强以及无可控硅自锁效应等优点，在高速、高温、低功耗以及抗辐射等领域得到广泛关注和应用。
SOI功率集成电路技术的关键是实现高耐压、低功耗以及高压单元和低压单元之间的有效隔离。SOI横向器件，如LDMOSFET(Lateral Double-diffusedMetal-Oxide-Semiconductor Field-Effect-Transistor LDMOSFET，横向双扩散金属氧化物场效应晶体管)因其便于集成和相对较低的导通电阻而成为SOI功率集成电路的核心器件，在等离子显示屏、马达驱动、汽车电子、便携式电源管理产品以及个人电脑等应用中倍受青睐。同时，较之于VDMOSFET(VerticalDouble-diffused  Metal-Oxide-Semiconductor Field-Effect-TransistorVDMOS，垂直双扩散金属氧化物半导体场效应晶体管)，横向MOSFET更高的开关速度，使其在射频领域应用广泛。
对于常规LDMOSFET器件而言，漂移区长度随器件击穿电压的升高单调增加。这不仅使器件(或电路)的芯片面积增加、成本增大，而且不利于小型化。更为严重的是，器件的导通电阻随漂移区长度(或器件耐压)的增加而增大(导通电阻与器件耐压的关系式可以表达为：Ron∝BV2.5，其中BV为器件耐压，Ron为导通电阻)，导通电阻的增加导致功耗急剧增加，并且器件开关速度也随之降低。
与平面栅结构的MOSFET相比，具有槽栅结构的MOSFET，一方面可以增加封装密度，从而提高沟道密度和电流密度。另一方面槽栅MOSFET的沟道的长度不受光刻工艺的限制，沟道可以做得较短，从而降低导通电阻。以上两点均增加槽栅结构的MOSFET电流承受能力。再者，槽栅MOSFET能够避免JFET(JunctionField-Effect-Transistor，结型场效应晶体管)效应和闭锁效应。
为了克服上面提到的常规LDMOSFET存在的问题，业内研究者利用槽栅MOSFET的优点，提出了基于槽技术的SOI LDMOSFET器件结构。文献(Won-So Son，Young-Ho Sohn，Sie-Young Choi，【Effects of a trench under the gate inhigh voltage RESURF LDMOSFET for SOI power integrated circuits】Solid-State Electronics 48(2004)1629-1635)提出具有槽的RESURFLDMOSFET，其器件结构如图2所示。该器件将氧化物槽31引入栅电极G末端附近直至漏区之间的漂移区。当掺杂浓度过高时，氧化物槽31降低栅电极G末端之下硅表面的高电场，避免此处提前击穿，并降低漏区边缘的表面电场峰值，从而在降低导通电阻的基础上提高器件耐压。该器件在漂移区长度为16μm，介质埋层2和有源层3厚度分别为3μm和8μm时的最高耐压可达356V。该文献报道其实验结果耐压为352V，比导通电阻约为18.8mΩ·cm2。该类结构的LDMOSFET在250V时，比导通电阻约为9mΩ·cm2。可见，该结构降低漂移区长度和比导通电阻的效果非常有限。
文献Naoto Fujishima and C.Andre T.Salama，【A trench lateral powerMOSFET using self-aligned trench bottom contact holes】IEDM 1997，359-362中将漏电极D和栅电极G设计在同一阶梯型状的槽中，且槽的下半部分(靠近漏区)侧壁有厚氧化物层32。文中将其称为槽底部具有漏接触的槽型横向功率MOSFET(Trench Lateral Power MOSFET with Trench Bottom Drain Contact)，称为TLPM/D MOSFET，器件结构如图3所示。美国专利(US7005352B2，2006.2.28，【trench-type MOSFET having a reduced device pitch and on-resistance】)将源电极S和栅电极G设计在同一槽中，称为TLPM/S MOSFET，结构如图4所示。以上两种结构均是采用槽型结构以降低器件横向尺寸(或芯片面积)，进而降低器件的导通电阻并保持较高耐压，前者更适于耐压高于80V的槽型低阻MOSFET，后者更适于耐压低于80V的槽型低阻小尺寸MOSFET，且工艺较前者更简单。但对于耐压超过100V的TLPM/D MOSFET，一方面槽下部分的厚氧化物层32厚度增加，削弱了缩小器件横向尺寸的优势；另一方面，槽的深度随耐压增加，将漏电极和栅电极制作在同一个深而窄的槽内工艺难度增大。以上两种结构均需将漏电极与栅电极或源电极与栅电极制作在同一槽中，其工艺难度随耐压的提高(槽的深度增加)而增大，而且该结构减小器件横向尺寸的效果随耐压的升高而削弱。美国专利(US2007/0298562A1，2007.12.27，【method of manufacturinga semiconductor integrated circuit device】)将上面提到的TLPM/S器件用于集成电路，但集成电路中的各个器件之间须采用PN结隔离和浅槽隔离，且将高压MOSFET的源电极和栅电极设计在同一槽中，工艺较复杂。
发明内容
本发明所要解决的技术问题，就是提供一种SOI横向MOSFET器件，利用槽栅结构配合介质槽及其中的埋栅电极，提高LDMOSFET耐压，降低比导通电阻和功耗，降低器件横向尺寸和芯片面积。
本发明解决所述技术问题，采用的技术方案是，SOI横向MOSFET器件，包括纵向自下而上的衬底层、介质埋层和有源层，所述有源层中形成槽栅，所述槽栅由栅介质及其包围的导电材料构成，所述导电材料引出端为槽栅电极；其特征在于，所述槽栅纵向长度穿过有源层直到介质埋层；在槽栅一侧的有源层表面具有体区和漏区，所述体区和漏区之间有间距，所述漏区引出端为漏电极；所述体区的表面顺次是源区a，体接触区，源区b；所述源区a、源区b和体接触区的共同引出端为源电极；所述槽栅与体区和源区a接触；源区b和漏区之间形成介质槽，所述介质槽与源区b和体区接触，所述介质槽中介质的介电系数小于有源层材料的介电系数，所述介质槽纵向深度大于体区纵向深度且小于有源层的厚度；所述介质槽中由导电材料形成埋栅，所述埋栅靠近源区b，且被介质槽中介质包围，所述埋栅深度小于介质槽深度，所述埋栅深度≥所述体区深度，所述埋栅引出端为埋栅电极，所述埋栅电极与槽栅电极电气连接，其共同引出端为栅电极。
所述SOI横向MOSFET器件为对称结构，所述漏区位于器件中心，由中心漏区向外依次是介质槽、源区b、体接触区、源区a和槽栅，槽栅位于器件外围。便于利用槽栅介质实现器件或电路间的隔离。
所述SOI横向MOSFET器件为面对称结构，平分漏区且不穿过介质槽和栅槽的平面为其对称面。
所述SOI横向MOSFET器件为轴对称结构，过漏区中心的纵轴为其对称轴。
该方案在版图设计中，漏区剖面形状可以为圆形或除正三角形之外的正多边形，与之匹配的介质槽、源区b、体接触区、源区a和槽栅的剖面形状则为圆环形环带或除正三角形环带之外的正多边形环带。对于剖面形状为圆形的漏区，且介质槽、源区a、源区b、体接触区和槽栅为圆环形环带的器件结构，具有最佳的对称型，且减弱了曲率效应，因而耐压最高，且节省芯片面积。采用其他正多边形结构，如正六边形等也是一种常用的选择。一般而言，同一器件的漏区剖面形状与外围如栅槽和介质槽的剖面形状相匹配，如漏区为正六边形，介质槽、源区a、源区b、体接触区和槽栅也为正六边形环带。
所述栅介质纵向成上薄下厚的结构。该方案可以进一步提高器件耐压。
所述介质槽共有n条，n≥2，每条介质槽之间有间距；埋栅位于与体区接触的介质槽中。该方案适当增加介质槽的条数，有利于提高器件耐压。
所述介质槽之间的有源层材料导电类型相同或不同。该方案便于根据需要选择制作工艺、制作步骤，从而增加工艺的灵活性。
所述介质槽纵向深度，横向宽度及间距相等或不相等。
所述介质槽的条数大于3时，中间的介质槽深度大于两侧介质槽深度。这种结构有利于提高耐压。
所述漏区与介质槽接触或不接触。该方案中，漏区与介质槽不接触较之接触的结构形式，耐压有一定提高；漏区与介质槽接触较之不接触的结构，导通电阻有一定降低。
所述SOI横向MOSFET器件用于集成电路的有源器件。
所述集成电路为功率集成电路或射频功率集成电路。
所述有源层材料包括但不限于Si、SiC、SiGe、GaAs或GaN。该方案中列举的这几种材料技术成熟，取材方便。
所述有源层材料为Si，所述介质槽中介质为SiO2，或介电系数低于SiO2且临界击穿电场高于Si临界击穿电场3倍的介质：包括但不限于SiOF、CDO或SiCOF。
对于Si半导体，业界常用使用SiO2作介质，工艺成熟。由于SiO2的相对介电系数3.9低于Si的相对介电系数11.9，所以增强介质槽内介质的电场，提高器件耐压；选用相对介电系数低于SiO2且临界击穿电场高于Si临界击穿电场3倍的介质更有利于提高器件耐压。
所述有源层材料为Si，所述栅介质为SiO2；或介电系数高于SiO2的介质：包括但不限于Si3N4、Al2O3、AlN或HfO2。该方案中，高介电系数的栅介质可以增强栅电压对栅电荷的控制能力，增大跨导；或者在相同的栅结构MIS(Metal-Insulator-Semiconductor，栅电极-栅介质-栅介质下的半导体形成MIS结构)电容下，可以将栅介质做得更厚，减小隧道电流，避免隧穿效应，增强器件或芯片的稳定性与可靠性。
所述有源层材料为Si，所述介质埋层材料为SiO2；或介电系数低于SiO2且临界击穿电场高于Si临界击穿电场3倍的介质：包括但不限于SiOF、CDO或SiCOF。介质埋层采用介电系数较低的介质，可以增强介质埋层的电场，有利于器件耐压的提高。
本发明的有益效果是：①阻断状态下，在横向，位于漏区和源区b之间的介质槽内的介质参与耐压，由于介质(比如SiO2)的介电系数小于半导体有源层(比如Si)的介电系数，所以介质槽内电场远大于有源层内的电场；在纵向，槽栅结构和介质槽增强了有源层内的多维度耗尽。二者均使器件耐压提高，因此，对于相同的器件横向尺寸，器件耐压大幅度提高；或对于相同的耐压，漂移区和器件长度大幅度减小，从而降低导通电阻和功耗，可以满足降低芯片成本和小型化的要求。②介质槽使漂移区沿纵向折叠，缩小器件横向尺寸，进而降低比导通电阻和芯片成本，并增加开关速度。③介质槽内介质的介电系数低于有源层的介电系数，这降低了栅电极-漏电极间电容，提高了器件的开关频率和输出功率，特别有益于射频领域的应用。④导通状态下，纵向延伸至介质埋层的槽栅扩展漂移区纵向有效导电区域，大大降低导通电阻和功耗。同时，埋栅结构进一步增加器件的沟道密度和电流密度，降低功耗。⑤高压截止状态时，纵向延伸至介质埋层上界面的栅介质将来自于器件中心的漏区的高电位终止于槽栅以内，避免高电位对槽栅以外低压电路的影响。因此，栅槽同时也作为介质隔离槽，这不仅节省了介质隔离槽的面积，而且不需要象常规SOI高压集成电路那样，采用专门工艺流程制作介质隔离槽，简化了功率集成电路工艺，节约了成本。简言之，本发明的优点是提供了高耐压、高速、低功耗、低成本、小型化以及便于与功率集成电路集成的SOI横向MOSFET。
附图说明
图1是常规SOI技术高压集成电路剖面结构示意图。
图2是具有槽的SOI RESURF LDMOSFET器件结构示意图。
图3是TLPM/D MOSFET结构示意图。
图4是TLPM/S MOSFET结构示意图。
图5是具有面对称结构的SOI横向MOSFET器件元胞结构示意图(xz平面)；
AA′沿x方向，BB′沿z方向，纵向即为y方向；器件结构以过BB′的yz平面对称。
图6是具有轴对称结构的SOI横向MOSFET器件元胞结构示意图(xz平面)；
AA′沿x方向；纵向即为y方向；器件以过漏电极D中心的y轴为对称轴。
图7是N沟道SOI横向MOSFET元胞结构剖视图(沿图5或图6中AA′线的纵剖面，即xy平面图，下同)。
图8是漏区不与介质槽接触的N沟道SOI横向MOSFET器件元胞结构剖视图；
图9是栅介质上薄下厚的N沟道SOI横向MOSFET器件元胞结构剖视图；
图10a具有2个介质槽的N沟道SOI横向MOSFET器件剖视图(半个元胞)；
图10b是介质槽之间材料具有不同导电类型的N沟道SOI横向MOSFET器件结构示意图(半个元胞)；
图11a具有三个介质槽，且介质槽深度不同的N沟道SOI横向MOSFET器件结构示意图(半个元胞)；
图11b具有三个介质槽，且介质槽之间的有源层材料导电类型不同的N沟道SOl横向MOSFET结构示意图(半个元胞)；
图12是P沟道SOI横向MOSFET器件元胞结构剖视图；
图13是二维等势线分布比较示意图(半个元胞)；
图14是二维电流线分布比较示意图(半个元胞)；
图15是本发明用于集成电路中，高压SOI横向MOSFET器件与低压电路的隔离示意图。
附图标记：
1、衬底层；2、介质层；3、有源层；4、栅介质；5、导电材料；61为介质槽；6为介质槽内填充介质；7为埋栅；8为栅槽；9为体区；10为体接触区；11a为源区a；11b为源区b；21表示槽栅电极；22表示埋栅电极；30为介质隔离槽；31为氧化物槽；32为厚氧化物层；60为介质槽之间的有源层材料；S为源电极；D为漏电极；G为栅电极。
具体实施方式
下面结合附图及实施例，详细描述本发明的技术方案。
本发明的技术方案，充分利用槽栅、介质槽及埋栅，对SOI横向MOSFET器件的电气性能进行了综合改进和提高。为了方便描述，本发明的SOI横向MOSFET器件有的地方也简称为器件。
实施例1
参见图5所示，这是一种面对称结构的一个SOI横向MOSFET器件元胞版图布局示意图。该图为xz平面图，其中AA′沿x方向，BB′沿z方向，纵向即为y方向。该器件的对称面为过BB′的yz平面。该图包含介质槽61和槽栅8的版图，还有金属电极的版图：槽栅电极21、埋栅电极22、栅电极G、源电极S和漏电极D。在该版图布局上，电学起作用的源区、漏区，槽栅8，介质槽61，埋栅等图形均为条形，图中漏电极D位于器件中心，漏电极D两边为介质槽61，介质槽61外侧为源电极S，槽栅8位于器件最外侧以便实现集成电路中高、低压单元隔离。介质槽61中的导电材料形成埋栅，由埋栅电极22引出，槽栅8中的导电材料由槽栅电极21引出，他们的共同引出端为器件的栅电极G。图中栅电极G和源电极S采用了惯用的叉指状结构。
图6示出了一种具有轴对称结构的一个SOI横向MOSFET器件元胞版图布局图，即xz平面图，其中AA′沿x方向。该图以圆形图形为例描述轴对称结构。漏区D位于器件中心，与源区b被介质槽61隔开。器件以过漏电极D中心的y轴为对称轴。介质槽61中的埋栅由埋栅电极22引出，与器件最外围的槽栅8中的导电材料的引出端槽栅电极21电气连接，构成器件的栅电极G。槽栅8位于器件最外侧以便实现集成电路中高、低压单元隔离。
图7示出了N沟道SOI横向MOSFET器件元胞剖视图。该图为xy平面图。其包括纵向(y轴)自下而上的衬底层1、介质埋层2和有源层3。有源层3中形成槽栅8，槽栅8由栅介质4及其包围的导电材料5构成，导电材料5引出端为槽栅电极。槽栅8纵向长度穿过有源层3直到介质埋层2。在槽栅一侧的有源层表面具有体区9和漏区，漏区引出端为漏电极D。体区9和漏区之间有间距。体区9的表面顺次是源区a(图中标识为11a)，体接触区10，源区b(图中标识为11b)。源区a、源区b和体接触区10的共同引出端为源电极S。槽栅8与体区9和源区a接触，源区b和漏区之间形成介质槽61，介质槽61中填充介质6，介质6的介电系数小于有源层3材料的介电系数。介质槽61纵向深度大于体区9纵向深度且小于有源层3的厚度。介质槽61中由导电材料形成埋栅7，埋栅7靠近源区b，且被介质槽中介质6包围。埋栅7深度小于介质槽深度，埋栅7深度≥体区9深度，埋栅7引出端为埋栅电极，埋栅电极与槽栅电极电气连接，其共同引出端为器件的栅电极G。
槽栅结构的引入增大了器件的有效纵向导电面积，从而大大降低比导通电阻。槽栅和埋栅的双栅结构又使沟道密度增加，在相同器件大小的情况下比导通电阻降低。介质槽的引入不仅提高了器件耐压，而且减小了器件或芯片的横向尺寸，从而降低导通电阻和功耗，并因此节约成本。图7示出的是具有单介质槽61的N沟道SOI横向MOSFET器件。这种结构形状的器件工艺更容易实现，器件具有最佳的对称性。
实施例2
与实施例1相比，本例器件漏区n+与介质槽61不接触，其余结构与实施例1相同，如图8所示。与图7所示结构相比，本例中器件耐压有一定提高，但导通电阻略有上升。
实施例3
本例器件栅介质4纵向成上薄下厚的结构，如图9所示。这种槽栅8的结构有利于提高器件耐压。
实施例4
如图10a和图10b所示，本例器件共有2条介质槽61，也是N沟道SOI横向MOSFET器件。介质槽61的纵向深度相同。图10a介质槽之间有源层材料60与有源层3的材料导电类型相同，制造时，可以采用先刻介质槽61和填充介质6，再注入、扩散形成体区9，源区、漏区和体接触区10。图10b介质槽之间有源层材料60与有源层3的材料导电类型不同，制造时，可以采用先在有源层3上外延形成体区9，之后刻介质槽61和填充介质6，再注入、扩散形成体接触区、漏区n、源区和体区9的工艺。图10a、b仅示出了器件的半个元胞。
实施例5
本例器件介质槽61共有3条，介质槽61的纵向深度不相等，位于中间的介质槽61深度大于其两边的介质槽61深度，如图11a、b所示。中间的介质槽61深度大于两侧介质槽61深度，这种结构有利于提高耐压。图11a中介质槽61之间材料导电类型与有源层3相同，图11b中介质槽61之间材料导电类型与有源层3不同。
实施例6
参加图12，本例器件为具有单介质槽61的P沟道SOI横向MOSFET器件。本例器件有源层3、源区a、源区b、漏区、体区9和体接触区10的材料导电类型与N沟道SOI横向MOSFET器件(图7和图8所示)正好向反。其他结构参见实施例1。
实施例2-实施例5的结构均适用于P沟道SOI横向MOSFET器件。不过P沟道SOI横向MOSFET器件有源层3、源区a、源区b、漏区、体区9和体接触区10的材料导电类型与N沟道SOI横向MOSFET器件(图7-11所示)正好向反。
适当增加介质槽61的条数，可以提高器件耐压。但条数过多使得图形线条变窄，工艺难度增加。当采用多条介质槽的结构时，每条介质槽纵向深度，横向宽度及间距可以相等或不相等。
本发明的SOI横向MOSFET器件最适合由于集成电路的有源器件，特别是用于功率集成电路和射频功率集成电路。
本发明的上述几种实施例描述的器件，可以采用Si、SiC、SiGe、GaAs或GaN等作为源层3的材料制作器件或集成电路，这几种材料技术成熟，取材方便。可以满足不同器件或电路性能要求。
如果有源层材料采用Si，推荐的导电材料5和埋栅导电材料为多晶硅。
作为业界常用的介质，介质槽中介质6为SiO2，或可以采用介电系数低于SiO2且临界击穿电场高于Si临界击穿电场3倍的介质，如SiOF、CDO或SiCOF等。由于SiO2相对介电系数3.9低于Si相对介电系数11.9，所以增强了介质槽内介质的电场，提高器件耐压，选用相对介电系数低于SiO2且临界击穿电场高于Si临界击穿电场3倍的介质更有利于提高耐压。介质槽61中介质6的低介电系数，还有利于降低器件栅-漏电容，提高器件开关速度。
栅介质4的选择，也可以采用SiO2，或介电系数高于SiO2且临界击穿电场与SiO2相当或更高的介质：如Si3N4、AlN、Al2O3或HfO2等。栅介质采用较高的介电系数，可以增强栅电压对栅电荷的控制能力，增大跨导。或者在相同的栅结构MIS(Metal-Insulator-Semiconductor，栅电极-栅介质-栅介质下的半导体形成MIS结构)电容下，可以将栅介质做得更厚，减小隧道电流，避免隧穿效应，增强器件或芯片的稳定性与可靠性。
对于介质埋层2的材料，SiO2是业界常用的，或采用介电系数低于SiO2且临界击穿电场高于Si临界击穿电场3倍的介质，如SiOF、CDO或SiCOF等。采用介电系数较低的介质，可以增强介质埋层2的电场，有利于器件耐压的提高。
本发明的技术方案，对衬底材料几乎没有要求，可以是n型或p型半导体材料，甚至可以是绝缘介质材料，或与介质埋层为同一种介质材料。
图13是二维等势线分布比较示意图(半个元胞)。a代表常规平面栅LDMOSFET(无槽栅、埋栅和介质槽)；b代表具有槽栅但无介质槽的横向MOSFET；c代表本发明公开的具有槽栅、埋栅和介质槽的SOI横向MOSFET器件。图中2根相邻等势线的电压差为10V，三种结构击穿电压分别为254V，130V，109V。对比图13(a)和(b)可知，槽栅结构的引入使耐压从常规SOI LDMOS的109V提高到130V；对比图13(b)和(c)可知，介质槽使耐压130V提高到254V，提高了接近1倍。
图14是二维电流线分布(2根相邻电流线的电流强度差为1×10-6A/μm)。a代表常规平面栅LDMOSFET(无槽栅、埋栅和介质槽)；b代表具有槽栅但无介质槽的横向MOSFET；c代表本发明公开的具有槽栅、埋栅和介质槽的SOI横向MOSFET器件。在图14(a)的常规SOI LDMOSFET器件中，电流仅流经器件表面薄层，有效的导电面积较小。对比图14(a)和(b)可知，槽栅8的引入增大了器件的有效纵向导电面积，从而大大降低比导通电阻。因此，器件的比导通电阻从图14(a)的7.7mΩ.cm2降低为4mΩ.cm2。对比图14(b)和(c)可知，尽管介质槽61占据了漂移区中较大的导电区域，但优化的漂移区浓度因此而增大；而且，槽栅和埋栅使沟道密度增加，所以，本发明技术在相同的器件大小的情况下比导通电阻降低为3.5mΩ.cm2。
综上，本发明的技术一方面使器件耐压大大提高并缩小器件横向尺寸，起主要作用的是介质槽61；另一方面，槽栅8增大了器件有效纵向导电面积，大大降低比导通电阻；同时，槽栅8埋栅7两种结构使沟道密度和电流密度增加，显著降低比导通电阻，进而降低功耗；再者，介质槽降低了栅-漏电容，提高器件的频率和输出功率。
图15是本发明用于集成电路中，高压器件与电压电路的隔离示意图。可以看出，采用本发明的技术方案，高压器件与低压电路之间不需要形成专门的隔离槽(如图1中的30)，本发明的槽栅本身就具有完善的隔离作用，该技术降低了集成电路的制造成本和工艺难度。

Claims (14)

1.SOI横向MOSFET器件，包括纵向自下而上的衬底层、介质埋层和有源层，所述有源层中形成槽栅，所述槽栅由栅介质及其包围的导电材料构成，所述导电材料引出端为槽栅电极；其特征在于，所述槽栅纵向长度穿过有源层直到介质埋层；在槽栅一侧的有源层表面具有体区和漏区，所述体区和漏区之间有间距，所述漏区引出端为漏电极；所述体区的表面顺次是源区a，体接触区，源区b；所述源区a、源区b和体接触区的共同引出端为源电极；所述槽栅与体区和源区a接触；源区b和漏区之间形成介质槽，所述介质槽与源区b和体区接触，所述介质槽中介质的介电系数小于有源层材料的介电系数，所述介质槽纵向深度大于体区纵向深度且小于有源层的厚度；所述介质槽中由导电材料形成埋栅，所述埋栅靠近源区b，且被介质槽中介质包围，所述埋栅深度小于介质槽深度，所述埋栅深度≥所述体区深度，所述埋栅引出端为埋栅电极，所述埋栅电极与槽栅电极电气连接，其共同引出端为栅电极；所述SOI横向MOSFET器件为对称结构，所述漏区位于器件中心，由中心漏区向外依次是介质槽、源区b、体接触区、源区a和槽栅，槽栅位于器件外围。
2.根据权利要求1所述SOI横向MOSFET器件，其特征在于，所述SOI横向MOSFET器件为面对称结构，平分漏区且不穿过介质槽和槽栅的平面为其对称面。
3.根据权利要求2所述的SOI横向MOSFET器件，其特征在于，所述介质槽共有n条，n为大于或等于2的偶数，介质槽之间有间距；埋栅位于与体区接触的介质槽中。
4.根据权利要求1所述的SOI横向MOSFET器件，其特征在于，所述SOI横向MOSFET器件为轴对称结构，过漏区中心的纵轴为其对称轴。
5.根据权利要求4所述的SOI横向MOSFET器件，其特征在于，所述介质 槽共有j条，j为大于或等于1的整数，介质槽之间有间距；埋栅位于与体区接触的介质槽中。
6.根据权利要求3或5所述的SOI横向MOSFET器件，其特征在于，所述介质槽纵向深度，横向宽度及间距相等或不相等。
7.根据权利要求1所述的SOI横向MOSFET器件，其特征在于，所述栅介质纵向成上薄下厚的结构。
8.根据权利要求1所述的SOI横向MOSFET器件，其特征在于，所述漏区与介质槽接触或不接触。
9.根据权利要求1所述的SOI横向MOSFET器件，其特征在于，所述SOI横向MOSFET器件用于集成电路的有源器件。
10.根据权利要求9所述的SOI横向MOSFET器件，其特征在于，所述集成电路为功率集成电路或射频功率集成电路。
11.根据权利要求1所述的SOI横向MOSFET器件，其特征在于，所述有源层材料包括Si、SiC、SiGe、GaAs或GaN。
12.根据权利要求11所述的SOI横向MOSFET器件，其特征在于，所述有源层材料为Si，所述介质槽中介质为SiO2，或介电系数低于SiO2且临界击穿电场高于Si 临界击穿电场3倍的介质：包括SiOF、CDO或SiCOF。
13.根据权利要求11所述的SOI横向MOSFET器件，其特征在于，所述有源层材料为Si，所述栅介质为SiO2；或介电系数高于SiO2的介质：包括Si3N4、Al2O3、AlN或HfO2。
14.根据权利要求11所述的SOI横向MOSFET器件，其特征在于，所述有源层材料为Si，所述介质埋层材料为SiO2；或介电系数低于SiO2且临界击穿电场高于Si临界击穿电场3倍的介质：包括SiOF、CDO或SiCOF。 
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Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102487082A (zh) * 2010-12-02 2012-06-06 上海华虹Nec电子有限公司 横向沟槽金属氧化物半导体器件
CN102148251B (zh) * 2011-01-10 2013-01-30 电子科技大学 Soi横向mosfet器件和集成电路
US9136158B2 (en) 2012-03-09 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral MOSFET with dielectric isolation trench
CN102832237B (zh) * 2012-07-03 2015-04-01 电子科技大学 一种槽型半导体功率器件
CN102810553B (zh) * 2012-08-21 2015-03-25 重庆大学 一种极低导通电阻的槽型场氧功率mos器件
CN103077950A (zh) * 2013-02-01 2013-05-01 上海宏力半导体制造有限公司 绝缘体上硅射频器件及其制造方法
CN105556647B (zh) * 2013-07-19 2017-06-13 日产自动车株式会社 半导体装置及其制造方法
CN103646951A (zh) * 2013-12-17 2014-03-19 山东大学 一种耐高温电子器件原材料及其应用
CN104241365A (zh) * 2014-04-10 2014-12-24 电子科技大学 一种soi横向功率mosfet器件
CN103915505A (zh) * 2014-04-21 2014-07-09 天津理工大学 一种槽栅槽源soi ldmos器件
JP2017518018A (ja) * 2014-05-07 2017-06-29 ワイトリシティ コーポレーションＷｉｔｒｉｃｉｔｙ Ｃｏｒｐｏｒａｔｉｏｎ 無線エネルギー伝送システムにおける異物検出
US9406793B2 (en) 2014-07-03 2016-08-02 Broadcom Corporation Semiconductor device with a vertical channel formed through a plurality of semiconductor layers
CN105405880B (zh) * 2014-08-08 2019-05-07 瑞昱半导体股份有限公司 半导体元件及多栅极场效应晶体管
CN105514102A (zh) * 2014-10-17 2016-04-20 中芯国际集成电路制造(上海)有限公司 一种版图结构、半导体器件和电子装置
CN104299992B (zh) * 2014-10-23 2017-03-22 东南大学 一种横向沟槽绝缘栅双极型晶体管及其制备方法
CN107660312B (zh) * 2015-06-19 2022-08-12 英特尔公司 使用穿硅过孔栅极的竖直晶体管
CN105161420B (zh) * 2015-07-13 2017-10-13 电子科技大学 一种横向mosfet器件的制造方法
CN105206659B (zh) * 2015-08-28 2017-11-14 电子科技大学 一种横向高压功率器件的结终端结构
CN105070760B (zh) * 2015-09-06 2017-12-19 电子科技大学 一种功率mos器件
US10269916B2 (en) * 2016-05-24 2019-04-23 Maxim Integrated Products, Inc. LDMOS transistors and associated systems and methods
CN106711186A (zh) * 2016-12-08 2017-05-24 长沙理工大学 一种低比导的高压功率器件
US10177243B1 (en) * 2017-06-19 2019-01-08 Nxp B.V. Extended drain NMOS transistor with buried P type region
US10424646B2 (en) 2017-09-26 2019-09-24 Nxp Usa, Inc. Field-effect transistor and method therefor
US10522677B2 (en) 2017-09-26 2019-12-31 Nxp Usa, Inc. Field-effect transistor and method therefor
US10600911B2 (en) 2017-09-26 2020-03-24 Nxp Usa, Inc. Field-effect transistor and method therefor
US10600879B2 (en) 2018-03-12 2020-03-24 Nxp Usa, Inc. Transistor trench structure with field plate structures
US10833174B2 (en) 2018-10-26 2020-11-10 Nxp Usa, Inc. Transistor devices with extended drain regions located in trench sidewalls
US10749023B2 (en) 2018-10-30 2020-08-18 Nxp Usa, Inc. Vertical transistor with extended drain region
US10749028B2 (en) 2018-11-30 2020-08-18 Nxp Usa, Inc. Transistor with gate/field plate structure
US11387348B2 (en) 2019-11-22 2022-07-12 Nxp Usa, Inc. Transistor formed with spacer
US11329156B2 (en) 2019-12-16 2022-05-10 Nxp Usa, Inc. Transistor with extended drain region
US11217675B2 (en) 2020-03-31 2022-01-04 Nxp Usa, Inc. Trench with different transverse cross-sectional widths
US11075110B1 (en) 2020-03-31 2021-07-27 Nxp Usa, Inc. Transistor trench with field plate structure
CN115548089A (zh) * 2021-03-15 2022-12-30 无锡新洁能股份有限公司 半导体器件
CN113284954B (zh) * 2021-07-22 2021-09-24 成都蓉矽半导体有限公司 一种高沟道密度的碳化硅mosfet及其制备方法
CN113594258B (zh) * 2021-08-27 2023-04-25 电子科技大学 低辐射漏电高压ldmos器件
CN114725206B (zh) * 2022-03-08 2023-07-25 西南交通大学 一种基于低介电常数介质的SiCVDMOSFET器件
CN114420761B (zh) * 2022-03-30 2022-06-07 成都功成半导体有限公司 一种耐高压碳化硅器件及其制备方法
CN115064443A (zh) * 2022-06-21 2022-09-16 上海晶岳电子有限公司 一种功率半导体结构制造方法
CN116053302B (zh) * 2023-03-07 2023-07-04 南京邮电大学 基于双soi结构的背栅辅助resurf系统及双soi结构的制造方法
CN116613212B (zh) * 2023-03-20 2024-01-30 杭州芯迈半导体技术有限公司 一种沟槽型半导体功率器件及版图
CN117199155B (zh) * 2023-11-06 2024-02-13 杭州特洛伊光电技术有限公司 一种波导型可见光及近红外光探测器结构与制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227653A (en) * 1991-08-07 1993-07-13 North American Philips Corp. Lateral trench-gate bipolar transistors
US7445983B2 (en) * 2002-10-17 2008-11-04 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor integrated circuit device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172101A (ja) * 1989-05-16 1997-06-30 Toshiba Corp 半導体装置
DE69528944T2 (de) * 1994-09-16 2003-09-04 Toshiba Kawasaki Kk Halbleiteranordnung mit hoher Durchbruchspannung und mit einer vergrabenen MOS-Gatestruktur
JP4797265B2 (ja) * 2001-03-21 2011-10-19 富士電機株式会社 半導体装置および半導体装置の製造方法
JP3534084B2 (ja) * 2001-04-18 2004-06-07 株式会社デンソー 半導体装置およびその製造方法
US7012301B2 (en) * 2001-12-18 2006-03-14 Fuji Electric Co., Ltd. Trench lateral power MOSFET and a method of manufacturing the same
JP2006269720A (ja) * 2005-03-24 2006-10-05 Toshiba Corp 半導体素子及びその製造方法
US20070029573A1 (en) * 2005-08-08 2007-02-08 Lin Cheng Vertical-channel junction field-effect transistors having buried gates and methods of making
US7759731B2 (en) * 2006-08-28 2010-07-20 Advanced Analogic Technologies, Inc. Lateral trench MOSFET with direct trench polysilicon contact and method of forming the same
CN101246825B (zh) * 2008-03-07 2010-09-22 北京工业大学 硅材料高频低功耗功率结型场效应晶体管(jfet)的制造方法
US7781832B2 (en) * 2008-05-28 2010-08-24 Ptek Technology Co., Ltd. Trench-type power MOS transistor and integrated circuit utilizing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227653A (en) * 1991-08-07 1993-07-13 North American Philips Corp. Lateral trench-gate bipolar transistors
US7445983B2 (en) * 2002-10-17 2008-11-04 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor integrated circuit device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开平9-172101A 1997.06.30

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