CN103187443B - 横向双扩散金属氧化物半导体场效应晶体管 - Google Patents

横向双扩散金属氧化物半导体场效应晶体管 Download PDF

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CN103187443B
CN103187443B CN201110453969.0A CN201110453969A CN103187443B CN 103187443 B CN103187443 B CN 103187443B CN 201110453969 A CN201110453969 A CN 201110453969A CN 103187443 B CN103187443 B CN 103187443B
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CN103187443A (zh
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韩广涛
颜剑
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CSMC Technologies Corp
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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Abstract

本发明提供一种横向双扩散金属氧化物半导体场效应晶体管(LDMOS),该LDMOS包括源区、栅介质层、漏区、设置在漏区和栅介质层之间的漂移区、设置在漂移区之上的场氧化层、基本设置在栅介质层之上的栅极,其中,在所述场氧化层的相对靠近所述漏区的部分之上设置场区辅助电极,在开态时,所述场区辅助电极被偏置与所述漏区所偏置的电压方向相同的电压。该LDMOS具有在开态时崩溃电压高的特点,并且工作电压高。

Description

横向双扩散金属氧化物半导体场效应晶体管
技术领域
本发明属于横向双扩散金属氧化物半导体场效应晶体管(LateralDoubleDiffusedMOSFET,LDMOS)技术领域,尤其涉及在场氧化层上设置场辅助电极以提高其在开态的崩溃电压的LDMOS。
背景技术
LDMOS作为一种功率开关器件,其具有工作电压相对高、工艺简单、易于同低压CMOS电路在工艺上兼容等优点,在工作时包括有“关态(Off-state)”和“开态(On-state)”。随着LDMOS的广泛应用功率集成电路(PowerIntegratedCircuit,PIC),对LDMOS的器件性能要求也越来越高,其中一个重要要求在于提高LDMOS在开态的崩溃电压。
图1所示为传统LDMOS的基本截面结构示意图。如图1所示,在LDMOS10的P型衬底100上,在P型衬底100上通过构图掺杂工艺形成有源区110、漏区170、P型体区120、高压N阱150(用于形成漂移区),源区110和漏区170之上可以分别构图引出源极(S)和漏极(D)(图中未示出),P型体区220之上构图氧化形成栅介质层130、并在栅介质层130上形成多晶硅的栅极140(G),在高压N阱250上采用LOCOS(LocalOxidationofSilicon,硅的局部氧化)工艺形成场氧化层160,栅极140可以部分地延伸至场氧化层160之上。
图1所示的LDMOS通常工作在高压条件下,例如,在开态时,栅极140和漏区170会被偏置高压,漂移区因此会被不断耗尽;随着漏区170上偏置的电压不断提高(也即源漏电压Vds不断提高),漂移区中的耗尽层会向漏区170不断扩展;当耗尽层快要接触到漏区170的N+阱边界时,由于漏区170的高掺杂特性,耗尽层向漏区170继续扩展有限,在漏区170与漂移区的交接处,电力线分布趋于密集,也即漏区170偏置的高压容易加载在该交接处的有限区域内,该区域电场随着Vds的增加而快速增大;进而,也容易由于大电场引发碰撞电离(ImpactIonization)导致击穿。
因此,图1所示实施例的传统LDMOS在开态下随着Vds的上升而容易被击穿,也即开态下的崩溃电压较低。
中国专利申请号为CN201110077379.2、名称为“LDMOS器件”的发明专利中,公开了一种LDMOS,其在漂移区中设置有电容区域,以改善漂移区域的电场分布,从而提高击穿电压(不同于崩溃电压)、减小导通电阻。但是,其并没有解决图1所示LDMOS中存在的问题。
发明内容
本发明的目的之一在于,提高LDMOS在开态下的崩溃电压。
为实现以上目的或者其他目的,本发明提供一种LDMOS,包括源区、栅介质层、漏区、设置在漏区和栅介质层之间的漂移区、设置在漂移区之上的场氧化层、基本设置在栅介质层之上的栅极,其特征在于,在所述场氧化层的相对靠近所述漏区的部分之上设置场区辅助电极,在开态时,所述场区辅助电极被偏置与所述漏区所偏置的电压方向相同的电压。
按照本发明一实施例的LDMOS,其中,所述场区辅助电极与所述漏区偏置相同大小的电压。
在之前所述任意实施例的LDMOS中,优选地,所述场区辅助电极与所述漏区之间的距离为所述场氧化层的长度的5%至25%。
在之前所述任意实施例的LDMOS中,优选地,所述场区辅助电极与所述栅极均为多晶硅电极,所述场区辅助电极和所述栅极同步地构图形成。
在之前所述任意实施例的LDMOS中,优选地,所述漂移区与所述漏区同类型掺杂,并且,所述漂移区低于所述漏区掺杂浓度。
优选地,所述漂移区的掺杂浓度范围为1×1015/cm3至1×1018/cm3
优选地,所述漏区的掺杂浓度范围为1×1018/cm3至1×1022/cm3
在之前所述任意实施例的LDMOS中,优选地,所述场区辅助电极以一段或多段的形式设置于所述场氧化层之上。
按照本发明又一实施例的LDMOS,其中,所述场区辅助电极与所述漏区上的漏极分离地设置。
按照本发明还一实施例的LDMOS,其中,所述场区辅助电极与所述漏区上的漏极一体化地设置。
优选地,所述场区辅助电极与所述漏极为金属或金属硅化物材料制成。
按照本发明再一实施例的LDMOS,其中,所述LDMOS为N沟道LDMOS,所述电压方向为正向。
本发明的技术效果是,通过在场氧化层之上设置场区辅助电极,其在开态下偏置与漏区所偏置电压方向相同的电压,从而可以使场区辅助电极的大致下方所对应的漂移区区域的杂质浓度增加,在Vds增大时,该区域阻止耗尽层向高掺杂的漏区边界扩展,能降低漏区与漂移区交接处的电场,优化电场分布,避免碰撞电离发生,提高崩溃电压,并从而提高LDMOS的工作电压。
附图说明
从结合附图的以下详细说明中,将会使本发明的上述和其他目的及优点更加完全清楚,其中,相同或相似的要素采用相同的标号表示。
图1是传统LDMOS的基本截面结构示意图。
图2是按照本发明一实施例提供的LDMOS的基本截面结构示意图。
图3是LDMOS的转移特性曲线示意图。
图4是按照本发明又一实施例提供的LDMOS的基本截面结构示意图。
具体实施方式
下面介绍的是本发明的多个可能实施例中的一些,旨在提供对本发明的基本了解,并不旨在确认本发明的关键或决定性的要素或限定所要保护的范围。容易理解,根据本发明的技术方案,在不变更本发明的实质精神下,本领域的一般技术人员可以提出可相互替换的其他实现方式。因此,以下具体实施方式以及附图仅是对本发明的技术方案的示例性说明,而不应当视为本发明的全部或者视为对本发明技术方案的限定或限制。
在附图中,为了清楚起见,夸大了层和区域的厚度,并且,由于刻蚀引起的圆润等形状特征未在附图中示意出。
本文中,“上”、“下”、“左”、“右”的方向性术语是相对于附图中的LDMOS的方位来定义的(例如,左右方向是指LDMOS的沟道方向、其平行于衬底表面,上下方向垂直于衬底表面)。并且,应当理解到,这些方向性术语是相对的概念,它们用于相对于的描述和澄清,其可以根据LDMOS所放置的方位的变化而相应地发生变化。
图2所示为按照本发明一实施例提供的LDMOS的基本截面结构示意图。在该实施例中,LDMOS20为N沟道LDMOS,以下结合图2对该实施例的LDMOS结构进行具体说明。
如图2所示,LDMOS形成于衬底200上,对于N沟道LDMOS,衬底200为P型掺杂,其具体掺杂浓度不受本发明限制性的。衬底200具体地可以通过外延生长形成、也可以为晶圆衬底。在衬底200中形成有源区210和漏区270,在该实例中,源区210和漏区270通过对衬底200构图N型掺杂形成N+阱来形成,源区210和漏区270的掺杂浓度可以相同,因此,二者可以同步地掺杂形成。源区210和漏区270之上可以分别形成源极(图中未示出)和漏极271;源极用于引出源区210,二者被定义为LDMOS的源端;漏极271用于引出漏区270,二者被定义为LDMOS的漏端。在优选实例中,源区210和漏区270的N型掺杂浓度范围可以为1×1018/cm3至1×1022/cm3,例如掺杂浓度设置为1×1020/cm3
在衬底200上,形成了P阱的体区220,同时还形成了漂移区250。在优选实例中,体区220的掺杂浓度范围可以为1×1015/cm3至1×1018/cm3,例如掺杂浓度设置为1×1017/cm3。对于N沟道LDMOS,漂移区250为N型掺杂(如图所示N阱),其掺杂浓度一般地低于漏区270的掺杂浓度,在优选实施例中,漂移区250掺杂浓度范围可以为1×1015/cm3至1×1018/cm3,例如掺杂浓度设置为5×1016/cm3
继续如图2所示,在衬底200表面、源端和漏端之间形成栅介质层230,具体地,其可以通过构图氧化形成,当然,也可以通过薄膜沉积等方法构图形成。在漂移区250上,采用LOCOS工艺构图氧化形成场氧化层260。在栅介质层230上构图形成栅极240,如图2示意,栅极240可以覆盖靠近栅介质层230的部分场氧化层260。栅极240具体材料不受本发明限制,例如,其可以为低电阻率的多晶硅构图形成。
继续如图2所示,在场氧化层260上,构图形成有场区辅助电极280,场区辅助电极280相对靠近漏区270设置,需要理解的是,场区辅助电极280的位置相对于场氧化层260两旁的栅介质层230和漏区270来定义的,在本发明中,“相对靠近漏区270”可以理解为场区辅助电极280与漏区270的距离小于或等于场区辅助电极280与场氧化层260的距离,例如,场区辅助电极280置于场氧化层260的中心线261的右边(即漏区一旁);场区辅助电极280可以选择低电阻率的多晶硅构图形成。
对于N沟道LDMOS20,在其处于开态时,Vds大于零,也即漏端偏置正向电压、源端偏置在0伏;同时,将场区辅助电极280偏置正向电压时(与漏区偏置的电压方向相同,均为正),场区辅助电极280大致下方所对应的漂移区将被增强,N型杂质浓度将大大上升(电子浓度增加),因此,场区辅助电极280下方区域的杂质浓度相对较高。随着Vds的增大,在漂移区的耗尽层向漏区270靠近的过程中,当耗尽层耗尽到该下方区域时,该区域的电力线将更加密集,电场相对更高,从而能导致耗尽层进一步向漏区280耗尽,也即耗尽层很难向高掺杂的漏区280边界扩展。因此,能降低漏区280与漂移区250交接处的电场,避免其因Vds的增大而导致大电场条件下的碰撞电离发生,开态下的崩溃电压得到大大提高。
在一优选实例中,场区辅助电极280偏置与漏端相同方向且相同大小的电压,例如,漏极270和场区辅助电极280连接在同一电压源上,这样减少相应电源的设计,有利于减少LDMOS的外围电路。
图3所示为LDMOS的输出特性曲线示意图。其中,曲线11为图1所示实施例LDMOS的转移特性曲线,曲线21为图2所示实施例LDMOS的转移特性曲线(场区辅助电极280与漏端偏置相同电压)。对比曲线11和21,对于曲线11,当Vds达到35伏左右时,Ids开始快速上升,表明在漏区180与漂移区150交接处开始发生碰撞电离;对于曲线21,Vds达到41伏左右时,Ids才开始快速上升,表明在漏区280与漂移区250交接处开始发生碰撞电离。因此,开态下的崩溃电压得到大大提高。在崩溃电压得到提高的情况下,LDMOS20相对LDMOS10的工作电压提高,例如,LDMOS20可以在Vds=38V下工作。
继续如图2所示,场区辅助电极280相对靠近漏区270设置时,其相对漏区270的距离优选地为场氧化层260的长度(沟道方向上的长度)的5%至25%,例如,10%。场区辅助电极280的面积相对场氧化层260的面积较小,其面积大小范围为场氧化层260的面积的5%至25%,例如,10%。场区辅助电极280为多晶硅时,其可以为P型掺杂也可以为N型掺杂,其电阻率较低,具体地,可以与多晶硅的栅极240同步地构图形成(但是,二者不能连接在一起),场区辅助电极280的具体厚度以及掺杂浓度不受本发明实施例限制。场区辅助电极280偏置的电压也不受以上实施例限制,例如,其还可以偏置其他的正向电压,例如+10V等。
在其它实施例中,场区辅助电极280可以多段地设置(图2中一段设置),每段场区辅助电极280均相对靠经漏区270设置。每段场区辅助电极280的作用原理与以上实施例中的场区辅助电极280的作用原理基本一致。
图4所示为按照本发明又一实施例提供的LDMOS的基本截面结构示意图。相比于图2所示实施例,其主要区别在于,漏极271向场氧化层260之上延伸,从而在场氧化层260之上的部分电极被定义为场区辅助电极380,因此场区辅助电极380相对于漏极271一体化地设置,这样,容易使LDMOS在开态时、场区辅助电极与漏极或漏区偏置相同电压,结构相对更简单,也更容易制备。在该实施例中,场区辅助电极380与漏极271采用相同的材料,例如,金属或金属硅化物(salicide)电极。
以上实施例所揭示的LDMOS均为N沟道LDMOS,本领域技术人员根据以上教导提出结构相似的P沟道LDMOS,在此不再一一示例;需要理解的是,P沟道LDMOS的场区辅助电极与漏区在开态是偏置负向的电压以提高场区辅助电极之下大致对应的漂移区区域的杂质浓度。
以上例子主要说明了本发明的LDMOS。尽管只对其中一些本发明的实施方式进行了描述,但是本领域普通技术人员应当了解,本发明可以在不偏离其主旨与范围内以许多其他的形式实施。因此,所展示的例子与实施方式被视为示意性的而非限制性的,在不脱离如所附各权利要求所定义的本发明精神及范围的情况下,本发明可能涵盖各种的修改与替换。

Claims (11)

1.一种横向双扩散金属氧化物半导体场效应晶体管,包括源区、栅介质层、漏区、设置在漏区和栅介质层之间的漂移区、设置在漂移区之上的场氧化层、基本设置在栅介质层之上的栅极,其特征在于,在所述场氧化层的相对靠近所述漏区的部分之上设置有用于提高所述横向双扩散金属氧化物半导体场效应晶体管在开态下的崩溃电压的场区辅助电极,所述场区辅助电极与所述漏区上的漏极分离地设置。
2.如权利要求1所述的横向双扩散金属氧化物半导体场效应晶体管,其特征在于,在开态时,所述场区辅助电极被偏置与所述漏区所偏置的电压方向相同的电压。
3.如权利要求2所述的横向双扩散金属氧化物半导体场效应晶体管,其特征在于,所述场区辅助电极与所述漏区偏置相同大小的电压。
4.如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管,其特征在于,所述场区辅助电极与所述漏区之间的距离为所述场氧化层的长度的5%至25%。
5.如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管,其特征在于,所述场区辅助电极与所述栅极均为多晶硅电极,所述场区辅助电极和所述栅极同步地构图形成。
6.如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管,其特征在于,所述漂移区与所述漏区同类型掺杂,并且,所述漂移区低于所述漏区掺杂浓度。
7.如权利要求6所述的横向双扩散金属氧化物半导体场效应晶体管,其特征在于,所述漂移区的掺杂浓度范围为1×1015/cm3至1×1018/cm3
8.如权利要求6所述的横向双扩散金属氧化物半导体场效应晶体管,其特征在于,所述漏区的掺杂浓度范围为1×1018/cm3至1×1022/cm3
9.如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管,其特征在于,所述场区辅助电极以一段或多段的形式设置于所述场氧化层之上。
10.如权利要求1所述的横向双扩散金属氧化物半导体场效应晶体管,其特征在于,所述场区辅助电极与所述漏极为金属或金属硅化物材料制成。
11.如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管,所述横向双扩散金属氧化物半导体场效应晶体管为N沟道横向双扩散金属氧化物半导体场效应晶体管,所述电压方向为正向。
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