CN106384747B - 一种场效应管 - Google Patents

一种场效应管 Download PDF

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CN106384747B
CN106384747B CN201611051951.7A CN201611051951A CN106384747B CN 106384747 B CN106384747 B CN 106384747B CN 201611051951 A CN201611051951 A CN 201611051951A CN 106384747 B CN106384747 B CN 106384747B
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CN106384747A (zh
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李风浪
李舒歆
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Huzhou Qiqi Electromechanical Technology Co., Ltd
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Dongguan Lianzhou Intellectual Property Operation and Management Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

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  • Power Engineering (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

本发明涉及半导体技术领域,特别涉及一种场效应管,包括半导体衬底;形成在半导体衬底正面的漂移区;依次形成在漂移区表面上的栅绝缘层和多晶硅栅极;依次形成在漂移区表面内的体区和位于体区内的源区,体区和源区位于多晶硅栅极的两侧;形成在源区表面的源极金属层;形成在半导体衬底背面的漏极金属层,漂移区与多晶硅栅极间增加绝缘介质区,进而增加多晶硅栅极和漂移区间距,减小栅漏寄生电容,提高开关速度。

Description

一种场效应管
技术领域
本发明涉及半导体技术领域,特别涉及一种场效应管。
技术背景
近年来,随着微电子技术的迅猛发展,以及汽车电子、航空航天、工业控制、电力运输等相关领域的迫切需求,发展新型大功率半导体器件越来越多的受到人们关注。垂直双扩散金属氧化物半导体场效应管(VDMOS)因具有开关损耗小、输入阻抗高、驱动功率小、频率特性好、跨导高度线性等优点,被越来越广泛地应用在模拟电路和驱动电路中,尤其是高压功率部分。
现有的VDMOS结构包括:半导体衬底;形成在半导体衬底正面的漂移区;依次形成在漂移区表面上的栅绝缘层和多晶硅栅极;依次形成在漂移区表面的体区和位于体区内的源区,体区和源区位于多晶硅栅极的两侧;形成在源区表面的源极金属层;形成在半导体衬底背面的漏极金属层。由于栅绝缘层两侧分别为导电的多晶硅栅极和漂移区,因此会形成栅漏寄生电容,影响场效应管开关性能。
发明内容
本发明的目的是提供一种场效应管,有效减小栅漏寄生电容,提高开关速度。
为实现上述目的,本发明采用以下通过调整多晶硅栅极和漂移区间距,减小栅漏寄生电容的技术方案:
一种场效应管,包括半导体衬底;形成在半导体衬底正面的漂移区;依次形成在漂移区表面上的栅绝缘层和多晶硅栅极;依次形成在漂移区表面内的体区和位于体区内的源区,体区和源区位于多晶硅栅极的两侧;形成在源区表面的源极金属层;形成在半导体衬底背面的漏极金属层,所述体区包括第一体区与第二体区两部分,第一体区多数载流子浓度大于第二体区多数载流子浓度,所述栅绝缘层与所述第二体区接触,所述栅绝缘层与漂移区之间形成绝缘介质区,所述绝缘介质区两侧与所述第二体区接触,所述绝缘介质区厚度不小于所述第二体区厚度。
优选的,所述绝缘介质区的介电常数小于栅绝缘层。
优选的,所述绝缘介质区厚度等于所述第二体区厚度。
可选的,所述绝缘介质区材料为氧化硅、氮化硅或氮氧化硅。
可选的,所述半导体衬底和漂移区为n型半导体,体区为p型半导体,源区为n型半导体。
可选的,所述半导体衬底为硅衬底。
可选的,所述绝缘介质区通过在漂移区上表面氧离子注入形成。
可选的,所述绝缘介质区通过刻蚀漂移区上表面后化学气相沉积形成。
另一种场效应管,包括半导体衬底;形成在半导体衬底正面的漂移区;依次形成在漂移区表面上的栅绝缘层和多晶硅栅极;依次形成在漂移区表面内的体区和位于体区内的源区,体区和源区位于多晶硅栅极的两侧;形成在源区表面的源极金属层;形成在半导体衬底背面的漏极金属层,所述栅绝缘层与多晶硅栅极之间形成绝缘介质区,所述绝缘介质区形成在栅绝缘层中部上,与栅绝缘层下的漂移区相对,所述多晶硅栅极形状呈向下的凹型。
另一种场效应管,包括半导体衬底;形成在半导体衬底正面的漂移区;依次形成在漂移区表面上的栅绝缘层和多晶硅栅极;依次形成在漂移区表面内的体区和位于体区内的源区,体区和源区位于多晶硅栅极的两侧;形成在源区表面的源极金属层;形成在半导体衬底背面的漏极金属层,所述栅绝缘层与漂移区之间形成绝缘介质区,所述绝缘介质区与体区不接触。
相对于现有技术,本发明具有以下优点:
本发明一种场效应管,栅绝缘层与漂移区之间形成绝缘介质区,增加了多晶硅栅极和漂移区之间的距离,有效减小栅漏寄生电容。体区包括第一体区与第二体区两部分,第一体区多数载流子浓度大于第二体区多数载流子浓度,所述栅绝缘层与所述第二体区接触,所述绝缘介质区两侧与所述第二体区接触,场效应管导通时,第二体区多数载流子浓度小于第一体区,可快速感应出反型层,引导第一体区感应出导电沟道,场效应管截止时由于第二体区与绝缘介质区接触,可减小漏电流,增加击穿电压。
另一种场效应管,所述栅绝缘层与多晶硅栅极之间形成绝缘介质区,所述绝缘介质区形成在栅绝缘层中部上,与栅绝缘层下的漂移区相对,所述多晶硅栅极形状呈向下的凹型,增加了多晶硅栅极和漂移区之间的距离,有效减小栅漏寄生电容。
另一种场效应管,所述栅绝缘层与漂移区之间形成绝缘介质区,所述绝缘介质区与体区不接触,增加了多晶硅栅极和部分漂移区之间的距离,有效减小栅漏寄生电容。
附图说明
图1为本发明第一实施例的场效应管剖面结构示意图;
图2为本发明第二实施例的场效应管剖面结构示意图;
图3为本发明第三实施例的场效应管剖面结构示意图。
具体实施方式
为了更好地理解本发明,下面结合附图以及实施例对本发明作进一步介绍,实施例仅限于解释本发明,并不对本发明构成任何限定。
第一实施例
如图1所示,本实施例场效应管,包括半导体衬底10;形成在半导体衬底正面的漂移区20;依次形成在漂移区20表面上的栅绝缘层30和多晶硅栅极40;依次形成在漂移区20表面内的体区50和位于体区50内的源区60,体区50和源区60位于多晶硅栅极40的两侧;形成在源区60表面的源极金属层70;形成在半导体衬底10背面的漏极金属层80,所述体区50包括第一体区51与第二体区52两部分,第一体区51多数载流子浓度大于第二体区52多数载流子浓度,所述栅绝缘层30与所述第二体区52接触,所述栅绝缘层30与漂移区20之间形成绝缘介质区90,所述绝缘介质区90两侧与所述第二体区52接触,所述绝缘介质区90厚度不小于所述第二体区52厚度。
本实施例所述衬底10为高掺杂浓度的n型硅衬底,漂移区20为低掺杂浓度的n型硅外延层。
本实施例绝缘介质区90形成在栅绝缘层30与漂移区20之间,增加了多晶硅栅极40与漂移区20之间的距离,可有效减小栅漏寄生电容,提高开关速度,绝缘介质区90材料可为氧化硅、氮化硅或氮氧化硅,优选的,所述绝缘介质区90的介电常数小于栅绝缘层30,进一步减小寄生电容值。绝缘介质区90可有多种不同的形成方式,可通过在漂移区20上表面氧离子注入形成或通过刻蚀漂移区20上表面后化学气相沉积形成。本实施例所述绝缘介质区厚度等于所述第二体区厚度。
本实施例漂移区20表面掺杂p型杂质元素,如硼,形成第一体区51,在第一体区51内重掺杂n型杂质元素,如磷或砷,形成源区60,在第一体区51靠近栅绝缘层90一侧轻掺杂n型杂质元素,如磷或砷,形成第二体区52,第二体区52空穴浓度低于第一体区51空穴浓度,场效应管导通时,第二体区52多数载流子浓度小于第一体区,可快速感应出反型层,引导第一体区51感应出导电沟道,场效应管截止时由于第二体区52与绝缘介质区接触,可减小漏电流,增加击穿电压。
第二实施例
如图2所示,本实施例场效应管,包括半导体衬底10;形成在半导体衬底正面的漂移区20;依次形成在漂移区20表面上的栅绝缘层30和多晶硅栅极40;依次形成在漂移区20表面内的体区50和位于体区50内的源区60,体区50和源区60位于多晶硅栅极40的两侧;形成在源区60表面的源极金属层70;形成在半导体衬底10背面的漏极金属层80,所述栅绝缘层30与多晶硅栅极40之间形成绝缘介质区90,所述绝缘介质区90形成在栅绝缘层30中部上,与栅绝缘层30下的漂移区20相对,所述多晶硅栅极40形状呈向下的凹型,多晶硅栅极和漂移区之间的距离增加,有效减小栅漏寄生电容,绝缘介质区90以及栅绝缘层30材料可为氧化硅、氮化硅或氮氧化硅,优选的,所述绝缘介质区90的介电常数小于栅绝缘层30,进一步减小寄生电容值。
第三实施例
如图3所示,本实施例场效应管,包括半导体衬底10;形成在半导体衬底正面的漂移区20;依次形成在漂移区20表面上的栅绝缘层30和多晶硅栅极40;依次形成在漂移区20表面内的体区50和位于体区50内的源区60,体区50和源区60位于多晶硅栅极40的两侧;形成在源区60表面的源极金属层70;形成在半导体衬底10背面的漏极金属层80,所述栅绝缘层70与漂移区20之间形成绝缘介质区90,所述绝缘介质区90与体区50不接触,增加了多晶硅栅极40和部分漂移区20之间的距离,有效减小栅漏,绝缘介质区90以及栅绝缘层30材料可为氧化硅、氮化硅或氮氧化硅,优选的,所述绝缘介质区90的介电常数小于栅绝缘层30,进一步减小寄生电容值。

Claims (8)

1.一种场效应管,包括半导体衬底;形成在半导体衬底正面的漂移区;依次形成在漂移区表面上的栅绝缘层和多晶硅栅极;依次形成在漂移区表面内的体区和位于体区内的源区,体区和源区位于多晶硅栅极的两侧;形成在源区表面的源极金属层;形成在半导体衬底背面的漏极金属层,其特征在于:所述体区包括第一体区与第二体区两部分,第一体区多数载流子浓度大于第二体区多数载流子浓度,所述栅绝缘层与所述第二体区接触,所述栅绝缘层与漂移区之间形成绝缘介质区,所述绝缘介质区两侧与所述第二体区接触,所述绝缘介质区厚度不小于所述第二体区厚度。
2.根据权利要求1所述的场效应管,其特征在于:所述绝缘介质区的介电常数小于栅绝缘层。
3.根据权利要求1所述的场效应管,其特征在于:所述绝缘介质区厚度等于所述第二体区厚度。
4.根据权利要求1所述的场效应管,其特征在于:所述绝缘介质区材料为氧化硅、氮化硅或氮氧化硅。
5.根据权利要求1所述的场效应管,其特征在于:所述半导体衬底和漂移区为n型半导体,体区为p型半导体,源区为n型半导体。
6.根据权利要求1所述的场效应管,其特征在于:所述半导体衬底为硅衬底。
7.根据权利要求6所述的场效应管,其特征在于:所述绝缘介质区通过在漂移区上表面氧离子注入形成。
8.根据权利要求1所述的场效应管,其特征在于:所述绝缘介质区通过刻蚀漂移区上表面后化学气相沉积形成。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101692462A (zh) * 2009-10-14 2010-04-07 上海宏力半导体制造有限公司 一种垂直双扩散mos晶体管结构
CN102456738A (zh) * 2010-10-29 2012-05-16 上海宏力半导体制造有限公司 一种vdmos晶体管
CN102468334A (zh) * 2010-11-19 2012-05-23 无锡华润上华半导体有限公司 Vdmos器件及其制造方法

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JP4191025B2 (ja) * 2003-12-22 2008-12-03 Necエレクトロニクス株式会社 縦型misfet

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101692462A (zh) * 2009-10-14 2010-04-07 上海宏力半导体制造有限公司 一种垂直双扩散mos晶体管结构
CN102456738A (zh) * 2010-10-29 2012-05-16 上海宏力半导体制造有限公司 一种vdmos晶体管
CN102468334A (zh) * 2010-11-19 2012-05-23 无锡华润上华半导体有限公司 Vdmos器件及其制造方法

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