CN102593178B - 具有超结结构的半导体器件及其制作方法 - Google Patents

具有超结结构的半导体器件及其制作方法 Download PDF

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CN102593178B
CN102593178B CN201210057865.2A CN201210057865A CN102593178B CN 102593178 B CN102593178 B CN 102593178B CN 201210057865 A CN201210057865 A CN 201210057865A CN 102593178 B CN102593178 B CN 102593178B
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CN102593178A (zh
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马荣耀
李铁生
唐纳德·迪斯尼
张磊
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

公开了一种具有超结结构的半导体器件及其制作方法。该半导体器件包括在晶片上形成的基本上矩形的第一区和在第一区外围的第二区，在所述第一区中设置沟槽栅极金属氧化物半导体(MOSFET)单元的多个沟槽区和多个立柱，其中相邻的沟槽区被立柱隔开，在沟槽区和立柱之间形成本体区，在所述第二区中形成沿着第一区的相应边延伸的多个立柱，其中，在所述第二区的角落中，多个横向立柱的端部与多个竖向立柱的端部分开并彼此交错。上述方案通过将转角处立柱之间形成为交错结构并在它们之间保持一定间距实现了在转角处的电荷平衡，从而避免了此处击穿的最先发生，从而提高了器件的耐压。

Description

具有超结结构的半导体器件及其制作方法
技术领域
本技术涉及半导体技术，具体涉及但不限于一种具有超结结构的半导体器件及其制作方法。
背景技术
超结(SJ：SuperJunction)结构可以降低Ron(导通电阻)*A(面积)，因此超结结构在小尺寸的器件中应用广泛。图1示出了现有技术的超结器件的俯视图。超结器件通常包括在晶片上形成的原胞区和端接区。在原胞区中形成半导体器件的主要部分，在端接区中引出半导体器件的端子。
对于超结器件，由于在转角(角落)处p型或n型立柱(深阱)的电荷不平衡，容易在超结器件晶片上的角落处导致击穿，如图1中的虚线框部分。图2A和图2B示出了图1所示的超结器件在角落处的放大图。图2A所示为传统的弧形P型立柱布局图，图2B所示为传统的另一种P型立柱布局图，垂直结合P型立柱布局。此外，由于不容易在原胞区的边缘部分中布置栅极沟槽和p型立柱，因此电荷平衡存在问题。因此，需要改善超结器件的电荷平衡。
发明内容
考虑到现有技术中的一个或多个问题，提出了一种具有超结结构的半导体器件及其制作方法。
根据本技术的实施例，提出了一种具有超结结构的半导体器件，包括在晶片上形成的基本上矩形的第一区和在第一区外围的第二区，在所述第一区中设置沟槽栅极金属氧化物半导体(MOSFET)单元的多个沟槽区和多个立柱，其中相邻的沟槽区被立柱隔开，在沟槽区和立柱之间形成本体区，在所述第二区中形成沿着第一区的相应边延伸的多个立柱，其中，在所述第二区的角落中，多个横向立柱的端部与多个竖向立柱的端部分开并彼此交错。
根据本技术的实施例，还提出了一种制作半导体器件的方法，包括步骤：提供一晶片；在晶片上形成的基本上矩形的第一区和在第一区外围的第二区，在所述第一区中设置沟槽栅极金属氧化物半导体(MOSFET)单元的多个沟槽区和多个立柱，其中相邻的沟槽区被立柱隔开，在沟槽区和立柱之间形成本体区，在所述第二区中形成沿着第一区的相应边延伸的多个立柱，其中，在所述第二区的角落中，多个横向立柱的端部与多个竖向立柱的端部分开并彼此交错。
利用本技术的方案，上述实施例通过将转角处立柱之间形成为交错结构并在它们之间保持一定间距实现了在转角处的电荷平衡，从而避免了此处击穿的最先发生，从而提高了器件的耐压。
附图说明
下面的附图表明了本技术的实施方式。这些附图和实施方式以非限制性、非穷举性的方式提供了本技术的一些实施例，其中：
图1是根据现有技术的超结器件的俯视图；
图2A是如图1所示的超结器件的角落处的示意图；
图2B是如图1所示的超结器件的角落处的另一示意图；
图3示意性地示出了根据本技术实施例的半导体器件的俯视图以及角落处的放大图；
图4示意性地示出了根据本技术实施例的半导体器件的俯视图以及原胞区域边缘处的放大图；
图5示意性地示出了沿着图4所示的俯视图中的A-A′线的横截面视图；以及
图6示意性地示出了根据本技术的实施例的制作方法的流程图。
具体实施方式
下面将阐述本技术的一些实施例，这些实施例涉及具有超结的半导体器件及其制作方法。另外，下面还将具体描述半导体器件的衬底的一些实施例。在本技术中，“衬底”包括但是并不局限于各种晶片，例如单个集成电路晶片，传感器晶片，开关晶片以及其他具有半导体性能的晶片。附图中以及下文将对某些实施例中的许多具体细节进行详细说明，以帮助读者透彻领会本技术的实施例。某些其他的实施例可能在构造、成分或者工艺流程方面与本技术披露的实施例有所不同，但是本领域的技术人员应该理解，在没有附图所示的实施例或者其他细节、方法、材料等的情况下，本技术的实施例也是可以实现的。
图3示意性地示出了根据本技术实施例的半导体器件300的俯视图和角落部分的放大图。在下面的讨论中，以功率器件为例进行说明，但是本领域的技术人员应该理由本技术并不局限于功率器件，也可以用在其他需要缩小器件尺寸的垂直结构器件中。
如图3所示，该实施例的半导体器件300包括原胞区(MainCellRegion)310和端接区(TerminationRegion)320。通常，在原胞区310中形成垂直结构的半导体器件的主要部分，在端接区320中引出半导体器件的端子。在图3所示的半导体器件300俯视图中，原胞区310和端接区320是基本上矩形形状，但是本领域的技术人员应该理解，也可以采用其他的形状，例如正方形等。
如图3右侧的放大图所示，晶片上的超结器件包括第一区FR，以及构成第二区的中间区IR和外围区PR，其中第一区FR和中间区IR构成原胞区310，外围区PR构成端接区320。但是，如本领域的技术人员理解的那样，根据另外的实施例，第一区FR也可以构成原胞区，中间区IR和外围区PR构成端接区。
根据一个实施例，在第一区FR中设置沟槽栅极金属氧化物半导体(MOSFET)单元的多个沟槽区330和多个立柱340，如图4所示。相邻的沟槽区被立柱隔开，在沟槽区和立柱之间形成本体区。在中间区IR和外围区PR中形成沿着第一区的相应边延伸的多个立柱，其中，在所述第二区的角落中，多个横向立柱的端部与多个竖向立柱的端部分开并彼此交错。第一区中立柱间距与中间区中立柱间距相同，都为L1。
根据一个实施例，在第二区的角落中，每个横向立柱的端部与垂直于该横向立柱的两个竖向立柱分开第一距离，该第一距离基本上为所述两个竖向立柱间距的一半。例如，在中间区IR中，每个横向立柱的端部与垂直于该横向立柱的两个竖向立柱分开了所述两个竖向立柱间距L1的一半。再如，在外围区PR中，每个横向立柱的端部与垂直于该横向立柱的两个竖向立柱分开了所述两个竖向立柱间距L2的一半。
在低电压的超结器件中，由于P型立柱比较浅，与P型立柱的电荷相比，P型体区的电荷是不可忽略的。如果在端接区320中保持立柱间距与原胞区310中的立柱间距相同，则电荷不平衡。所以，将端接区320中立柱之间的间距设置为比原胞区310中的立柱间距L1小的L2。
但是，如本领域的技术人员能够理解的那样，在高电压的超结器件中，中间区IR中立柱的间距与外围区PR中立柱的间距相同。
图4右侧的放大图中示出了左侧图中跨在原胞区310和端接区320的一小块正方形区域的具体结构。如图所示，在原胞区310中，栅极沟槽330与P型柱(或N型柱)140交替形成，也就是立柱将沟槽型MOSFET单元的各个栅极沟槽隔开。
在原胞区310的边缘处，将第一区中的横向立柱的端部与中间区IR中的竖向立柱之间的距离设置为第一区中横向立柱的间距的大约一半。
图5示意性地示出了沿着图1所示的俯视图中的A-A′线的横截面视图。如图5所示，根据该实施例的半导体器件500包括半导体衬底502，形成在半导体衬底502背侧的金属层501，形成在半导体衬底502上的外延层503，在外延层503中形成的立柱504，以及在立柱之间的外延层中形成的沟槽MOSFET单元。
外延层503的顶部形成为本体区507，半导体衬底503形成为漏极区。该沟槽MOSFET单元包括在本体区507中形成的源区508和浅沟槽栅极，栅极槽深大约为立柱间距的二分之一以下，最好在三分之一以下，从而降低栅极沟槽密度，使得栅极电容Qg降低。
根据另一实施例，该浅沟槽栅极的沟槽侧壁和底部沉积有厚氧化物层并且该浅沟槽填充有多晶硅506。
根据该实施例，在栅极沟槽上方形成栅极氧化物层509和作为源极的金属层510，并开孔通过导电通路建立栅极多晶硅到外部的连接。另外，在半导体衬底的背侧形成的金属层501作为漏极。
在该实施例中，本体区507也可以占据立柱504的上部。例如，相邻的沟槽MOSFET单元的本体区彼此相连接。但是，根据本技术的另一实施例，立柱504也可以将相邻的沟槽MOSFET单元的本体区507隔开。本体区507形成为浅本体区并且是轻掺杂的。根据本技术的再一实施例，对本体区进行两次轻掺杂注入。
根据上述实施例的超结器件，实现了Ron*Qg的极大降低。另外，该技术利用改进的超结技术，还减小了Ron*A。因此，该实施例的半导体器件适用于中高压高速电路领域。
为了提高立柱的浓度分布，在本技术的一些实施例中，立柱504是通过对外延层503多次注入形成的，最深的那次注入操作的剂量比其他次注入操作的剂量大。例如，最深的那次注入操作的剂量为其他次剂量的105％～110％。这样能够为立柱504的底部提供更多电荷来进行底部电荷补偿。在一些实施例中，外延层503是通过多次外延生长形成的，并且每次外延后进行多次注入操作。这样能够在立柱中形成较为优良的浓度分布。根据本发明的另外一些实施例，多次外延生长的厚度不同，首次外延生长的厚度大于后续外延生长的厚度。
图6示意性地示出了根据本技术的实施例的制作方法600的流程图。如图6所示，根据本发明的实施例的制作半导体器件的方法例如包括：
在601，提供一晶片；
在602，在晶片上形成的基本上矩形的第一区和在第一区外围的第二区，
在603，在第一区中设置沟槽栅极金属氧化物半导体(MOSFET)单元的多个沟槽区310和多个立柱320，其中相邻的沟槽区被立柱隔开，
在604，在沟槽区和立柱之间形成本体区，在第二区中形成沿着第一区的相应边延伸的多个立柱。在第二区的角落中，多个横向立柱的端部与多个竖向立柱的端部分开并彼此交错。
根据另外的实施例，在第二区的角落中，每个横向立柱的端部与垂直于该横向立柱的两个竖向立柱分开第一距离，该第一距离基本上为两个竖向立柱间距L2的一半。
根据其他实施例，第一区中的立柱的端部与第二区中垂直于该第一区中立柱的立柱分开了L1的一半。
针对传统超结器件因为在转角处很难实现N型立柱和P型立柱之间的电荷平衡而因此的击穿问题，上述实施例通过将转角处立柱之间形成为交错(stagger)结构并在它们之间保持一定间距实现了在转角处的电荷平衡，从而避免了此处击穿的最先发生，从而提高了器件的耐压。
尽管本发明已经提出了一些实施例，但是这并不应该是对本技术的限制。本领域的技术人员在阅读上述实施例后，可以掌握其他各种变化或者变型。例如，尽管上述实施例使用的是n-沟道器件，但是通过改变半导体区域的导电型，就可以将本技术应用于p-沟道器件。因此，权利要求中所覆盖的各种变化或者变型都属于本技术的保护范围。
虽然已参照几个典型实施例描述了本技术，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本技术能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (8)

1.一种具有超结结构的半导体器件，包括在晶片上形成的矩形的第一区和在第一区外围的第二区，在所述第一区中设置沟槽栅极金属氧化物半导体(MOSFET)单元的多个沟槽区和多个立柱，其中相邻的沟槽区被立柱隔开，在沟槽区和立柱之间形成本体区，在所述第二区中形成沿着第一区的相应边延伸的多个立柱，其中，在所述第二区的角落中，多个横向立柱的端部与多个竖向立柱的端部分开并彼此交错，每个横向立柱的端部与垂直于该横向立柱的两个竖向立柱分开的距离为所述两个竖向立柱间距的一半。
2.如权利要求1所述的半导体器件，其中第一区中的立柱的端部与第二区中垂直于该第一区中立柱的立柱分开了第一距离，该第一距离为所述第二区的角落中垂直于横向立柱的两个竖向立柱间距的一半。
3.如权利要求1所述的半导体器件，其中，第二区包括靠近第一区的中间区和远离第一区的外围区，在中间区中形成的立柱之间的间距大于在外围区中形成的立柱之间的间距。
4.如权利要求3所述的半导体器件，其中，在所述中间区的角落中，每个横向立柱的端部与垂直于该横向立柱的两个竖向立柱分开第一距离，该第一距离为所述两个竖向立柱间距的一半。
5.如权利要求3所述的半导体器件，其中，在所述外围区的角落中，每个横向立柱的端部与垂直于该横向立柱的两个竖向立柱分开第二距离，该第二距离为所述两个竖向立柱间距的一半。
6.如权利要求3所述的半导体器件，其中第一区和中间区构成所述半导体器件的原胞区，所述外围区构成所述半导体器件的端接区。
7.一种制作半导体器件的方法，包括步骤：
提供一晶片；
在晶片上形成的基本上矩形的第一区和在第一区外围的第二区，
在所述第一区中设置沟槽栅极金属氧化物半导体(MOSFET)单元的多个沟槽区和多个立柱，其中相邻的沟槽区被立柱隔开，在沟槽区和立柱之间形成本体区，
在所述第二区中形成沿着第一区的相应边延伸的多个立柱，
其中，在所述第二区的角落中，多个横向立柱的端部与多个竖向立柱的端部分开并彼此交错，每个横向立柱的端部与垂直于该横向立柱的两个竖向立柱分开的距离为所述两个竖向立柱间距的一半。
8.如权利要求7所述的方法，其中第一区中的立柱的端部与第二区中垂直于该第一区中立柱的立柱分开了第一距离该第一距离为所述第二区的角落中垂直于横向立柱的两个竖向立柱间距的一半。
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