TW201347188A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201347188A
TW201347188A TW102107864A TW102107864A TW201347188A TW 201347188 A TW201347188 A TW 201347188A TW 102107864 A TW102107864 A TW 102107864A TW 102107864 A TW102107864 A TW 102107864A TW 201347188 A TW201347188 A TW 201347188A
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TWI525819B (zh
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rong-yao Ma
Tiesheng Li
Donald Disney
Lei Zhang
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Monolithic Power Systems Inc
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Abstract

揭示一種具有超接面結構的半導體裝置及其製造方法。該半導體裝置包括在晶片上形成的基本上為矩形的第一區和在第一區之週邊的第二區，在該第一區中設置溝槽閘極金屬氧化物半導體(MOSFET)單元的多個溝槽區和多個立柱，其中，相鄰的溝槽區被立柱所隔開，在溝槽區與立柱之間形成本體區，在該第二區中形成沿著第一區的相應邊而延伸的多個立柱，其中，在該第二區的角落中，多個橫向立柱的端部與多個豎向立柱的端部被分開且彼此交錯的。該方案透過將轉角處立柱之間形成為交錯結構並在它們之間保持一定間距而實現了在轉角處的電荷平衡，從而避免了此處擊穿的最先發生，因而提高了裝置的耐壓。

Description

半導體裝置及其製造方法
本發明係有關半導體技術，具體上係有關但不限於一種具有超接面結構的半導體裝置及其製造方法。
超接面(SJ：Super Junction)結構可以降低Ron(導通電阻)*A(面積)，因此，超接面結構在小尺寸的裝置中應用廣泛。圖1示出了現有技術的超接面裝置的俯視圖。超接面裝置通常包括在晶片上形成的主單元區和端接區。在主單元區中形成半導體裝置的主要部分，在端接區中引出半導體裝置的端子。
對於超接面裝置，由於在轉角(角落)處之p型或n型立柱(深井)的電荷不平衡，容易在超接面裝置晶片上的角落處導致擊穿，如圖1中的虛線框部分。圖2A和圖2B示出了圖1所示的超接面裝置在角落處的放大圖。圖2A所示為傳統的弧形P型立柱佈局圖，圖2B所示為傳統的另一種P型立柱佈局圖，垂直結合P型立柱佈局。此外，由於不容易在主單元區的邊緣部分中配置閘極溝槽和p型立柱，因此電荷平衡存在有問題。因此，需要改善超 接面裝置的電荷平衡。
考慮到現有技術中的一個或多個問題，提出了一種具有超接面結構的半導體裝置及其製造方法。
根據本發明的實施例，提出了一種具有超接面結構的半導體裝置，包括在晶片上形成之基本上為矩形的第一區和在第一區之週邊的第二區，在所述第一區中設置溝槽閘極金屬氧化物半導體(MOSFET)單元的多個溝槽區和多個立柱，其中，相鄰的溝槽區被立柱所隔開，在溝槽區與立柱之間形成本體區，在所述第二區中形成沿著第一區的相應邊而延伸的多個立柱，其中，在所述第二區的角落中，多個橫向立柱的端部與多個豎向立柱的端部被分開且彼此交錯。
根據本發明的實施例，還提出了一種半導體裝置的製造方法，包括步驟：提供一晶片；在晶片上形成基本上為矩形的第一區和在第一區之週邊的第二區，在所述第一區中設置溝槽閘極金屬氧化物半導體(MOSFET)單元的多個溝槽區和多個立柱，其中，相鄰的溝槽區被立柱所隔開，在溝槽區與立柱之間形成本體區，在所述第二區中形成沿著第一區的相應邊而延伸的多個立柱，其中，在所述第二區的角落中，多個橫向立柱的端部與多個豎向立柱的端部被分開且彼此交錯。
利用本發明的方案，上述實施例透過將轉角處的立柱 之間形成為交錯結構並在它們之間保持一定間距而實現了在轉角處的電荷平衡，從而避免了此處擊穿的最先發生，因而提高了裝置的耐壓。
300‧‧‧半導體裝置
310‧‧‧主單元區
320‧‧‧端接區
330‧‧‧溝槽區
340‧‧‧立柱
500‧‧‧半導體裝置
501‧‧‧金屬層
502‧‧‧半導體基板
503‧‧‧外延層
504‧‧‧深井
505‧‧‧閘極氧化物層
506‧‧‧多晶矽
507‧‧‧本體區
508‧‧‧源極區
509‧‧‧閘極氧化物層
510‧‧‧金屬層
FR‧‧‧第一區
IR‧‧‧中間區
PR‧‧‧週邊區
下面的附圖表現了本發明的實施方式。這些附圖和實施方式以非限制性、非窮舉性的方式而提供了本發明的一些實施例，其中：圖1是依據現有技術的超接面裝置的俯視圖；圖2A是如圖1所示的超接面裝置的角落處的示意圖；圖2B是如圖1所示的超接面裝置的角落處的另一示意圖；圖3示意性地示出了依據本發明實施例的半導體裝置的俯視圖以及角落處的放大圖；圖4示意性地示出了依據本發明實施例的半導體裝置的俯視圖以及主單元區域邊緣處的放大圖；圖5示意性地示出了沿著圖4所示的俯視圖中的A-A'線的剖面視圖；以及圖6示意性地示出了根據本發明的實施例的製造方法的流程圖。
下面將闡述本發明的一些實施例，這些實施例係有關 具有超接面的半導體裝置及其製造方法。另外，下面還將具體描述半導體裝置的基板的一些實施例。在本發明中，“基板”包括但是並不局限於各種晶片，例如單個積體電路晶片，感測器晶片，開關晶片以及其他具有半導體性能的晶片。附圖中以及下文將對某些實施例中的許多具體細節來進行詳細說明，以幫助讀者透徹領會本發明的實施例。某些其他的實施例可能在構造、成分或者製程流程方面與本發明揭露的實施例有所不同，但是本領域的技術人員應該理解，在沒有附圖所示的實施例或者其他細節、方法、材料等的情況下，本發明的實施例也是可以被實現的。
圖3示意性地示出了依據本發明實施例的半導體裝置300的俯視圖和角落部分的放大圖。在下面的討論中，以功率裝置為例來進行說明，但是本領域的技術人員應該理解本發明並不局限於功率裝置，也可以被應用在其他需要縮小裝置尺寸的垂直結構裝置中。
如圖3所示，該實施例的半導體裝置300包括主單元區(Main Cell Region)310和端接區(Termination Region)320。通常，在主單元區310中形成垂直結構的半導體裝置的主要部分，在端接區320中引出半導體裝置的端子。在圖3所示的半導體裝置300俯視圖中，主單元區310和端接區320基本上為矩形形狀，但是本領域的技術人員應該理解，也可以採用其他的形狀，例如正方形等。
如圖3右側的放大圖所示，晶片上的超接面裝置包括第一區FR，以及構成第二區的中間區IR和週邊區PR，其中，第一區FR和中間區IR構成主單元區310，週邊區PR構成端接區320。但是，如本領域的技術人員理解的那樣，根據另外的實施例，第一區FR也可以構成主單元區，中間區IR和週邊區PR構成端接區。
依據一個實施例，在第一區FR中設置溝槽閘極金屬氧化物半導體(MOSFET)單元的多個溝槽區330和多個立柱340，如圖4所示。相鄰的溝槽區被立柱所隔開，在溝槽區與立柱之間形成本體區。在中間區IR和週邊區PR中形成沿著第一區的相應邊而延伸的多個立柱，其中，在所述第二區的角落中，多個橫向立柱的端部與多個豎向立柱的端部被分開且彼此交錯。第一區中立柱的間距與中間區中立柱的間距相同，都為L1。
依據一個實施例，在第二區的角落中，每個橫向立柱的端部與垂直於該橫向立柱的兩個豎向立柱係分開有第一距離，該第一距離基本上為所述兩個豎向立柱之間距的一半。例如，在中間區IR中，每個橫向立柱的端部與垂直於該橫向立柱的兩個豎向立柱係分開有所述兩個豎向立柱之間距L1的一半。再如，在週邊區PR中，每個橫向立柱的端部與垂直於該橫向立柱的兩個豎向立柱係分開有所述兩個豎向立柱之間距L2的一半。
在低電壓的超接面裝置中，由於P型立柱比較淺，所以與P型立柱的電荷相比，P型體區的電荷是不可忽略 的。如果在端接區320中保持立柱的間距與主單元區310中的立柱之間距相同，則電荷不平衡。所以，將端接區320中立柱之間的間距設定為比主單元區310中的立柱之間距L1小的L2。
但是，如本領域的技術人員能夠理解的那樣，在高電壓的超接面裝置中，中間區IR中立柱的間距與週邊區PR中立柱的間距相同。
圖4右側的放大圖中示出了左側圖中跨在主單元區310和端接區320的一小塊正方形區域的具體結構。如圖所示，在主單元區310中，閘極溝槽330與P型柱(或N型柱)140係交替地形成，也就是說，深井(立柱)將溝槽型MOSFET單元的各個閘極溝槽隔開。
在主單元區310的邊緣處，將第一區中的橫向立柱的端部與中間區IR中的豎向立柱之間的距離係設定為第一區中橫向立柱之間距的大約一半。
圖5示意性地示出了沿著圖1所示的俯視圖中的A-A'線的剖面視圖。如圖5所示，依據該實施例的半導體裝置500包括半導體基板502，形成在半導體基板502背側的金屬層501，形成在半導體基板502上的外延層503，在外延層503中形成的深井504，以及在深井之間的外延層中形成的溝槽MOSFET單元。
外延層503的頂部係形成為本體區507，半導體基板503係形成為汲極區。該溝槽MOSFET單元包括在本體區507中所形成的源極區508和淺溝槽閘極，閘極槽深大約 為深井之間距的二分之一以下，最好在三分之一以下，從而降低閘極溝槽密度，使得閘極電容Qg降低。
根據另一實施例，該淺溝槽閘極的溝槽側壁和底部係沉積有厚的氧化物層並且該淺溝槽係填充有多晶矽506。
根據該實施例，在閘極溝槽的上方形成閘極氧化物層509和用作為源極的金屬層510，並開孔透過導電通路而建立閘極多晶矽到外部的連接。另外，在半導體基板的背側所形成的金屬層501用作為汲極。
在該實施例中，本體區507也可以佔據深井504的上部。例如，相鄰的溝槽MOSFET單元的本體區係彼此相連接。但是，根據本發明的另一實施例，深井504也可以將相鄰的溝槽MOSFET單元的本體區507隔開。本體區507係形成為淺的本體區並且是輕度摻雜的。根據本發明的再一實施例，對本體區進行兩次輕度摻雜注入。
根據上述實施例的超接面裝置，實現了Ron*Qg的極大降低。另外，該技術利用改進的超接面技術，還減小了Ron*A。因此，該實施例的半導體裝置係適用於中高壓高速電路領域。
為了提高深井的濃度分佈，在本發明的一些實施例中，深井504係透過對外延層503進行多次注入來予以形成的，最深的那次注入操作的劑量係比其他次注入操作的劑量更大。例如，最深的那次注入操作的劑量為其他次劑量的105%~110%。這樣能夠為深井504的底部提供更多電荷來進行底部電荷補償。在一些實施例中，外延層 503係透過多次外延生長來予以形成的，並且每次外延之後進行多次注入操作。這樣能夠在深井中形成較為優良的濃度分佈。根據本發明的另外一些實施例，多次外延生長的厚度不同，首次外延生長的厚度係大於後續之外延生長的厚度。
圖6示意性地示出了依據本發明的實施例的製造方法600的流程圖。如圖6所示，依據本發明的實施例的半導體裝置的製造方法例如包括：在601，提供一晶片；在602，在晶片上形成基本上為矩形的第一區和在第一區之週邊的第二區，在603，在第一區中設置溝槽閘極金屬氧化物半導體(MOSFET)單元的多個溝槽區310和多個立柱320，其中，相鄰的溝槽區被立柱所隔開，在604，在溝槽區與立柱之間形成本體區，在第二區中形成沿著第一區的相應邊而延伸的多個立柱。在第二區的角落中，多個橫向立柱的端部與多個豎向立柱的端部被分開且彼此交錯。
根據另外的實施例，在第二區的角落中，每個橫向立柱的端部與垂直於該橫向立柱的兩個豎向立柱係分開有第一距離，該第一距離基本上為兩個豎向立柱之間距L2的一半。
根據其他實施例，第一區中的立柱的端部與第二區中垂直於該第一區中立柱的立柱係分開有L1的一半。
針對傳統超接面裝置因為在轉角處很難實現N型立柱與P型立柱之間的電荷平衡而因此的擊穿問題，上述實施例透過將轉角處的立柱之間形成為交錯(stagger)結構並在它們之間保持一定間距而實現了在轉角處的電荷平衡，從而避免了此處擊穿的最先發生，因而提高了裝置的耐壓。
儘管本發明已經提出了一些實施例，但是這並不應該是對本發明的限制。本領域的技術人員在閱讀上述實施例後，可以掌握其他各種變化或者變型。例如，儘管上述實施例使用的是n-通道裝置，但是透過改變半導體區域的導電型，就可以將本發明應用於p-通道裝置。因此，申請專利範圍中所涵蓋的各種變化或者變型都屬於本發明的保護範圍。
雖然已參照幾個典型實施例來描述了本發明，但應當理解，所用的術語是說明和示例性、而非限制性的術語。由於本發明能夠以多種形式來予以具體實施而不脫離發明的精神或實質，所以應當理解，上述實施例不限於任何前述的細節，而應在隨附之申請專利範圍所限定的精神和範圍內廣泛地解釋，因此落入申請專利範圍或其等效範圍內的全部變化和變型都應為隨附之申請專利範圍所涵蓋。
300‧‧‧半導體裝置
310‧‧‧主單元區
320‧‧‧端接區

Claims (10)

  1. 一種具有超接面結構的半導體裝置，包括在晶片上形成之基本上為矩形的第一區和在第一區之週邊的第二區，在該第一區中設置溝槽閘極金屬氧化物半導體(MOSFET)單元的多個溝槽區和多個立柱，其中，相鄰的溝槽區被立柱所隔開，在溝槽區與立柱之間形成本體區，在該第二區中形成沿著第一區的相應邊而延伸的多個立柱，其中，在該第二區的角落中，多個橫向立柱的端部與多個豎向立柱的端部係分開且彼此交錯的。
  2. 如申請專利範圍第1項所述的半導體裝置，其中，在該第二區的角落中，每個橫向立柱的端部與垂直於該橫向立柱的兩個豎向立柱係分開有第一距離，該第一距離基本上為該兩個豎向立柱間距的一半。
  3. 如申請專利範圍第2項所述的半導體裝置，其中，第一區中的立柱的端部與第二區中垂直於該第一區中立柱的立柱係分開有該第一距離。
  4. 如申請專利範圍第1項所述的半導體裝置，其中，在第二區包括靠近第一區的中間區和遠離第一區的週邊區，在中間區中所形成的立柱之間的間距係大於在週邊區中所形成的立柱之間的間距。
  5. 如申請專利範圍第4項所述的半導體裝置，其中，在該中間區的角落中，每個橫向立柱的端部與垂直於該橫向立柱的兩個豎向立柱係分開有第一距離，該第一距離基本上為該兩個豎向立柱間距的一半。
  6. 如申請專利範圍第4項所述的半導體裝置，其中，在該週邊區的角落中，每個橫向立柱的端部與垂直於該橫向立柱的兩個豎向立柱係分開有第二距離，該第二距離基本上為該兩個豎向立柱間距的一半。
  7. 如申請專利範圍第4項所述的半導體裝置，其中，第一區和中間區構成該半導體裝置的主單元區，該週邊區構成該半導體裝置的端接區。
  8. 一種半導體裝置的製造方法，包括步驟：提供一晶片；在晶片上形成基本上為矩形的第一區和在第一區之週邊的第二區，在該第一區中設置溝槽閘極金屬氧化物半導體(MOSFET)單元的多個溝槽區和多個立柱，其中，相鄰的溝槽區被立柱所隔開，在溝槽區與立柱之間形成本體區，在該第二區中形成沿著第一區的相應邊而延伸的多個立柱，其中，在該第二區的角落中，多個橫向立柱的端部與多個豎向立柱的端部係分開且彼此交錯的。
  9. 如申請專利範圍第8項所述的方法，其中，在該第二區的角落中，每個橫向立柱的端部與垂直於該橫向立柱的兩個豎向立柱係分開有第一距離，該第一距離基本上為該兩個豎向立柱間距的一半。
  10. 如申請專利範圍第9項所述的方法，其中，第一 區中的立柱的端部與第二區中垂直於該第一區中立柱的立柱係分開有該第一距離。
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