TWI455309B - Ｐｎ接面與金氧半導體電容混合減少表面電場電晶體 - Google Patents

Ｐｎ接面與金氧半導體電容混合減少表面電場電晶體 Download PDF

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TWI455309B
TWI455309B TW097100497A TW97100497A TWI455309B TW I455309 B TWI455309 B TW I455309B TW 097100497 A TW097100497 A TW 097100497A TW 97100497 A TW97100497 A TW 97100497A TW I455309 B TWI455309 B TW I455309B
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Steven Leibiger
Gary M Dolny
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Description

PN接面與金氧半導體電容混合減少表面電場電晶體
此發明一般係關於半導體裝置，且更特定言之係關於高壓減少表面電場(RESURF)電晶體裝置及製造此類裝置之方法。
垂直與橫向高壓電晶體兩者係廣泛用於電力應用中。在開啟狀態中，需要該電晶體具有低開啟電阻以最小化傳導損失。在關閉狀態中，需要該電晶體具有一高崩潰或阻隔電壓。橫向減少表面電場電晶體係橫向裝置，其具有彼此橫向間隔之一源極與一汲極並在該等源極與汲極區域之間具有一漂移區域。在開啟狀態中，電流在源極與汲極之間流過該漂移區域，而在關閉狀態中，該漂移區域係空乏從而防止電流。為增加電力電晶體之效能特性，發明者Fujihiro在2000年8月1日發佈的美國專利6,097,063與發明者Rumennik等人在2001年3月27日發佈的美國專利6,207,994 B1揭示一橫向裝置中一具有第一與第二導電率類型(p/n)之半導體材料之交替層的漂移區域的使用。發明者Chen在1993年1月1日發佈的美國專利5,216,275與發明者Tihanyi在1995年8月1日發佈的美國專利5,438,215將此概念應用於垂直裝置。以下文章係關於揭示在一VDMOS裝置中於該漂移區域之側壁處使用金屬厚氧化物以增加阻隔電壓或增加背景摻雜－Liang等人的"氧化物旁通VDMOS(OBVDMOS)：超接面高壓金氧半導體電力裝置之 替代"(IEEE Electron Devices Letters，第22卷，第8號，第407至409頁，2001年8月)。相對於此等技術，本發明之一優點係當處於電壓阻隔狀態時四側而非雙側空乏區域之使用。
一直以來都需要具有高阻隔電壓與更低開啟狀態電阻兩者的電晶體。本發明解決此需要。
依據本發明，提供一對於上述需要之解決方式。
依據本發明之一特徵，提供：一半導體裝置，其包含：一半導體基板；一源極區域與一汲極區域，其係提供於該基板中；其中該源極區域與該汲極區域係彼此橫向間隔；一漂移區域，其處於該基板中該源極區域與該汲極區域之間；其中該漂移區域包括一結構，其具有延伸於該源極區域與該汲極區域之間的至少第一與第二溝渠電容器，該溝渠電容器具有一內板及與該內板相鄰之一介電材料；並進一步包括一堆疊，其具有至少一第一導電率類型之一第一區域、一第二導電率類型之一第二區域及該第一導電率類型之一第三區域，其中該堆疊位於該至少第一與第二溝渠電容器之間並與該等第一與第二溝渠電容器之該介電質接觸；其中當該裝置處於一開啟狀態時，電流在該等源極與汲 極區域之間流過該第二導電率類型之該第二區域；而當該裝置處於一關閉/阻隔狀態時，該第二導電率類型之該第二區域係四向空乏於該堆疊之該等第一與第三區域中及該等第一與第二溝渠電容器中。
依據本發明之另一特徵，提供一製造一半導體裝置之方法，其包含：提供一半導體基板，其具有彼此橫向間隔之一源極與一汲極，在該等源極與汲極區域之間具有一漂移區域；在該漂移區域中形成一區域，其包括一第一導電率類型之一第一區域、該第一區域之頂部上的一第二導電率類型之一第二區域及該第二區域之頂部上的該第一導電率類型之一第三區域；以及在該區域中產生至少兩個間隔的溝渠電容器，其係延伸於該源極與該汲極之間，其中該等第一、第二及第三區域之一堆疊係形成於該等溝渠電容器之間並於該等溝渠電容器電連接。
本發明具有以下優點：
1.提供一減少表面電場高壓電晶體，其在阻隔模式中除PN介面空乏以外還使用金氧半導體電容器空乏。此允許該漂移區域中明顯更高的摻雜並因而大大減少該電晶體之開啟狀態電阻。
2.藉由在阻隔模式中使用由四個側之空乏，存在超過已知雙側空乏的改良，因而改良該電晶體之性質。
現在提供本發明之範例性具體實施例。雖然此等具體實施例解說對矽基電力裝置的概念應用，預期本文揭示之原理將適用於各種半導體裝置，包括使用化合物半導體材料(例如碳化矽)形成之半導體裝置，以及積體電路。雖然裝置之範例指示特定導電率類型與特定材料(例如介電材料與導體)之併入，此等裝置僅係範例性並且並不預期本發明限於併入此類傳統組件或方法之具體實施例。例如本文所示之具體實施例係NMOS電晶體，但本發明亦可藉由反轉摻雜極性而應用於一PMOS電晶體。
現參考圖1，顯示本發明之一具體實施例。如所示，減少表面電場電晶體10包括：一半導體P－ 基板12，其具有一具有一源極接點16之源極14；一p－井18；閘極20；汲極22，其具有一汲極接點24；以及一漂移區域26，其在源極14與汲極22之間。漂移區域26併入溝渠金氧半導體電容器/P＋ /N＋ 接面混合結構。更特定言之，該混合結構26包括藉由P＋ /N＋ 堆疊30分離的間隔溝渠電容器28。該等P＋ /N＋ 堆疊30之各堆疊具有一垂直P＋ 區域32，其亦在圖4D中顯示並且其在其個別堆疊中與各P＋ 及N＋ 層接觸以使得所有P＋ 區域係彼此並聯連接且同樣所有該等N＋ 區域係彼此並聯連接。該等P＋ 摻雜區域32亦係藉由圖4D中之連接34示意性表示之一金屬層來電連接至填充於該等溝渠電容器28中之多晶矽。該等區域32連接該P＋ /N＋ 堆疊26中之P＋ 層與該等溝渠電容器28中之P＋ 多晶矽，以便如圖4C所示在該P＋ /N＋ 堆疊26中之N＋ 層中產生四側空乏區域。
圖2與3係沿圖1中之線2-2與3-3之個別正視斷面概略圖。圖2顯示該等溝渠電容器28之一者的輪廓，其顯示二氧化矽介電層40與多晶矽42。圖2與3以箭頭44指示當該減少表面電場電晶體10處於開啟狀態時電流在源極14與汲極22之間透過該P+ /N+ 堆疊26流動。該P+ /N+ 堆疊26包括P+ 之第一導電率類型之區域46，其與N+ 之第二導電率類型之區域48交錯。如圖2與3所示，電流主要流過該等N+ 區域48。
圖4A至4D係沿圖1中之線4A，B，C-4A，B，C的斷面概略圖。如所示，溝渠電容器26包括使用摻雜多晶矽42填充的具有二氧化矽側壁40之溝渠50。N+ 區域48係導電/阻隔區域，其取決於該減少表面電場電晶體10是否係開啟或關閉的。
圖4B顯示處於開啟狀態的半導體裝置，其中P+ /N+ 堆疊26之P+ /N+ 層與該等溝渠電容器28之接面係偏壓以便不空乏該等N+ 摻雜導電區域48。電流係顯示為流入該圖式之平面，如藉由交叉圓形56所描述。
圖4C顯示處於關閉狀態的半導體裝置，其中該等P+ /N+ 堆疊26之P+ /N+ 層與該等溝渠電容器28之間的接面係偏壓以便從四側空乏該等N+ 摻雜導電區域48。因而，電流係阻隔，如藉由虛線矩形60所示。由於該四側空乏，當在該減少表面電場電晶體10處於關閉狀態時仍空乏該等N+ 層48時，與使用雙側空乏區域相比，該等N+ 層48之摻雜可顯著更高(高達2倍)或該等N+ 層48之大小可顯著增加，或增加該等N+ 層48之摻雜與大小的組合。該N+ 區域之更高摻雜及/ 或增加的表面積顯著減少該裝置之開啟狀態電阻。
圖4D係沿圖1中之線4D－4D的斷面概略圖。該等P＋ 區域32形成該等P＋ 層32至該減少表面電場電晶體10之頂部的連接，其係藉由本發明之一具體實施例中的金屬化(未顯示)來使用該等溝渠電容器22中之P＋ 多晶矽42接合在一起。當該減少表面電場電晶體10處於關閉狀態時，該等P＋ 層32與該等溝渠電容器28中之P＋ 多晶矽42之共同連接34在該等空乏區域46中提供均勻性。
圖5A至5C係解說製造圖1之本發明中之選擇細節的斷面概略圖，其用以顯示製造該等P＋ /N＋ 堆疊26之P＋ /N＋ 層中之選擇細節。圖5A至5C顯示連續的P＋ 與N＋ 植入物70、72、74、76及78以形成針對該等P＋ /N＋ 堆疊26之多區區域。熟習此項技術者將明白還可藉由擴散或使用磊晶層來形成該等P＋ /N＋ 層。
圖6A至6D係解說製造圖1之本發明中的進一步選擇細節的斷面概略圖，其用以顯示形成該等溝渠電容器28之選擇細節。圖6A顯示半導體基板12之上部表面上的遮罩80。在該等P＋ /N＋ 堆疊26中蝕刻一或多個溝渠82用於形成溝渠電容器28。圖6B顯示沈積或生長於溝渠82之側壁與底部上的二氧化矽40。圖6C顯示沈積於該等溝渠82中以形成該等溝渠電容器28的P＋ /N＋ 多晶矽84。接著移除該遮罩80與該基板12之上的P＋ /N＋ 多晶矽之部分。
圖6D顯示一具體實施例中形成於該基板12與藉由離子植入形成之P＋ 區域46之頂部上的另一遮罩88。在形成該等區 域32之後，該遮罩88係移除。
該等溝渠電容器28係以與一溝渠閘極相同之方式加以製造，並因此不要任何額外的遮罩。代替該等溝渠電容器28使用p＋ 支柱會要求使用該等溝渠電容器28不需要的額外處理。
圖7係一單一P－ 基板102(圖8中顯示)上的兩個圖1所示之減少表面電場電晶體10連同一額外裝置100一起的平面概略圖，其具有包圍三個裝置之各裝置的一N－ 磊晶層104與一隔離區域106。
圖8係沿圖7中之線8－8的正視斷面概略圖。如可在圖7中看出，該等溝渠電容器28向下延伸至該P－ 基板102中，該隔離區域106亦如此以從而隔離圖7所示之三個裝置。
例如，該額外裝置100可以係針對一同步降壓轉換器之一控制器，其控制該等兩個減少表面電場電晶體10，其中該等三個裝置係藉由線接合互連。
圖9係用於CMOS積體電路的圖1所示之減少表面電場電晶體10連同一P－ 井112中之一互補減少表面電場電晶體110一起的正視斷面概略圖。該互補減少表面電場電晶體110中的多數摻雜類型與該減少表面電場電晶體10中之摻雜類型相反。因而，對應電容器112係以N＋ 多晶矽114來填充，並且該等P＋ /N＋ 堆疊116之各堆疊具有N＋ 頂部、中間及底部層118與該等N＋ 層118之間的P＋ 層120。
雖然已顯示與說明本發明之特定具體實施例，應明白在本發明之精神與範疇內可實現變更與修改。因而，可將熟 習此項技術者熟知的其他材料用於形成該等溝渠電容器並可使用其他程序來形成該等p/n堆疊與溝渠電容器。此外，該裝置可具有比所示溝渠電容器之數目多或少的溝渠電容器數目及比該等堆疊中該等第一與第二導電率類型之交替區域之數目多或少的交替區域數目。
10‧‧‧減少表面電場電晶體
12‧‧‧半導體P－ 基板
14‧‧‧源極
16‧‧‧源極接點
18‧‧‧p－井
20‧‧‧閘極
22‧‧‧汲極/溝渠電容器
24‧‧‧汲極接點
26‧‧‧漂移區域/P＋ /N＋ 堆疊/溝渠電容器
28‧‧‧溝渠電容器
30‧‧‧P＋ /N＋ 堆疊
32‧‧‧P＋ 區域/P＋ 層
34‧‧‧連接
40‧‧‧二氧化矽介電層/二氧化矽側壁
42‧‧‧多晶矽
46‧‧‧P＋ 區域
48‧‧‧N＋ 區域/N＋ 區域層
50‧‧‧溝渠
70‧‧‧植入物
72‧‧‧植入物
74‧‧‧植入物
76‧‧‧植入物
78‧‧‧植入物
80‧‧‧遮罩
82‧‧‧溝渠
84‧‧‧P＋ /N＋ 多晶矽
88‧‧‧遮罩
100‧‧‧裝置
102‧‧‧P－ 基板
104‧‧‧N－ 磊晶層
106‧‧‧隔離區域
110‧‧‧減少表面電場電晶體
112‧‧‧P－ 井/電容器
114‧‧‧N＋ 多晶矽
116‧‧‧P＋ /N＋ 堆疊
118‧‧‧N＋ 層
120‧‧‧P＋ 層
一般而言，結合附圖由以上更詳細的說明已更佳地明白上述及其他特徵、特性、優點及本發明，其中：圖1係本發明之一具體實施例的平面概略圖；圖2係沿圖1中之線2－2的正視斷面概略圖；圖3係沿圖1中之線3－3的正視斷面概略圖；圖4A至4C係沿圖1中之線4A，B，C－4A，B，C的斷面概略圖；圖4D係沿圖1中之線4D－4D的斷面概略圖；圖5A至5E係解說製造圖1之本發明中之選擇細節的斷面概略圖；圖6A至6D係解說製造圖1之本發明中之進一步選擇細節的斷面概略圖；圖7係一單一基板上的兩個圖1所示之具體實施例連同一額外裝置一起的平面概略圖，其具有包圍該三個裝置之各裝置的一隔離區域；圖8係沿圖7中之線8－8的正視斷面概略圖；以及圖9係一CMOS積體電路配置中圖1所示之具體實施例連同一互補具體實施例一起的正視斷面概略圖。
應明白，為清楚起見且在認為適當之處，該等圖式中參考數字已係重複以指示對應特徵。而且，圖式中各種物件的相對大小在某些情況下已係扭曲以更清楚顯示本發明。
10‧‧‧減少表面電場電晶體
12‧‧‧半導體P－ 基板
14‧‧‧源極
16‧‧‧源極接點
18‧‧‧p－井
20‧‧‧閘極
22‧‧‧汲極/溝渠電容器
24‧‧‧汲極接點
26‧‧‧漂移區域/P＋ /N＋ 堆疊/溝渠電容器
28‧‧‧溝渠電容器
30‧‧‧P＋ /N＋ 堆疊
32‧‧‧P＋ 區域/P＋ 層

Claims (10)

  1. 一種半導體裝置，其包含：一半導體基板；一源極區域與一汲極區域，其係提供於該基板中；其中該源極區域與該汲極區域係彼此橫向間隔；一漂移區域，其處於該基板中該源極區域與該汲極區域之間；其中該漂移區域包括：一結構，其具有從鄰近的該源極區域延伸至鄰近的該汲極區域的至少第一及第二溝渠MOS電容器；並進一步包括一垂直堆疊，其具有至少三個區域，一者在另一者之頂部上，包括至少一第一導電率類型之一第一區域、一第二導電率類型之一第二區域及該第一導電率類型之一第三區域，其中該第一、第二及第三區域之每一個區域從鄰近的該源極區域延伸至鄰近的該汲極區域且延伸於該第一與第二溝渠MOS電容器之間；其中當該裝置處於一開啟狀態時，電流在該等源極與汲極區域之間流過該第二導電率類型之該第二區域；而當該裝置處於一關閉/阻隔狀態時，該第二導電率類型之該第二區域係藉由來自該堆疊之該等第一與第三區域及來自該等第一與第二溝渠MOS電容器的四個分離電場來空乏。
  2. 如請求項1之裝置，其中該第一導電率類型之該等第一與第三區域係p區域，且其中該第二導電率類型之該第 二區域係一n區域。
  3. 如請求項1之裝置，其中該第一導電率類型之該等第一與第三區域係n區域，而該第二導電率類型之該第二區域係一p類型。
  4. 如請求項1之裝置，其中該等溝渠電容器包括一個二氧化矽壁與填充該溝渠MOS電容器之其餘部分之一摻雜多晶矽。
  5. 如請求項1之裝置，其中該裝置係一減少表面電場電晶體。
  6. 如請求項1之裝置，其中該堆疊之該第二導電率類型之該區域係比不採用該等第一及第二溝渠MOS電容器之一減少表面電場電晶體中之一可比較區域顯著更高地摻雜。
  7. 如請求項1之裝置，其中該半導體基板具有複數個間隔溝渠電容器與在該複數個間隔溝渠電容器之間交錯的複數個第一與第二導電率類型之堆疊。
  8. 一種製造一半導體裝置之方法，其包含：提供一半導體基板，其具有彼此橫向間隔之一源極與一汲極，在該等源極與汲極區域之間具有一漂移區域；在該漂移區域中形成一區域，其包括一垂直堆疊，該垂直堆疊具有至少一第一導電率類型之一第一區域、該第一區域之頂部上的一第二導電率類型之一第二區域及該第二區域之頂部上的該第一導電率類型之一第三區域，其中該第一、第二及第三區域之每一個區域從鄰近 的該源極區域橫向延伸至鄰近的該汲極區域；以及在該區域中產生至少兩個間隔的溝渠電容器，其係橫向延伸於該源極與該汲極之間，其中該垂直堆疊係形成於該等溝渠電容器之間並於該等溝渠電容器電連接。
  9. 如請求項8之方法，其中該形成步驟包括植入該等第一、第二及第三區域。
  10. 如請求項8之方法，其中該產生步驟包括在延伸於該源極與該汲極之間的該區域中蝕刻平行間隔的溝渠，氧化該等蝕刻的溝渠之側壁以在該等側壁上形成一層二氧化矽層，及使用摻雜多晶矽來填充該等溝渠之其餘部分。
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