CN103579325B - 半导体衬底中包含沟槽的半导体器件及其制造方法 - Google Patents

半导体衬底中包含沟槽的半导体器件及其制造方法 Download PDF

Info

Publication number
CN103579325B
CN103579325B CN201310349620.1A CN201310349620A CN103579325B CN 103579325 B CN103579325 B CN 103579325B CN 201310349620 A CN201310349620 A CN 201310349620A CN 103579325 B CN103579325 B CN 103579325B
Authority
CN
China
Prior art keywords
groove
semiconductor
semiconductor substrate
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310349620.1A
Other languages
English (en)
Other versions
CN103579325A (zh
Inventor
安东·毛德
赖因哈德·普洛斯
汉斯-约阿希姆·舒尔茨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Austria AG
Original Assignee
Infineon Technologies Austria AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria AG filed Critical Infineon Technologies Austria AG
Publication of CN103579325A publication Critical patent/CN103579325A/zh
Application granted granted Critical
Publication of CN103579325B publication Critical patent/CN103579325B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2225—Diffusion sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/05078—Plural internal layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)

Abstract

本发明公开了半导体衬底中包含沟槽的半导体器件及其制造方法。该半导体器件包括半导体衬底。第一沟槽从第一侧延伸入或穿过该半导体衬底。半导体层在该第一侧邻接该半导体衬底。该半导体层在该第一侧覆盖该第一沟槽。该半导体器件进一步包括在该半导体衬底的与该第一侧相反的第二侧处的接触体。

Description

半导体衬底中包含沟槽的半导体器件及其制造方法
技术领域
本发明总体上涉及半导体器件及其制造方法，具体地，涉及在半导体衬底中包含沟槽的半导体器件及其制造方法。
背景技术
在垂直半导体器件中，电流在半导体晶片的第一侧至半导体晶片的与第一侧相反的第二侧之间流动。例如，电流从位于第一侧的场效应晶体管（FET）的源极流至第二侧的漏极。经由第二侧，半导体晶片可安装至例如引线框或铜直接键合（DCB）基板的载体。在垂直半导体器件中，期望的是半导体器件的底面与载体之间的低欧姆接触以及从第一侧至第二侧穿过半导体器件的低欧姆电流路径。在操作器件包括高电流密度的半导体器件，例如包含低于100V的电压阻断能力的低电压FET，该器件的第一侧和第二侧之间任何寄生电阻都是不利的。由于与具有较高电压阻断能力的器件相比，低电压半导体器件的漂移区很薄，因此薄晶圆技术是实现所述器件的一种途径。
在垂直半导体器件中，期望减少导通状态电阻。
发明内容
根据实施方式，一种半导体器件，包括半导体衬底。半导体器件还包括从第一侧延伸至半导体衬底或从第一侧穿过半导体衬底的第一沟槽。该半导体器件进一步包括在第一侧与半导体衬底邻接的半导体层。该半导体层覆盖第一侧的第一沟槽。该半导体器件还包括在半导体衬底的与第一侧相反的第二侧处的接触体。
根据另一实施方式，半导体晶圆包括硅衬底。该半导体晶圆进一步包括从第一侧延伸入半导体衬底的第一沟槽。该半导体晶片还包括与硅衬底邻接的半导体层，其中，该半导体层覆盖第一侧的第一沟槽。
根据又一实施方式，一种半导体器件的制造方法，包括：形成从第一侧至半导体衬底中的第一沟槽。该方法进一步包括在第一侧形成邻接该半导体衬底的半导体层，其中，该半导体层覆盖第一侧的第一沟槽。该方法还包括在该半导体衬底的与第一侧相反的第二侧处形成接触体。
在阅读以下详细描述并观察附图后，本领域技术人员将认识到附加的特征和优点。
附图说明
包含附图从而提供对本发明的进一步理解，并且将附图并入本说明书中且构成本说明书一部分。附图示出本发明实施方式，并且与说明书一起用于说明本发明原理。本发明的其它实施方式以及本发明的许多预期优点将容易理解，因为它们通过参考以下详细描述变为更好理解。
图1示出了包含由半导体层覆盖的半导体衬底中的沟槽的半导体器件的一部分的横截面示意图。
图2A示出了图1所示的半导体层中形成的平面栅晶体管单元的一部分的横截面示意图。
图2B示出了图1所示的半导体层中形成的沟槽栅晶体管单元的一部分的横截面示意图。
图3A示出了图1所示的沟槽被部分填充导电材料的横截面示意图。
图3B示出了图1所示的沟槽被部分填充导电材料及该导电材料顶部的扩散阻挡层的横截面示意图。
图3C示出了图1所示的沟槽部分被填充导电材料及该导电材料顶部及一侧的扩散阻挡层的横截面示意图。
图3D示出了图1所示的沟槽被部分填充导电材料及该沟槽底部的电电介质的横截面示意图。
图4示出了沿图1中的线A-A'的n-掺杂及p-掺杂的分布的一个实施方式的示意图。
图5示出了关于图1所示的第一沟槽的几个沟槽的几何结构的平面示意图，其可单独或合并使用。
图6A和6B示出了根据实施方式的半导体晶圆的横截面示意图和平面示意图。
图6C示出了图6A和6B所示的半导体衬底的一部分的扫描电子显微图。
图7示出了根据实施方式的半导体器件的制造方法的简化流程图。
图8A示出了根据实施方式在第一侧形成沟槽之后的半导体衬底的横截面示意图。
图8B示出了在沟槽至少被部分填充导电材料之后图8A的半导体衬底的横截面示意图。
图8C示出了形成在第一侧邻接半导体衬底的半导体层之后图8B中的半导体衬底的横截面示意图。
图8D示出了从与第一侧相反的第二侧移除半导体衬底的一部分之后图8C中的半导体衬底的横截面示意图。
图8E示出了在第二侧处形成接触体之后图8D中的半导体衬底的横截面示意图。
具体实施方式
在下面的具体实施方式中，参考形成本发明的一部分的附图，其中通过图解的方式示出可实施本发明的具体实施方式。应理解，在不脱离本发明的范围的情况下，可利用其它实施方式且可进行结构或逻辑的改变。例如，对于一个实施方式而示出或描述的特征可用于或结合其它实施方式以产生又一实施方式。其目的在于本发明包括这些修改和变化。使用特定的语言（其不应被解释为限制所附权利要求书的范围）描述实施方式。
附图未按比例绘制且仅供说明之用。为清楚起见，如果没有另外说明，相应元件已在不同的附图中由相同的标号指定。
如“第一”、“第二”等的术语用于描述不同的元件、区域、部分等但也不意在限制。通篇描述中，相似术语指代相似元件。
术语“具有”、“包含（containing）”、“包括（including）”、“包括（comprising）”等是开放的，且这些术语表明所述的结构、元件或特征的存在，但不排除其它元件或特征。
冠词“一个”和“所述”旨在包括复数以及单数，除非上下文清楚地另有指示。
附图示出通过在掺杂类型“n”或“p”之后的“–”或“+”表示的相对掺杂浓度。例如，“n-”是指低于“n”掺杂区的掺杂浓度的掺杂浓度，同时“n+”掺杂区具有比“n”掺杂区高的掺杂浓度。相同的相对掺杂浓度的掺杂区不必具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区域可具有相同或不同的绝对掺杂浓度。
术语“电连接”描述电连接元件之间的永久低欧姆连接，例如有关元件之间的直接接触或经由金属和/或高掺杂的半导体的低欧姆连接。术语“电耦合”涵盖“电连接”但还包括适于信号传输的一个或多个中间元件可被设置在电耦合元件之间，例如，可控制为暂时提供第一状态下的低欧姆连接和第二状态下的高欧姆电去耦的元件。
图1示出了根据实施方式的半导体器件100的一部分。
半导体器件100包括半导体衬底110。根据实施方式，半导体衬底110是单晶硅衬底。根据其他实施方式，半导体衬底110包括其他半导体材料，例如SiC或GaN。
第一沟槽115从第一侧120延伸穿过半导体基板110。半导体层125与半导体衬底110在第一侧120邻接。半导体层125覆盖在第一侧120的第一沟槽115。换言之，半导体层125封闭在第一侧120的第一沟槽115，因此，作为密封层密封在第一侧120的第一沟槽115。第一沟槽115埋在半导体层125下方的半导体衬底110中。
在半导体衬底110的第二侧130，接触体135邻接第一沟槽115的底面。接触体135包括一种或多种导电材料。例如，接触体可包括高掺半导体、半导体金属化合物、碳、金属和金属合金之一的层或其任何组合的层堆叠。
在图1中所示的实施方式中，第一沟槽穿过半导体衬底110延伸至接触体135。换言之，接触体135封闭第一沟槽115的底面，并充当密封第一沟槽115的密封层。根据另一实施方式，第一沟槽115可在半导体衬底110终止，并且半导体衬底110的一部分保留在第一沟槽115的底面与第二侧130的接触体135之间。
在半导体层125中，形成掺杂区，其构成半导体器件100的功能元件。根据实施方式，半导体器件100是分立式半导体，其包括布置成一个或多个单元阵列的多个晶体管单元。半导体器件100的示例包括例如绝缘栅场效应晶体管（IGFET）的FET，例如，包括具有金属和非金属栅电极的FET及绝缘双极晶体管（IGBT）的金属氧化物半导体场效应晶体管（MOSFET）。根据另一实施方式，半导体器件100是集成电路，其包括例如电阻器（例如，扩散电阻器）、晶体管、二极管、电容器的多个电路元件。
下文将参考图2A进一步描述形成在半导体层125中的平面栅晶体管的一个示例。下文参考图2B进一步描述形成在半导体层125中的沟槽栅晶体管的另一示例。下文进一步参考图3A至3D描述第一沟槽115的填充的实施方式。
根据实施方式，第一沟槽的沿着正交于第一侧120的垂直方向y的深度d在20μm到200μm的范围。
根据实施方式，第一沟槽115的最大宽度w在0.2μm到10μm的范围。如果第一沟槽115具有锥度，那么最大宽度是指第一沟槽115的沿横向x包含相向侧壁的最大距离的那部分。
根据实施方式，第一沟槽115的长宽比在10至50的范围。长宽比被定义为沟槽的深度除以其宽度。
图2A示出了形成在图1所示的半导体层125的部分126中的平面栅晶体管单元的横截面示意图。半导体层125的表面140处形成P掺杂体区145和n+掺杂源区150。P掺杂体区145和n+掺杂源区150电耦接至表面140的源接触155。位于源接触155和P掺杂体区145间的电接触可通过布置P+掺杂体接触区来改良。在图2A中以简化方式示出的源接触155可包括布置在形成于表面140上的介电层的开口中的导电材料。例如，接触体可以是接触插塞或接触线，其包括：高度掺杂多晶半导体材料、金属硅化物（TiSi2、MoSi2、WSi2、PtSi2中的任一种或任何组合）和/或金属（例如，W、Al、Cu、Pd、Ti、Ta、TiN、TaN中的任一种或任何组合）、或其组合。
包括栅极电介质161和栅电极162的平面栅极结构160邻接表面140。图2A中所示的平面栅晶体管单元的电流沿垂直方向y在表面140处的源接触体155与第二侧130（见图1）处的接触体135之间流动。在图1和2A中所示示例中，位于第二侧处的接触体135是漏接触。
图2B示出了形成在图1所示的半导体层125的部分126中的沟槽栅晶体管单元的一部分的横截面示意图。栅极沟槽171从表面140延伸至半导体层125中。图2B中所示的实施方式中，栅极沟槽171的底面终止在第一沟槽115的顶面上方。换言之，栅极沟槽171在半导体层125中终止且不穿过半导体层125延伸到半导体衬底110。根据其他实施方式，栅极沟槽171穿过半导体层125延伸到半导体衬底110中。栅极沟槽171包括被电介质172包围的栅电极173。电介质172的位于栅电极173与P掺杂体区175之间的那部分构成栅极电介质。例如，栅极电介质可为热氧化物。电介质172可进一步包括电介质材料和/或层，如沉积的氧化物，这种氧化物由化学气相沉积（CVD）沉积以及诸如Si3N4的氮化物。
在半导体层125的表面140处，形成P掺杂体区175和n+掺杂源区180。P掺杂体区175和n+掺杂源区180电耦接至表面140的源接触185。位于源接触185与P掺杂体区175之间的电接触可通过布置P+掺杂主体接触区来改良。在图2B中以简化方式示出的源接触185可包括布置在形成于表面140上的介电层的开口中的导电材料。例如，接触体可包括接触插塞或接触线，其包括：高度掺杂多晶半导体材料、金属硅化物（TiSi2、MoSi2、WSi2、PtSi2中的任一种或任意组合）和/或金属（W、Al、Cu、Pd、Ti、Ta、TiN、TaN中的任一种或任意组合）、或其组合。
图2B中所示的沟槽栅晶体管单元的电流沿垂直方向y在表面140处的源接触185与第二侧130（见图1）的接触体135之间流动。在图1和2B所示的示例中，位于第二侧处的接触体是漏接触。邻接栅极电介质的沟道区域187的导电性可经由施加至栅电极173的栅电压控制。
包围栅电极173的电介质173的厚度可不一致，例如，在栅电极173下方更厚。此外，在栅电极173下方，可在栅极沟槽171中形成一个或多个附加电极，且该附加电极与半导体层125介质隔离。该一个或多个附加电极可电浮接或连接至电压，例如，一个或多个附加电极可连接至源电位。
图3A是图1所示的第一沟槽115的横截面示意图。在图3A中所示的实施方式中，第一沟槽115被部分地填充导电材料1650。
根据实施方式，导电材料1650包含碳（C）、钼（Mo）、钛（Ti）、钽（Ta）、铜（Cu）和铝（Al）中的至少一种。
根据实施方式，空隙164可形成在部分地填充第一沟槽115的导电材料1650中。导电材料1650也可至少部分地多孔。例如，多孔Cu和/或多孔Mo可形成导电材料1650的一部分或构成导电材料。例如，多孔金属可通过所谓的等离子体粉尘（plasmadust technology）技术形成。
根据几个实施方式，导电材料1650和半导体衬底110的热膨胀系数相差小于500%或300%。当考虑到相对于半导体衬底110的热膨胀系数来选择导电材料1650时，可避免或减少由于热平衡诱发的应力导致对器件可靠性的负面影响。鉴于此，在降低由热平衡诱发的应力方面，导电材料1650的多孔结构或含有空隙的结构可能是有利的。
图3B示出了图1所示的第一沟槽115被部分填充导电材料1651及导电材料1651顶部的扩散阻挡层167的横截面示意图。图3A中所示的导电材料1650的上述细节适用于导电材料1651。扩散阻挡层167可包括TiN、TaN、Si3N4、SiO2中的任意一种及其组合。在应当避免或最小化导电材料1651从第一沟槽115的顶面向外的扩散的情况下，布置扩散阻挡层167是有利的。
图3C示出了图1所示的第一沟槽115被部分填充导电材料1651及内衬在导电材料1651的顶部和侧部的扩散阻挡层168的横截面示意图。图3A中所示的导电材料1650的细节适用于导电材料1651。扩散阻挡层168可包括TiN、TaN、Si3N4、SiO2中的任意一种或其组合。例如，内衬于导电材料1651的侧面的扩散阻挡层168的那部分与内衬于导电材料1651的顶面的扩散阻挡层168的那部分可以是不同的材料。例如，扩散阻挡层168的内衬于导电材料1651侧面的那部分可包含TiN，而扩散阻挡层168的内衬于导电材料1651顶面的那部分可包含Si3N4。在应当避免或最小化导电材料1651从第一沟槽115的顶面或侧面向外扩散的情况下，设置扩散阻挡层167是有利的。图3C示出了在半导体衬底110变薄及涂覆接触层135之后的横截面示意图。根据实施方式，扩散阻挡层168最初也存在于导电材料1651下方且可在薄化处理中移除。然而，扩散阻挡层168也可保持存在于接触层135和导电材料1651之间。
图3D示出了图1所示的第一沟槽115被部分填充导电材料1652及在第一沟槽115的底面的电介质169的横截面示意图。图3A中所示的导电材料1650的细节适用于导电材料1652。例如，电介质169的底面的材料可通过考虑其对于半导体衬底110的材料的蚀刻选择性而选定。例如，电介质169可包括或由SiO2组成，半导体衬底可包括或由Si组成。在这种情况下，在到达电介质169时，在移除半导体衬底的过程中，特征出现变化。这在特征（例如，耐磨性）方面的变化可用于终止对半导体衬底的移除。为充分利用导电材料1652的优势，可实现半导体衬底110的选择性接触掺杂133，这确保导电材料1652和接触层133之间的低欧姆电阻。此外或可替代地，电介质169可在涂覆接触层133之前移除。
图3A和3D所示的填充是示例。可使用不同的示例中所示的利用导电材料的其他填充或填充物组合。例如，也可在第一沟槽115的底面布置扩散阻挡层。
图4示出了沿图1中的线A-A'的n掺杂及P掺杂的分布的示意图。
半导体衬底110包括本底P掺杂。例如，P掺杂半导体晶圆，例如，P掺杂12英寸硅片（如掺杂有硼的8Ωcm/12英寸硅晶圆）可形成半导体衬底110。P本底掺杂是不变的，并在图4中以P表示。半导体衬底110还包括n型掺杂剂。n型掺杂剂的浓度分布从第一沟槽115到半导体衬底110沿横向x递减。例如，n型掺杂剂可从第一沟槽115的侧壁的扩散源向外扩散进入周围的半导体衬底110。因此，先前P掺杂的半导体晶圆变为n掺杂。在替代性实施方式中，在p掺杂半导体衬底110上生长（例如，外延生长）n掺杂层。在这种情况下，可选定任何形式的n掺杂浓度，而P本底掺杂只可存在于例如半导体衬底110的向外扩散。
除如图3A至3D的示例所示的第一沟槽115中的导电填充物外，经由第一沟槽115中的扩散源的半导体衬底110的掺杂进一步使得半导体衬底110的导电性提高，由此形成于半导体衬底110中的垂直半导体器件的寄生电阻减少。换言之，这些措施使得在垂直半导体器件中导通状态电阻降低。
图5示出了可单独或组合地用作图1所示的第一沟槽115的几何结构的几个沟槽几何结构的平面示意图。例如，第一沟槽115可形成围绕分立式半导体或集成电路的有源区的闭环1151。闭环也可包围分立式半导体的结终端区或集成电路的器件区域。作为另一示例，第一沟槽115可布置成具有圆形或椭圆形截面面积的柱形图案1152。作为又一示例，第一沟槽115可布置成条1153或一系列的条形段1154。可应用这些或另外的几何结构的任何组合。例如，形成闭环1151的沟槽可具有比条1153或段1154大的宽度。在这种情况下，形成闭环1154的沟槽可延伸入半导体衬底比条1153和段1154更深。由闭环1154包围的分隔装置可通过从闭环1154的后面到底部及从闭环的正面到顶面移除半导体材料来实现。当将P扩散出形成为闭环1154的沟槽，即，将P扩散出围绕有源器件区域的沟槽外时，可设置高效的吸气层（getter layer），其发挥作用防止重金属从芯片边缘扩散入有源器件区域。
例如，可适当地选择相邻的第一沟槽115和导电填充物之间的横向距离以将半导体衬底的导电性调整至对于此处待形成的器件所需要的。
图6A和6B示出了根据实施方式的半导体晶圆600的横截面示意图和平面示意图。半导体晶圆的直径可为4英寸（100mm），6英寸（150mm），8英寸（200mm），12英寸（300mm）或更大。图6A中的平面示意图所示的半导体晶圆600是包括硅衬底610的半导体晶圆600。如图6B的横截面示意图中所示，第一沟槽615从第一侧620延伸入硅衬底610。通过外延工艺、或由适当的退火工艺与硅层后续的外延沉积结合使靠近表面的硅的回流工艺、或晶圆键合法来实现的硅层625邻接硅衬底610并覆盖在第一侧620的第一沟槽615。第一沟槽615的顶面和底面可包括弯曲的形状，这是由于通过热处理半导体衬底610在形成罩住第一沟槽615的顶面的硅层625时，半导体衬底610的材料的表面扩散介导回流（surfacediffusion mediated reflow）。图5示出了平面示图内的第一沟槽615的几何结构的示例。图3A至3D和4中示出了第一沟槽615的填充的示例和半导体衬底掺杂分布。
图6C示出了图6A和6B中所示的硅衬底的一部分的扫描电子显微图。
图7示出了根据实施方式的半导体器件的制造方法的简化流程图。
流程步骤S700包括形成从第一侧穿入半导体衬底的第一沟槽。
流程步骤S710包括形成在第一侧邻接半导体衬底的半导体层，其中，半导体层覆盖第一侧的第一沟槽。
流程步骤S720包括在与第一侧相反的半导体衬底的第二侧形成接触。
根据实施方式，在半导体衬底上形成半导体层包括在周围环境包含氢时在温度范围为900℃至1400℃热处理半导体衬底，在第一侧使半导体衬底的材料的表面扩散介导回流并通过外延附生沉积第一半导体层。然后，在此半导体层上可沉积成外延硅层。
根据又一个实施方式，该方法还包括在第一沟槽的底部形成电介质。当移除半导体衬底的处理时到达位于第一沟槽底部的电介质时，电介质可造成从第二侧移除半导体衬底的处理停止。
根据又一个实施方式，该方法还包括在形成半导体层之前用导电材料至少部分填充第一沟槽。至于导电材料和可选的扩散阻挡层，请参考图3A至3D中的实施方式和以上说明中的相关部分。
根据又一个实施方式，该方法还包括在第一沟槽中形成扩散源并通过热处理从扩散源将掺杂剂引入半导体衬底。由此，可形成如图4中所示的扩散分布。
图8A示出了从第一侧820形成第一沟槽815之后的半导体衬底的横截面示意图。例如，半导体衬底可以是12英寸（300mm）半导体晶圆或可包括直径小于12英寸，例如8英寸（200mm）或6英寸（150mm)的晶圆，或可包括直径大于300mm的晶圆。可通过适当的蚀刻工艺（例如，干法刻蚀等的各向异性刻蚀）将第一沟槽815形成至半导体衬底810中。
根据实施方式，第一沟槽815可蚀刻成深度d在20μm至200μm的范围。沟槽的长宽比介于10至50之间。半导体衬底810中将被蚀刻的部分可由蚀刻掩膜（例如，在半导体衬底810上的图案化硬掩膜或图案化光致抗蚀剂）限定。
选择性扩散源，例如，掺杂玻璃或高掺半导体层，可在清洗工艺后布置在沟槽815的侧壁。可进行加热（thermal heating）以将掺杂剂从掺杂剂源扩散入围绕第一沟槽815的半导体衬底810。当增加热平衡，例如通过增加加热的持续时间和/或增加加热过程中最高温度时，将增加掺杂剂数量及这些掺杂剂进入半导体衬底810的扩张。被引入半导体衬底810的掺杂剂可导致原来的导电类型的改变。例如，当开始是P掺杂硅晶片且将n型掺杂剂（例如，P）通过从扩散源扩散出经过第一沟槽815的侧壁引入硅晶圆时，硅晶圆的导电类型可从p型设置成n型（反之亦然）。当增加热平衡但减小邻近的第一沟槽815间的间隔时，由于相对的第一沟槽815引起的扩散分布的重叠，沿着横向的掺杂浓度的改变可减小。在扩散工艺（例如，蚀刻工艺）之后，从沟槽移除扩散源。
参考图8B所示的半导体衬底810的横截面示意图，沟槽815被部分填充导电材料865。例如，导电材料865包括或由C组成。这在从与第一侧820相反的第二侧830移除半导体衬底810时，允许在碳的底面设置自对准阻挡。
第一沟槽815可部分或完全地由导电材料865填充并且导电材料865可包括空隙。除组成导电材料865的C外，也可使用其他的导电材料。深加工过程中，在抵消由作用于半导体衬底810的热平衡诱发的应力方面，热膨胀系数与半导体衬底810的材料相似的导电材料是有利的。根据其他实施方式，可使用金属和/或金属合金或不同的金属和/或金属合金堆叠层调整第一沟槽815中的导电材料865的期望热膨胀系数。
如果填充入第一沟槽815的导电材料865的扩散常数相对于半导体衬底的材料810而言过高，第一沟槽815的表面和/或导电材料865的顶面可能被扩散阻挡层覆盖，如一个或多个TiN、TaN、Si3N4、SiO2。也可使用这些材料的组合。扩散阻挡层可将形成于第一沟槽815中的导电材料865封进内部。换言之，扩散阻挡层可内衬于沟槽的侧壁和填入第一沟槽815中的导电材料865的顶面。因此，可避免或减少加工设备或其他晶圆受到向外扩散的污染。这进一步允许可使用更多的导电材料。
参考图8C中所示的半导体衬底810的横截面示意图，半导体层825形成在半导体衬底810上并且与半导体衬底810在第一侧820邻接。半导体层825覆盖第一侧820的第一沟槽815。在沟槽不是被完全填充导电材料的情况下，半导体层825的形成包括：例如，通过热处理半导体衬底810使半导体衬底810的材料的表面扩散介导回流。在硅衬底的情况下，在包括氢的环境中温度可介于900℃与1400℃。可替换地，不完全填充有导电材料的沟槽剩余的体积可由通过横向外延或横向外延过生长横向外延的硅填充。
通过材料的表面扩散介导回流，可磨圆第一沟槽815的顶面的边缘且可封闭第一沟槽815的顶面。随后，在第一侧820，半导体层825通过外延附生而沉积在半导体衬底810上。如果沟槽完全填充有导电材料，硅层的横向外延将导致均质硅层825。沉积在半导体衬底810上的半导体层825的材料可对应于半导体衬底810的材料。根据另一实施方式，这些材料可不相同，导致沉积在半导体衬底810上的半导体层825中诱发应力。通过恰当选择材料，可使沉积在半导体衬底810上的半导体层825中诱发的应力保持在对于半导体器件深加工可接受的范围内。
根据实施方式，在通过半导体衬底810的材料的表面扩散介导回流封闭第一沟槽815后，以及在其上沉积半导体层之前，在第一侧820的半导体衬底810的一部分可移除。例如，可使用化学机械抛光（CMP）。
沉积在半导体衬底810上的半导体层825可通过外延附生来形成，当形成作为硅层的半导体层825时可利用加工气体，如三氯硅烷（TCS）或二氯甲硅烷（DCS）。
例如，当通过半导体基板810的材料的表面扩散介导回流封闭第一沟槽815时，第一沟槽的宽度可在0.2μm至5μm之间。
因为位于相对的第一沟槽815之间的台面区域缺乏形成的闭合，晶圆的顶面可相对于半导体衬底810偏转，导致有利的晶圆弯曲减小。
随后可用已知的工艺用于在半导体层825中形成集成电路的电路元件或分立式半导体，例如，用于在半导体层825中形成p和n掺杂半导体区的离子注入工艺。图2A和2B中示出了可能形成于半导体层825中的器件的示例。
参考图8D中所示的半导体衬底810的横截面示意图，半导体衬底810的一部分从第二侧830移除。根据实施方式，从第二侧向上移除半导体衬底810直至第一沟槽815的底面。根据另一实施方式，半导体衬底810的移除在到达第一沟槽815的底面之前结束。换言之，半导体衬底810的一部分可保持在第一沟槽815的底面下方。
当从第二侧830向上移除半导体衬底810直至第一沟槽815的底面时，到达第一个沟槽815的底面的材料（如C或SiO2）可导致在移除半导体衬底810的过程中特征的改变，这可用于终止移除半导体衬底810的过程。
参考图8E中所示的半导体衬底810的横截面示意图，包含诸如金属或金属合金的导电材料层或层堆叠的接触体835形成在第二侧830。在背面金属化沉积之前，穿过第二侧830的离子注入可通过例如利用高剂量磷或硼注入以形成低欧姆n或P背面接触的方法实现。
后续可用更多已知的工艺以制造所期望的半导体器件。至于导电材料865和选择性的填充在第一沟槽815的扩散阻挡层，请参考图3A至3D中所示的实施方式。
根据另一实施方式，第一沟槽815可在封闭位于第一侧820的第一沟槽815之后填充导电材料。换言之，第一沟槽815可在从第二侧830移除半导体衬底810直至第一沟槽815的底面之后被填充导电材料。
上述器件和方法通过利用上述措施之一或其组合的半导体衬底的导电性使垂直半导体器件的导通状态电阻减少。
上述方法改进半导体器件的散热和热容量。这允许省去其他措施（例如，正面冷却和/或倒装芯片安装）。
第一沟槽815的对准可适应半导体层825中光学元件的对准。例如，条形第一沟槽815可平行于半导体层825中的条形晶体管单元而对准。因此，可减少晶圆弯度或衬底弯度。
进一步，例如，包含空隙的第一沟槽815可布置在半导体器件的边缘区域（如晶体管单元阵列的边缘区域）。沟槽815可部分或全部填充有电介质（如SiO2）。这允许在操作体二极管时减少或避免在边缘区域载流子诸如（与IGBT和二极管的高动态粗糙度（HDR）相似）。
尽管在此讨论和描述的是具体的实施方式，但本领域技术人员可以领会在不偏离本发明的范围下，各种替代性和/或等价执行方式可代替所示及该具体的实施方式。本申请旨在覆盖所有在此讨论的具体实施方式的改编或变形。因此，本发明仅受权利要求及其等同物的限制。

Claims (24)

1.一种半导体器件，包括：
半导体衬底；
第一沟槽，从第一侧延伸至所述半导体衬底中或穿过所述半导体衬底；
半导体层，在所述第一侧邻接所述半导体衬底，其中，所述半导体层在所述第一侧覆盖所述第一沟槽；以及
接触体，位于所述半导体衬底的与所述第一侧相对的第二侧，
其中，所述半导体衬底包括p型掺杂剂和n型掺杂剂；且其中，所述p型掺杂剂的浓度低于所述n型掺杂剂的浓度，所述n型掺杂剂的浓度分布沿着与所述第一侧平行的横向方向从所述第一沟槽的侧壁至所述半导体衬底而减小。
2.根据权利要求1所述的半导体器件，还包括：
延伸至所述半导体层中的第二沟槽，其中，所述第二沟槽的底面终止在所述半导体层内并且在所述半导体衬底上方。
3.根据权利要求1所述的半导体器件，其中，所述半导体衬底是包含硼浓度在5×1014cm-3至5×1015cm-3之间的硅衬底。
4.根据权利要求1所述的半导体器件，其中，沿着正交于所述第一侧的垂直方向，所述第一沟槽的深度在20μm至200μm的范围。
5.根据权利要求1所述的半导体器件，其中，所述第一沟槽的最大宽度在0.2μm至10μm的范围。
6.根据权利要求1所述的半导体器件，其中，所述第一沟槽的长宽比在10至50的范围。
7.根据权利要求1所述的半导体器件，其中，所述半导体层的厚度在5μm至15μm的范围。
8.根据权利要求1所述的半导体器件，其中，第一沟槽至少部分地填充有导电材料。
9.根据权利要求8所述的半导体器件，其中，所述第一沟槽包括导电材料；且其中，所述导电材料与所述半导体衬底的热膨胀系数相差小于500％。
10.根据权利要求8所述的半导体器件，其中，所述导电材料包括C、Mo、Cu、Al、Ti、Ta和W中的至少一种。
11.根据权利要求8所述的半导体器件，还包括在所述第一沟槽中的空隙。
12.根据权利要求8所述的半导体器件，其中，所述导电材料至少部分有孔。
13.根据权利要求8所述的半导体器件，还包括位于所述导电材料和所述半导体衬底之间的扩散阻挡层。
14.根据权利要求13所述的半导体器件，其中，所述扩散阻挡层包括TiN、TaN、Si3N4、SiO2、和TiW中的至少一种。
15.根据权利要求1所述的半导体器件，其中，所述第一沟槽包围所述半导体器件的有源区。
16.根据权利要求1所述的半导体器件，还包括多个第一沟槽，其中，在与所述第一侧平行的平面内，所述第一沟槽的几何结构包括一个或多个条、闭环、圆、椭圆、和多边形。
17.根据权利要求1所述的半导体器件，其中，所述第一沟槽被布置在所述半导体器件的边缘区域中。
18.一种半导体晶圆，包括：
硅衬底；
第一沟槽，从第一侧延伸入至所述硅衬底中；
半导体层，位于所述硅衬底上，其中，所述半导体层在所述第一侧覆盖所述第一沟槽，
其中，所述硅衬底包括p型掺杂剂和n型掺杂剂；且其中，所述p型掺杂剂的浓度低于所述n型掺杂剂的浓度，所述n型掺杂剂的浓度分布沿着与所述第一侧平行的横向方向从所述第一沟槽的侧壁至所述硅衬底而减小。
19.一种制造半导体器件的方法，包括：
形成从第一侧至半导体衬底中的第一沟槽；
形成在所述第一侧与所述半导体衬底邻接的半导体层，其中，所述半导体层在所述第一侧覆盖所述第一沟槽；
在所述半导体衬底的与所述第一侧相对的第二侧形成接触体，
其中，所述半导体衬底包括p型掺杂剂和n型掺杂剂；且其中，所述p型掺杂剂的浓度低于所述n型掺杂剂的浓度，所述n型掺杂剂的浓度分布沿着与所述第一侧平行的横向方向从所述第一沟槽的侧壁至所述半导体衬底而减小。
20.根据权利要求19所述的方法，其中，在所述半导体衬底上形成半导体层包括通过在包含氢的周围环境中并且在温度范围在900℃到1400℃热处理所述半导体衬底，使所述半导体衬底的材料的表面在所述第一侧扩散介导回流，并通过外延附生沉积第一半导体层。
21.根据权利要求19所述的方法，还包括在所述第一沟槽的底部形成电介质。
22.根据权利要求19所述的方法，还包括在形成所述半导体层之前用导电材料至少部分填充所述第一沟槽。
23.根据权利要求19所述的方法，还包括在所述第一沟槽中形成扩散源；并通过热处理从所述扩散源将掺杂剂引入所述半导体衬底中。
24.根据权利要求19所述的方法，还包括从所述第二侧去除所述半导体衬底直至所述第一沟槽的底部。
CN201310349620.1A 2012-08-10 2013-08-12 半导体衬底中包含沟槽的半导体器件及其制造方法 Active CN103579325B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/571,455 2012-08-10
US13/571,455 US9219144B2 (en) 2012-08-10 2012-08-10 Semiconductor device including a trench in a semiconductor substrate and method of manufacturing a semiconductor device

Publications (2)

Publication Number Publication Date
CN103579325A CN103579325A (zh) 2014-02-12
CN103579325B true CN103579325B (zh) 2016-12-28

Family

ID=49999322

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310349620.1A Active CN103579325B (zh) 2012-08-10 2013-08-12 半导体衬底中包含沟槽的半导体器件及其制造方法

Country Status (3)

Country Link
US (3) US9219144B2 (zh)
CN (1) CN103579325B (zh)
DE (1) DE102013108473B4 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015041638A (ja) * 2013-08-20 2015-03-02 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
CN104979440B (zh) * 2014-04-10 2019-01-18 传感器电子技术股份有限公司 复合衬底
DE102015116579A1 (de) 2015-09-30 2017-03-30 Infineon Technologies Austria Ag Superjunction-Halbleitervorrichtung und Herstellungsverfahren
US10324530B2 (en) * 2015-12-14 2019-06-18 Facebook Technologies, Llc Haptic devices that simulate rigidity of virtual objects
DE102016116499B4 (de) * 2016-09-02 2022-06-15 Infineon Technologies Ag Verfahren zum Bilden von Halbleiterbauelementen und Halbleiterbauelemente
KR102618350B1 (ko) * 2016-12-14 2023-12-28 삼성디스플레이 주식회사 디스플레이 장치
US10593659B2 (en) 2017-03-30 2020-03-17 International Business Machines Corporation Deep high capacity capacitor for bulk substrates
DE102017212871A1 (de) * 2017-07-26 2019-01-31 Robert Bosch Gmbh Verfahren zum Herstellen einer vertikalen Feldeffekttransistorstruktur und entsprechende vertikale Feldeffekttransistorstruktur
IT201700119626A1 (it) * 2017-10-23 2019-04-23 Valentina Daddi Transistor ibrido a gate isolato multi-struttura e multi-materiale
US11380597B2 (en) * 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
DE102018122739A1 (de) 2018-09-17 2020-03-19 Infineon Technologies Ag Halbleitervorrichtung mit einer Dotierstoffquelle
CN112201694B (zh) * 2020-10-20 2022-03-08 杭州电子科技大学温州研究院有限公司 一种半椭圆氧化沟槽ldmos晶体管
CN112466942B (zh) * 2020-12-01 2022-06-07 西安电子科技大学 具有插指型金刚石散热层的GaN HEMT及制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040208A (en) * 1997-08-29 2000-03-21 Micron Technology, Inc. Angled ion implantation for selective doping

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4371521B2 (ja) * 2000-03-06 2009-11-25 株式会社東芝 電力用半導体素子およびその製造方法
JP2005150522A (ja) * 2003-11-18 2005-06-09 Toshiba Corp 半導体装置及びその製造方法
JP2009141218A (ja) 2007-12-07 2009-06-25 Toshiba Corp 半導体装置
US7893488B2 (en) * 2008-08-20 2011-02-22 Alpha & Omega Semiconductor, Inc. Charged balanced devices with shielded gate trench
US8021926B2 (en) * 2009-09-22 2011-09-20 Freescale Semiconductor, Inc. Methods for forming semiconductor devices with low resistance back-side coupling

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040208A (en) * 1997-08-29 2000-03-21 Micron Technology, Inc. Angled ion implantation for selective doping

Also Published As

Publication number Publication date
US20140042593A1 (en) 2014-02-13
CN103579325A (zh) 2014-02-12
DE102013108473B4 (de) 2020-06-25
US9219144B2 (en) 2015-12-22
US9570566B2 (en) 2017-02-14
US20160035842A1 (en) 2016-02-04
US20170148887A1 (en) 2017-05-25
US9842904B2 (en) 2017-12-12
DE102013108473A1 (de) 2014-02-13

Similar Documents

Publication Publication Date Title
CN103579325B (zh) 半导体衬底中包含沟槽的半导体器件及其制造方法
KR101626290B1 (ko) 수직 전하-보상 구조물 및 표면-아래 접속층을 구비한 반도체 소자 및 방법
KR101279574B1 (ko) 고전압 반도체 소자 및 그 제조 방법
CN101632151B (zh) 可实现三维电荷耦合的高电压半导体功率组件结构
KR101632938B1 (ko) 밀봉 플러그를 구비한 반도체 트렌치 구조와 방법
US7394144B2 (en) Trench semiconductor device and method of manufacturing it
TWI542018B (zh) 帶有集成肖特基二極體的mosfet
CN105702739B (zh) 屏蔽栅沟槽mosfet器件及其制造方法
CN103650148B (zh) 绝缘栅双极晶体管
TWI390728B (zh) 超接合半導體裝置結構及方法
US9570596B2 (en) Super junction semiconductor device having a compensation structure
US6998680B2 (en) Semiconductor device
CN103311275B (zh) 半导体器件和制造半导体器件的方法
US10290735B2 (en) Methods of manufacturing a semiconductor device with a buried doped region and a contact structure
JP2003086800A (ja) 半導体装置及びその製造方法
US7795671B2 (en) PN junction and MOS capacitor hybrid RESURF transistor
CN108695393B (zh) 包括沟槽结构中的场电极和栅电极的半导体器件及制造方法
CN103137688B (zh) 一种沟槽mos结构半导体装置及其制造方法
US11227945B2 (en) Transistor having at least one transistor cell with a field electrode
TW201631759A (zh) 具場電極功率電晶體
CN113224146A (zh) 晶体管器件和制备晶体管器件的栅极的方法
CN105826375A (zh) 一种沟槽型半超结功率器件及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant