CN101573800A - Pn结及mos电容器混合减低表面场晶体管 - Google Patents

Pn结及mos电容器混合减低表面场晶体管 Download PDF

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CN101573800A
CN101573800A CN200780049209.5A CN200780049209A CN101573800A CN 101573800 A CN101573800 A CN 101573800A CN 200780049209 A CN200780049209 A CN 200780049209A CN 101573800 A CN101573800 A CN 101573800A
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史蒂文·莱比格尔
加里·多尔尼
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Fairchild Semiconductor Corp
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Abstract

本发明揭示一种高电压半导体装置，例如RESURF晶体管，其具有包括减低的导通状态电阻在内的改善的性质。所述装置包括：半导体衬底；提供于所述衬底中的源极区域及漏极区域；其中所述源极区域与所述漏极区域彼此横向间隔开；及位于所述衬底中所述源极区域与所述漏极区域之间的漂移区域。所述漂移区域包括具有延伸于所述源极区域与所述漏极区域之间的至少两个间隔沟槽式电容器的结构；且进一步包括具有至少第一导电率类型的第一区域、第二导电率类型的第二区域及所述第一导电率类型的第三区域的堆叠，其中所述堆叠在所述源极区域与所述漏极区域之间且在所述至少第一与第二沟槽式电容器之间延伸并电连接到所述第一及第二沟槽式电容器。当所述装置处于导通状态时，电流穿过所述第二导电率类型的所述第二区域在所述源极与漏极区域之间流动；且当所述装置处于关断/阻断状态时，所述第二导电率区域分四路耗尽到所述堆叠的所述第一及第三区域中且耗尽到所述第一及第二沟槽式电容器中。

Description

PN结及MOS电容器混合减低表面场晶体管
技术领域
本发明一般涉及半导体装置且明确地说涉及高电压减低表面场(RESURF)晶体管装置及制造此类装置的方法。
背景技术
垂直及横向高电压晶体管两者均广泛用于电力应用中。在导通状态中，需要晶体管具有低导通电阻以使传导损失降到最低。在关断状态中，需要晶体管具有高击穿或阻断电压。横向RESURF晶体管是具有彼此横向间隔的源极及漏极且具有位于源极与漏极区域之间的漂移区域的横向装置。在导通状态中，电流穿过漂移区域在源极与漏极之间流动，而在关断状态中，漂移区域被耗尽以防止电流流动。为增加功率晶体管的性能特性，2000年8月1号颁布的美国专利6,097,063(发明人Fujihiro(富士広))以及2001年3月27号颁布的美国专利6,207,994B1(发明人Rumennik(儒曼尼科)等人)揭示在横向装置中使用具有交替层的第一及第二导电率类型(p/n)的半导体材料的漂移区域。1993年1月1号颁布的美国专利5,216,275(发明人Chen(陈))及1995年8月1号颁布的美国专利5,438,215(发明人Tihanyi(蒂汉尼))将此概念应用于垂直装置。以下论文值得关注的是其揭示在VDMOS装置中于漂移区域的侧壁处使用金属厚氧化物以增加阻断电压或增加背景掺杂-“Oxide-Bypassed VDMOS(OBVDMOS0：An Alternative to Superjunction High Voltage MOS Power Devices”，byLiang et al.，IEEE Electron Devices Letters，Vol.22.NO.8，Pages 407-409，August 2001(“氧化物旁通VDMOS(OBVDMOS0：超级结高电压MOS电力装置”，Liang(梁)等人，IEEE电子装置通讯，卷22，编号8，页407-409，2001年8月)。本发明相对于这些技术的优点是当处于电压阻断状态时使用四侧耗尽区域而非使用两侧耗尽区域。
存在对既具有高阻断电压又具有甚至更低导通状态电阻的晶体管的持续需要。本发明解决此需要。
发明内容
根据本发明，提供一种用来解决以上所论述需要的解决方案。
根据本发明的特征，提供
半导体装置，其包含：
半导体衬底；
提供于所述衬底中的源极区域及漏极区域；其中所述源极区域与所述漏极区域彼此横向间隔开；
位于所述衬底中所述源极区域与所述漏极区域之间的漂移区域；
其中所述漂移区域包括具有延伸于所述源极区域与所述漏极区域之间的至少第一及第二沟槽式电容器的结构，所述沟槽式电容器具有内板及邻近于所述内板的介电材料；且进一步包括具有至少第一导电率类型的第一区域、第二导电率类型的第二区域及所述第一导电率类型的第三区域的堆叠，其中所述堆叠位于所述至少第一与第二沟槽式电容器之间且与所述第一及第二沟槽式电容器的所述电介质接触；
其中当所述装置处于导通状态时，电流穿过所述第二导电率类型的所述第二区域在所述源极与漏极区域之间流动；且当所述装置处于关断/阻断状态时，所述第二导电率区域分四路耗尽到所述堆叠的所述第一及第三区域且耗尽到所述第一及第二沟槽式电容器。
根据本发明的另一特征，提供
一种制造半导体装置的方法，其包含：
提供具有彼此横向间隔开的源极及漏极的半导体衬底，其中在所述源极与漏极区域之间具有漂移区域；
在所述漂移区域中形成一区，所述区包括至少第一导电率类型的第一区域、位于所述第一区域顶部上的第二导电率类型的第二区域及位于所述第二区域顶部上的所述第一导电率类型的第三区域；及
在所述区中产生延伸于所述源极与所述漏极之间的至少两个间隔沟槽式电容器，其中在所述沟槽式电容器之间形成与所述沟槽式电容器电连接的所述第一、第二及第三区域的堆叠。
本发明具有以下优点：
1.提供在阻断模式中除PN结耗散外还使用MOS电容器耗散的RESURF高电压晶体管。此允许漂移区域中的显著较高掺杂且因此极大地减低晶体管的导通状态电阻。
2.通过在阻断模式中使用来自四个侧的耗散，存在优于已知的两侧耗散的改进，因此改进晶体管的性质。
附图说明
通过结合附图阅读以下更详细说明，将更好地了解前文所述及其它特征、特性、优点及本发明的大体内容。
图1是本发明的实施例的平面示意图；
图2是沿图1中的线2-2截取的正视横截面示意图；
图3是沿图1中的线3-3截取的正视横截面示意图；
图4A-4C是沿图1中的线4A、B、C-4A、B、C截取的横截面示意图；
图4D是沿图1中的线4D-4D截取的横截面示意图；
图5A-5E是图解说明制作图1的本发明中的选择细节的横截面示意图；
图6A-6D是图解说明制作图1的本发明中的其它选择细节的横截面示意图；
图7是图1中所示实施例中的两者连同单个衬底上的额外装置与环绕三个装置中的每一者的隔离区域的平面示意图；
图8是沿图7中的线8-8截取的正视横截面示意图；及
图9是图1中所示实施例连同CMOS集成电路布置中的互补实施例的正视横截面示意图。
应了解，出于清晰的目的且在认为适当时，已在图中重复参考编号以指示对应的特征。此外，在一些情况下，已使图中各种对象的相对大小发生变形以更清楚地显示本发明。
具体实施方式
现在提供本发明的实例性实施例。尽管这些实施例图解说明基于硅的电力装置的概念的应用，但打算的是本文所揭示的原理将应用于各种半导体装置，包括以化合物半导体材料(例如，碳化硅)形成的那些半导体装置以及集成电路。虽然装置的实例参考特定导电率类型，且并入有特定材料(例如，电介质及导体)，但这些仅是实例性的且并不打算将本发明局限于并入有此类常规组件或方法的实施例。例如，本文中所示的实施例是NMOS晶体管，但本发明还可通过反转掺杂极性而应用于PMOS晶体管。
现在参照图1，其显示本发明的实施例。如图所示，RESURF晶体管10包括半导体P-衬底12，其具有：具有源极触点16的源极14、p-阱18、栅极20、具有漏极触点24的漏极22以及位于源极14与漏极22之间的漂移区域26。漂移区域26并入有沟槽式MOS电容器/P+/N+结混合结构。更明确地说，混合结构26包括由p+/N+堆叠30分离的间隔沟槽式电容器28。P+/N+堆叠30中的每一者具有垂直P+区域32，所述区域还显示于图4D中，且所述区域与其相应堆叠中的每一P+及N+层接触，使得所有P+区域彼此并联连接，且同样地，使得所有N+区域彼此并联连接。P+掺杂区域32还通过由图4D中的连接34示意性表示的金属层电系接到填充于沟槽式电容器28中的多晶硅。区域32将P+/N+堆叠26中的P+层与沟槽式电容器28中的P+多晶硅连接在一起，以在P+/N+堆叠26中的N+层中形成四侧耗尽区域，如图4C中所示。
图2及3是沿图1中的线2-2及3-3截取的相应正视横截面示意图。图2显示沟槽式电容器28中的一者的轮廓，其显示二氧化硅介电层40及多晶硅42。图2及3以箭头44指示当RESURF晶体管10导通时电流穿过P+/N+堆叠26在源极14与漏极22之间流动。P+/N+堆叠25包括与第二导电率类型N+的区域48交错的第一导电率类P+的区域46。如图2及3中所示，电流主要穿过N+区域48流动。
图4A-4D是沿图1中的线4A、B、C-4A、B、C截取的横截面示意图。如图所示，沟槽式电容器26包括沟槽50，所述沟槽50具有填充有掺杂多晶硅42的二氧化硅侧壁40。N+区域48取决于RESURF晶体管10是导通还是关断而作为传导/阻断区域。
图4B显示处于导通状态的半导体装置，其中P+/N+堆叠26的P+/N+层与沟槽式电容器28的结经偏压而不使N+掺杂传导区域48耗尽。图中将电流显示为流动到图的平面中，如由带叉的圆圈56所描绘。
图4C显示处于关断状态的半导体装置，其中P+/N+堆叠26的p+/N+层与沟槽式电容器28之间的结经偏压而使N+掺杂传导区域48从四个侧耗尽。电流流动因此被阻断，如由虚线矩形60所示。由于四侧耗尽，因此与两侧耗尽区域相比，N+层48层的掺杂可显著较高(高达2的倍数)，或N+层48的大小可以是显著增加的，或者增加N+层48的掺杂及大小的组合，而当RESURF晶体管10关断时，仍使N+层48耗尽。N+区域的较高掺杂及/或增加的表面积显著减低装置的导通状态电阻。
图4D是沿图1的线4D-4D截取的横截面示意图。P+区域32形成P+层32到RESURF晶体管10顶部的连接，在本发明的一个实施例中，其通过金属化(未显示)与沟槽式电容器22的P+多晶硅42接合在一起。P+层32与沟槽式电容器28中的P+多晶硅42的共用连接34在RESURF晶体管10关断时提供耗尽区域中的均匀性。
图5A-5C是图解说明制作图1的本发明中的选择细节的横截面示意图，以显示在制作p+/N+堆叠26的P+/N+层中的选择细节。图5A-5C显示用以形成p+/N+堆叠26的多区域区的连续P+及N+植入70、72、74、76及78。所属领域的技术人员将了解P+/N+层还可通过扩散或以外延层来形成。
图6A-6D是图解说明制作图1的本发明中的其它选择细节的横截面示意图，以显示形成沟槽式电容器28中的选择细节。图6A显示半导体衬底12的上表面上的掩模80。一个或一个以上沟槽82蚀刻于P+/N+堆叠26以用于形成沟槽式电容器28。图6B显示二氧化硅40沉积或生长于沟槽82的侧壁及底部上。图6C显示P+/N+多晶硅84沉积于沟槽82中以形成沟槽式电容器28。接着移除掩模80及P+/N+多晶硅在衬底12上方的部分。
图6D显示在一个实施例中另一掩模88形成于衬底12的顶部上且通过离子植入形成P+区域46。在形成区域32之后，移除掩模88。
沟槽式电容器28是以与沟槽栅极相同方式制作的，且因此不需要任何额外的掩模。在沟槽式电容器28的适当位置中使用p+柱将需要沟槽式电容器28不需要的额外处理。
图7A是图1中所示RESURF晶体管10中的两者连同单个P-衬底102(显示于图7B中)上的额外装置100以及环绕三个装置中的每一者的N-外延层104及隔离区域106的平面示意图。
图7B是沿图7A中的线7B-7B截取的正视横截面示意图。如在图7A中可见到，沟槽式电容器28与隔离区域106一样向下延伸到P-衬底102中，以借此隔离图7A中所示的三个装置。
额外装置100可以是用于同步降压转换器的控制器，例如，所述控制器借助通过线接合互连的三个装置控制两个RESURF晶体管10。
图8是图1中所示的RESURF晶体管10连同CMOS集成电路中使用的P-阱112中的互补RESURF晶体管110的正视横截面示意图。互补RESURF晶体管110中的主要掺杂类型与RESURF晶体管10中的掺杂类型相反。因此，对应电容器112填充有N+多晶硅114，且P+/N+堆叠116中的每一者具有N+顶部中间及底部层118，以及位于N+层118之间的P+层120。
虽然已显示及描述了本发明的特定实施例，但将理解可在本发明的精神及范围内实现若干变化及修改。因此，可使用所属领域的技术人员众所周知的其它材料来形成沟槽式电容器且可使用其它工艺来形成p/n堆叠及沟槽式电容器。另外，所述装置可具有多于或少于所示数目的沟槽式电容器，及具有多于或少于所述堆叠中的所述第一及第二导电率类型的所述数目的交替区域。

Claims (10)

1、一种半导体装置，其包含：
半导体衬底；
提供于所述衬底中的源极区域及漏极区域；其中所述源极区域与所述漏极区域彼此横向间隔开；
位于所述衬底中所述源极区域与所述漏极区域之间的漂移区域；
其中所述漂移区域包括具有延伸于所述源极区域与所述漏极区域之间的至少两个间隔沟槽式电容器的结构；且进一步包括具有至少第一导电率类型的第一区域、第二导电率类型的第二区域及所述第一导电率类型的第三区域的堆叠，其中所述堆叠在所述源极区域与所述漏极区域之间且在所述至少第一与第二沟槽式电容器之间延伸并电连接到所述第一及第二沟槽式电容器；
其中，当所述装置处于导通状态时，电流穿过所述第二导电率类型的所述第二区域在所述源极与漏极区域之间流动；且当所述装置处于关断/阻断状态时，所述第二导电率区域由来自所述堆叠的所述第一及第三区域以及来自所述第一及第二沟槽式电容器的四个单独电场耗尽。
2、如权利要求1所述的装置，其中所述第一导电率类型的所述第一及第三区域是p区域且其中所述第二导电率类型的所述第二区域是n区域。
3、如权利要求1所述的装置，其中所述第一导电率类型的所述第一及第三区域是n区域且所述第二导电率类型的所述第二区域是p型。
4、如权利要求1所述的装置，其中所述沟槽式电容器包括二氧化硅壁及填充所述沟槽式电容器的其余部分的掺杂多晶硅。
5、如权利要求1所述的装置，其中所述装置是RESURF晶体管。
6、如权利要求1所述的装置，其中所述堆叠的所述第二导电率类型的所述区域被掺杂得明显高于未采用所述间隔沟槽式电容器的RESURF晶体管中的可比区域。
7、如权利要求1所述的装置，其中所述半导体衬底具有多个间隔沟槽式电容器及交错于所述多个间隔沟槽式电容器之间的第一及第二导电率类型的多个堆叠。
8、一种制造半导体装置的方法，其包含：
提供具有彼此横向间隔开的源极及漏极的半导体衬底，其中在所述源极与漏极区域之间具有漂移区域；
在所述漂移区域中形成一区，所述区包括至少第一导电率类型的第一区域、位于所述第一区域顶部上的第二导电率类型的第二区域及位于所述第二区域顶部上的所述第一导电率类型的第三区域；及
在所述区中产生延伸于所述源极与所述漏极之间的至少两个间隔沟槽式电容器，其中在所述沟槽式电容器之间形成与所述沟槽式电容器电连接的所述第一、第二及第三区域的堆叠。
9、如权利要求8所述的方法，其中所述形成步骤包括对所述第一、第二及第三区域进行植入。
10、如权利要求8所述的方法，其中所述产生步骤包括在所述衬底区中蚀刻延伸于所述源极与所述漏极之间的若干平行间隔沟槽、氧化所述经蚀刻沟槽的侧壁以在所述侧壁上形成二氧化硅层、及用掺杂多晶硅填充所述沟槽的剩余部分。
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