CN103413822B - 降低浮空埋层半导体器件漏电流的方法 - Google Patents

降低浮空埋层半导体器件漏电流的方法 Download PDF

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CN103413822B
CN103413822B CN201310370379.0A CN201310370379A CN103413822B CN 103413822 B CN103413822 B CN 103413822B CN 201310370379 A CN201310370379 A CN 201310370379A CN 103413822 B CN103413822 B CN 103413822B
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CN103413822A (zh
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谭开洲
唐昭焕
刘嵘侃
刘勇
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CETC 24 Research Institute
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Abstract

本发明涉及一种降低浮空埋层半导体器件漏电流的方法。包括半导体衬底材料、第一外延层、分裂浮空埋层、第二外延层、侧壁掺杂深槽、被保护器件、表面结终端和划片道。其中，被保护器件、表面结终端处于第二外延层中，分裂浮空埋层位于第二外延层和第一外延层之间，侧壁掺杂深槽穿透第二外延层与分裂浮空埋层相连接；半导体衬底材料、第一外延层和第二外延层导电类型相同，分裂浮空埋层、侧壁掺杂深槽与半导体材料导电杂质类型相反。这种结构可以在保持双外延层的分裂浮空埋层半导体器件高耐压低导通电阻的同时，避免了常规浮空埋层器件划片道边缘漏电的缺点。

Description

降低浮空埋层半导体器件漏电流的方法
技术领域
本发明属于半导体器件和集成电路技术领域，特别涉及一种降低浮空埋层半导体器件漏电流的方法。
背景技术
目前半导体器件，尤其是高压半导体硅器件，其击穿电压和导通电阻的优化设计是互相影响和相互矛盾的，获得高击穿电压一般就很难获得低的导通电阻。业界针对传统的器件结构已经提出了一些在保持击穿电压不变来降低导通电阻的方法，最著名的是具有超结（SuperJunction，简称SJ）结构的器件，但这种器件要求其互补的N型和P型耐压漂移区耗尽后空间电荷匹配非常严格，5%的失配就可以导致很大的耐压下降，其次是降低表面电场（RESURF）技术的在半导体器件体内巧妙应用，如双层和三层RESURF的LDMOS，槽栅肖特基，槽栅VDMOS和槽栅IGBT等，还有一类较少讨论的是利用分裂浮空埋层（splitburriedfloatinglayer，简称SBFL）来实现的，如SaitohW等人的“Ultralowon-resistanceSBDwithp-buriedfloatinglayer”,PowerSemiconductorDevicesandICs,Proceedingsofthe14thInternationalSymposiumon4-7,pp.33–36,June2002；JohjiNishio等人的"Ultralow-LossSiCFloatingJunctionSchottkyBarrierDiodes(Super-SBDs)",IEEETRANSACTIONSONELECTRONDEVICES,Vol.55(8),pp.1954-1960,AUGUST2008；南雅公等人的“4H-SiC双层浮结肖特基势垒二极管温度特性研究”,微电子学,Vol.41(1),pp.146-149,Feb2011.和“Studyandoptimalsimulationof4H-SiCfloatingjunctionSchottkybarrierdiodes'structuresandelectricproperties”,Chin.Phys.B,Vol.19(10),pp.107304-1,2010.。
从效果来看，槽栅结构和三层以下的RESURF理论上不如SJ结构，而多层的分裂浮空埋层SBFL结构与SJ结构在极限情况下理论上是基本上是等价的。现实情况下，SJ结构的研究热度和应用超过SBFL结构，SBFL结构目前主要还是在SiC材料中应用较多。
SBFL结构相对于SJ结构在浮空埋层的杂质浓度范围要求没SJ结构电荷平衡那么高，这是SBFL结构的最大优点，并且在外延层数较少时工艺实现难度相对较小。
而已有的SBFL结构浮空埋层与芯片的划片道是相连接的，这将导致SBFL结构器件在耐受反向高压时，浮空埋层空间耗尽层必然会与具有高缺陷密度的划片道交叠而导致SBFL结构器件反向漏电增加，本发明的目的就是提出了一种解决这种问题方法。
发明内容
本发明解决上述SBFL结构器件在反向高压时存在较大漏电问题的技术方案在于，一种降低浮空埋层半导体器件漏电流的方法，包括：
半导体材料1，第一外延层2，分裂浮空埋层3，第二外延层4，侧壁掺杂深槽5，被保护器件6，表面结终端7，划片道8。
半导体材料1、第一外延层2、第二外延层4都是相同导电杂质类型，分裂浮空埋层3、侧壁掺杂深槽5与半导体材料1是相反导电杂质类型。
被保护器件6和表面结终端7都处于第二外延层4中，分裂浮空埋层3位于第二外延层4和第一外延层2之间，侧壁掺杂深槽5穿透第二外延层4与分裂浮空埋层3相连接。
分裂浮空埋层3自身间距W1不大于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的8%，侧壁掺杂深槽5与表面结终端7间距W3不小于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的25%，分裂浮空埋层3到侧壁掺杂深槽5左侧距离W2不小于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的25%，分裂浮空埋层3到侧壁掺杂深槽5右侧距离W4不小于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的30%。
分裂浮空埋层3到划片道8距离不小于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的20%。
第一外延层2和第二外延层4杂质浓度相等，第一外延层2和第二外延层4杂质浓度为所设计电压在理想平行平面突变结低掺杂区杂质浓度的1.7倍到2.2倍之间。
第一外延层2厚度为所设计电压在理想平行平面突变结情况下最大耗尽层厚度的35%～50%，第二外延层4厚度为所设计电压在理想平行平面突变结情况下最大耗尽层厚度的45%～55%。
有益效果：
由于本发明的一种降低浮空埋层半导体器件漏电流的方法采用了上述技术方案，具有以下优点：
1）在保持SBFL结构器件低导通电阻和高耐压情况下，避免了普通SBFL结构因空间耗尽层与划片道附近半导体材料缺陷交叠而导致的反向漏电流；
2）本方法对SBFL结构所做改动很小，仅增加一次掺杂深槽和一次分裂浮空埋层3版图修改，增加成本较小；
3）本方法避免普通SBFL结构因空间耗尽层与划片道附近半导体材料缺陷相互作用导致的长期可靠性问题，器件稳定性和可靠性得到提高。
附图说明
图1是本发明降低浮空埋层半导体器件漏电流的方法结构示意图。
图2是本发明实施例的硅片第一次外延及形成后分裂浮空埋层3的示意图。
图3是在本发明图2的硅片上进行了第二次外延和侧壁掺杂深槽5刻蚀及其扩散掺杂后的示意图。
图4是在本发明图3的硅片上进行了被保护器件6、表面结终端7掺杂以及表面氧化层9和金属层10形成后的示意图。
具体实施方式
以被保护器件6为一个最简单的600V耐压的二极管结构为例来说明本方法的实施，二极管以外的其它器件具备本方法描述特征的实施例不应被视为不同的方法。图1中“被保护器件”还可以是双极三极管、MOSFET、VDMOS、IGBT等能够利用此结构作为结终端保护的半导体器件或者集成电路。
一般被保护器件的结构是对称的，而图1以“被保护器件”右侧结终端剖面对称结构为例来说明本方法的内容，同样剖面结构作一个镜象轴对称可以放在“被保护器件”左侧构成完整的终端结构。故以对称右侧描述方法为例的内容是完整和清晰的。
下面以结构最简单的硅二极管为例来具体说明。
1、在0.02～0.001Ω.cmN型<100>硅材料上采用行业通行方法形成光刻对位标识；
2、根据二极管600V耐压要求，采用行业通行方法在所述硅材料生长N型第一外延层2，其浓度取为600V理想平行平面突变结低掺杂区杂质浓度的1.89倍，即掺杂浓度为5.8×1014/cm3，处于理想平行平面突变结低掺杂区杂质浓度的1.7倍到2.2倍之间，其厚度取为理想平行平面突变结最大耗尽层厚度的47%，即25μm，处于理想平行平面突变结最大耗尽层厚度的35%～50%范围内，如图1和图2所示；
3、使用行业通用干氧化形成40nm氧化层，再采用通用光刻方法套刻出分裂浮空层3，根据分裂浮空埋层3自身间距（W1）不大于所设计电压在理想平行平面突变结最大耗尽层厚度的8%，分裂浮空埋层3间距取为4μm，是最大耗尽层厚度的7.5%，浮空埋层与划片道8的距离为15μm，是理想平行平面突变结最大耗尽层厚度的28%，如图1和图2所示；
4、在第3步基础上进行通用的硼离子注入方法，注入能量为80KeV，注入剂量为1.0×1013/cm2；
5、在第4步注入去胶后进行注入杂质退火激活，采用行业通用的N2气保护退火，温度950摄氏度，时间20分钟，如图1和图2所示；
6、在第5步工艺基础上漂光氧化层，生长N型第二外延层4，厚度27μm，是最大耗尽层厚度的51%，浓度仍为5.8×1014/cm3；
7、在第6步工艺基础上，使用行业通用的水汽热氧化600nm，采用通用深槽刻蚀方法，刻蚀出31μm深槽5，深槽穿透浮空埋层3，槽宽1.5μm，深槽5左侧距离浮空层3（W2）62μm，右侧距离浮空层3（W4）21μm，如图1和图3所示；
8、在第7步工艺基础上，使用行业通用的100:1HF溶液浸泡30秒钟去除刻蚀产生的聚合物，再采用标准半导体清洗程序1号液（氨水：双氧水：去离子水=1：2：7）、2号液（盐酸：双氧水：去离子水=1：2：7）将所述硅片清洗干净，再用行业通用的100:1HF溶液浸泡15秒钟去掉侧壁氧化层，保留硅表面氧化层，进行行业通用的硼扩散，扩散杂质总量按方块电阻计小于100Ω每方块；
9、在第8步工艺基础上，进行行业通用的干热氧化100nm，对已经掺杂的深槽5进行氧化层侧壁保护，然后进行行业通用的LPCVD多晶硅填充深槽，多晶厚度以填满深槽为限，对于1.5μm宽度的深槽5，多晶厚度一般为1μm，然后再用行业通用的CMP方法抛光去除表面多晶硅，再用行业通用的方法去除表面残留的氧化层，如图1和图3所示；
10、在第9步工艺基础上，用行业通用的方法进行硅表面干热生长70nm氧化层，用行业通用的光刻方法套刻出3μm宽的二极管P+区6（即被保护器件6），用行业通用的方法进行带胶硼离子注入，能量为60KeV，剂量为2×1015/cm2；
11、对于表面终端区7可以是任何一种成熟的表面结终端耐压结构，本例子使用了满足RESURF条件简单耐压终端结构，具体做法为：在第10步工艺基础上，用行业通用的注入去胶方法去胶后再套刻出表面终端区7，此表面终端区7横向长度为38μm，与二极管区6间距1μm，与掺杂深槽5间距（W3）24μm，再用行业通用的带胶硼离子注入方法，能量为80KeV，剂量为1.8×1012/cm2，注入去胶清洗后用行业通用的方法进行950摄氏度，20分钟N2气退火，如图4所示；
12、在第11步工艺基础上，用行业通用的LPCVD方法淀积600nm的二氧化硅，再用行业通用的光刻方法刻蚀出二极管P+接触孔，再用行业通用的溅射方法溅射1.2μm金属层10，光刻金属层10，然后进行行业通用的合金，最终完成器件的制作，如图4所示。
采用这种方法制作的600V二极管的外延比电阻为41.7mΩ.cm2，比理想平行平面突变结二极管的比导通电阻73.3mΩ.cm2减少了43%，与普通SBFL结构相同，但避免了普通SBFL结构划片道漏电和可靠性的缺点。
上述步骤中省略了众所周知的、明显的行业通用清洗等简单过程，这对于本领域的一般技术人员是周知的，这里没有再具体详细进行说明。

Claims (4)

1.一种降低浮空埋层半导体器件漏电流的半导体结构，包括：半导体材料(1)，第一外延层(2)，分裂浮空埋层(3)，第二外延层(4)，侧壁掺杂深槽(5)，被保护器件(6)，表面结终端(7)，划片道(8)；其特征在于：半导体材料(1)、第一外延层(2)、第二外延层(4)都是相同导电杂质类型，分裂浮空埋层(3)、侧壁掺杂深槽(5)与半导体材料(1)是相反导电杂质类型；被保护器件(6)和表面结终端(7)都处于第二外延层(4)中，分裂浮空埋层(3)位于第二外延层(4)和第一外延层(2)之间，侧壁掺杂深槽(5)穿透第二外延层(4)与分裂浮空埋层(3)相连接；分裂浮空埋层(3)自身间距不大于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的8％，侧壁掺杂深槽(5)与表面结终端(7)间距不小于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的25％，分裂浮空埋层(3)到侧壁掺杂深槽(5)左侧距离不小于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的25％，分裂浮空埋层(3)到侧壁掺杂深槽(5)右侧距离不小于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的30％；第一外延层位于半导体材料上，第二外延层位于第一外延层上。
2.如权利要求1所述的一种降低浮空埋层半导体器件漏电流的半导体结构，其特征在于：分裂浮空埋层(3)到划片道(8)距离不小于所设计电压在理想平行平面突变结情况下最大耗尽层厚度的20％。
3.如权利要求1所述的一种降低浮空埋层半导体器件漏电流的半导体结构，其特征在于：第一外延层(2)和第二外延层(4)杂质浓度相等，第一外延层(2)和第二外延层(4)杂质浓度为所设计电压在理想平行平面突变结低掺杂区杂质浓度的1.7倍到2.2倍之间。
4.如权利要求1所述的一种降低浮空埋层半导体器件漏电流的半导体结构，其特征在于：第一外延层(2)厚度为所设计电压在理想平行平面突变结情况下最大耗尽层厚度的35％～50％，第二外延层(4)厚度为所设计电压在理想平行平面突变结情况下最大耗尽层厚度的45％～55％。
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