JP4189415B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4189415B2 JP4189415B2 JP2006182703A JP2006182703A JP4189415B2 JP 4189415 B2 JP4189415 B2 JP 4189415B2 JP 2006182703 A JP2006182703 A JP 2006182703A JP 2006182703 A JP2006182703 A JP 2006182703A JP 4189415 B2 JP4189415 B2 JP 4189415B2
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Description
図1は本発明の第1の実施形態にかかる半導体装置(縦型ショットキーバリアダイオード)の1素子分の縦断面図である。図1のA−A線に沿った摸式的な横断面図を図2に示すが、本実施形態の1素子の構成要素は5を除き平面的には同心円状に形成されている。通常の半導体装置では、このような半導体素子が複数個並列に形成され、1チップを構成している。なお、図2において、7を角部に電界集中緩和用の丸み(R)を付けた方形のリングとする等の変形も可能である。
第1の実施の形態はn型SiC層2に埋め込みp型領域5,7が各1層設けられたものであったが、複数段のp型埋め込み領域を設けてもよい。図17は、第2の実施形態に係る半導体装置の断面図で、第1の実施形態と同一箇所には同一番号を付して、重複する説明を省略する。
図18は、本発明の第3の実施形態の半導体装置の断面図で、本発明をpnダイオードに適用した実施形態である。参照番号13がp型アノード領域で、111 がNiアノード電極、112 がTi/Alのパッド電極(フィールドプレート)である。その他第1の実施形態と同一箇所には同一番号を付して、重複する説明を省略する。
図19は、本発明の第4の実施形態に係る半導体装置の断面図で、本発明を縦型MOSFETに適用した実施形態である。参照番号14がp型領域、15がn型ソース領域、16が(ゲート)絶縁膜、17がゲート電極、18がソース電極(第1の電極)となる。その他第1の実施形態と同一箇所には同一番号を付して、重複する説明を省略するが、参照番号4がドレイン電極(第2の電極)となる。なお、p型SiC半導体基板1上にn型SiC半導体層2を設けるようにすれば、IGBTを構成することができる。
2…半導体層
3…第1の電極(ショットキーメタル)
4…第2の電極
5…p型埋込み領域(第3の半導体領域)
7…p型埋込み領域(第2の半導体領域)
8…リサーフ層(第1の半導体領域)
9…ガードリング
10…チャネルストッパ(第4の半導体領域)
11…パッド電極(フィールドプレート)
12…フィールドプレート絶縁膜
13…アノード層
14…p型領域
15…n型ソース領域
16…(ゲート)絶縁膜
17…ゲート電極
18…ソース電極
Claims (21)
- 第1導電型のSiCからなる半導体基板と、
前記半導体基板上に形成され、活性領域とそれを取り囲む素子終端領域を有する第1導電型のSiCからなる半導体層と、
前記半導体層の前記活性領域の表面に選択的に形成された第1の電極と、
前記半導体基板の裏面に形成された第2の電極と、
前記半導体層の表面で、前記活性領域端部から前記素子終端領域にかけて形成された第2導電型の第1の半導体領域と、
前記半導体層の表面に略平行に、前記素子終端領域に帯状に埋め込まれた第2導電型の第2の半導体領域と、
を具備し、
前記第2の半導体領域は、複数の開口部を有するメッシュ状領域であり、前記活性領域の端部から50μm以内を始点とし、前記素子終端領域の周縁端部から50μm以内を終点として形成されていることを特徴とする半導体装置。 - 前記第1の半導体領域の不純物濃度は、前記第2の半導体領域の不純物濃度と実質的に略等しく、前記第1の半導体領域はリサーフ層として機能する請求項1に記載の半導体装置。
- 前記半導体層の前記活性領域内において、前記第2半導体領域と実質的に同じ深さに第2導電型の第3の半導体領域を更に具備することを特徴とする請求項1乃至2のいずれかに記載の半導体装置。
- 前記第3の半導体領域は、複数の開口部を有することを特徴とする請求項3に記載の半導体装置。
- 前記第1の電極と前記第2の電極との間に逆方向電圧印加時に、前記半導体層の上部に形成される等電位面が前記第2半導体領域の表面に沿う方向に向かって曲げられ相互に収斂するごとく曲げられることを特徴とする請求項1乃至4のいずれかに記載の半導体装置。
- 前記半導体層の前記素子終端領域の表面に、前記第1の半導体領域の周囲を離間して囲むように形成された第2導電型のガードリングをさらに具備することを特徴とする請求項1乃至5のいずれかに記載の半導体装置。
- 前記半導体層の前記素子終端領域の周縁部表面に、前記第1の半導体領域の周囲を離間して囲むように形成され、前記半導体層よりも不純物濃度が高い第1導電型の第4の半導体領域をさらに具備することを特徴とする請求項1乃至6のいずれかに記載の半導体装置。
- 前記第2の半導体領域の不純物濃度が1×1017〜5×1018/cm3であることを特徴とする請求項1乃至7のいずれかに記載の半導体装置。
- 前記第3の半導体領域の不純物濃度が1×1017〜5×1018/cm3であることを特徴とする請求項3または4に記載の半導体装置。
- 第1導電型のSiCからなる半導体基板と、
前記半導体基板上に形成され、活性領域とそれを取り囲む素子終端領域を有する第1導電型のSiCからなる半導体層と、
前記半導体層の前記活性領域の表面に選択的に形成された第1の電極と、
前記第1の電極を取り囲むように、前記第1の半導体層の表面を覆う絶縁膜と、
前記半導体基板の裏面に形成された第2の電極と、
前記半導体層の表面で、前記活性領域端部から前記素子終端領域にかけて形成された第2導電型のリサーフ層と、
前記半導体層の表面で、前記リサーフ層の周囲を離間して囲むように形成された第2導電型のガードリングと、
前記半導体層の表面に略平行に、前記素子終端領域に複数の開口部を有する帯状に埋め込まれており、前記活性領域の端部から50μm以内を始点とし、前記素子終端領域の周縁端部から50μm以内を終点として形成されている第2導電型の第1の埋め込み半導体領域と、
を具備することを特徴とする半導体装置。 - 前記半導体層の前記活性領域中において、前記リサーフ層より内側の領域内で、前記第1の埋め込み半導体領域と実質的に同じ深さに埋め込まれた第2導電型の第2の埋め込み半導体領域を更に具備することを特徴とする請求項10に記載の半導体装置。
- 前記第1の電極と前記第2の電極の間に逆方向電圧印加時に、前記半導体層の上部に形成される等電位面が前記第1の埋め込み半導体領域の表面に沿う方向に向かって曲げられ相互に収斂するごとく曲げられることを特徴とする請求項10または11に記載の半導体装置。
- 前記半導体層の前記素子終端領域の周縁端部に、前記ガードリングの周囲を囲むように形成され、前記第1の半導体層よりも不純物濃度が高い第1導電型のチャネルストッパ領域をさらに具備することを特徴とする請求項10乃至12のいずれかに記載の半導体装置。
- 前記第1の埋め込み領域の不純物濃度が1×1017〜5×1018/cm3であることを特徴とする請求項10乃至13のいずれかに記載の半導体装置。
- 前記第2の埋め込み領域の不純物濃度が1×1017〜5×1018/cm3であることを特徴とする請求項11に記載の半導体装置。
- 前記第2の埋め込み領域は、複数のリング状領域を、複数の放射状領域で連結したものであることを特徴とする請求項1〜15のいずれかに記載の半導体装置。
- 前記複数のリング状領域のうち、最内側のリングを最外側のリングに対して幅広としたことを特徴とする請求項16に記載の半導体装置。
- 前記複数のリング状領域のうち、最外側のリングを最内側のリングに対して幅広としたことを特徴とする請求項16に記載の半導体装置。
- 前記第2の埋め込み領域は、複数のドット状の開口部を有することを特徴とする請求項1〜15のいずれかに記載の半導体装置。
- 前記第2の埋め込み領域は、最内側に幅広のリングをさらに具備したことを特徴とする請求項19に記載の半導体装置。
- 前記第2の埋め込み領域は、最外側に幅広のリングをさらに具備したことを特徴とする請求項19に記載の半導体装置。
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