CN111354777A - 一种低导通电阻的异质结半导体器件 - Google Patents

一种低导通电阻的异质结半导体器件 Download PDF

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CN111354777A
CN111354777A CN201811585004.5A CN201811585004A CN111354777A CN 111354777 A CN111354777 A CN 111354777A CN 201811585004 A CN201811585004 A CN 201811585004A CN 111354777 A CN111354777 A CN 111354777A
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layer
current blocking
semiconductor device
annular
metal
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刘斯扬
张弛
肖魁
孙贵鹏
王德进
魏家行
卢丽
孙伟锋
陆生礼
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Southeast University
CSMC Technologies Fab2 Co Ltd
CSMC Technologies Corp
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CSMC Technologies Fab2 Co Ltd
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Priority to JP2021536808A priority patent/JP7273971B2/ja
Priority to US17/417,663 priority patent/US20220069115A1/en
Priority to PCT/CN2019/126517 priority patent/WO2020135207A1/zh
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Abstract

本发明涉及一种低导通电阻的异质结半导体器件，包括：金属漏电极，衬底，缓冲层，缓冲层内设有电流阻挡层，在缓冲层上设有栅极结构，所述栅极结构包括金属栅电极，GaN柱，AlGaN层，所述金属栅电极上方设有金属源电极，所述电流阻挡层包括多级电流阻挡层且各层的对称中心共线，各级电流阻挡层环形内口自上而下逐级减小，有效限制了峰值电场并使其远离沟道，保证了器件耐压能力，同时减少了电流损失，AlGaN层和GaN柱在缓冲层上方呈蜂窝状分布，产生多段沟道电流，有效提高了电流能力，使得器件在导通时获得更高的开态电流，从而降低了器件的导通电阻。

Description

一种低导通电阻的异质结半导体器件
技术领域
本发明主要涉及高压功率半导体器件领域，具体来说，是一种低导通电阻的异质结半导体器件。
背景技术
氮化镓(GaN)作为第三代宽禁带半导体代表具有良好电学特性，包括较高的反向耐压能力、较高的二维电子气浓度、较高的高温工作能力、较低的正向导通电阻、较高的开关频率以及较高的功率密度等优点。异质结半导体是基于两种禁带宽度不同的半导体材料接触形成异质结，电子会从宽禁带的半导体流向窄禁带的半导体中，从而在半导体截面的窄禁带半导体一侧形成量子阱，由于其中电子受到宽禁带半导体中杂质库仑散射的影响较小，所以具有较高的电子迁移率。基于AlGaN/GaN异质结半导体在半导体领域已经取得了广泛的应用。
垂直异质结半导体器件相比于横向异质结半导体器件的优点在于垂直异质结半导体器件可以通过缓冲层来承受耐压，但是横向异质结半导体器件主要是依靠金属栅电极与金属漏电极之间的有源区来承受耐压，在相同耐压能力下，垂直异质结半导体器件比横向异质结半导体器件所占用的横向面积小，这加快推进了异质结半导体器件在小型化和集成化方向上的发展。但是垂直异质结半导体器件无法同横向异质结半导体器件一样直接通过高迁移率的二维电子气直接实现源极漏极之间的电流导通，电流必须流经缓冲层，这就大大增加了器件的导通电阻，但是提高缓冲层的浓度又会带来器件承受耐压能力下降的问题，所以垂直异质结半导体器件的主要问题在于存在较大的导通电阻。
因此解决垂直异质结半导体器件的导通电阻问题是一个十分关键问题，常规的垂直GaN异质结半导体器件如图1所示，其器件结构主要包括金属漏电极1、衬底2、GaN缓冲层3、GaN柱5、AlGaN层6、电流阻挡层4、金属源电极8、金属栅电极10以及钝化层11，器件导通情况下，电流必须流经缓冲层3。常规的垂直异质结半导体器件存在明显的耐压与导通电阻的矛盾。
发明内容
本发明就是针对上述问题，提出一种低导通电阻的异质结半导体器件，有效提高了器件正向导通能力，减少了器件的导通电阻，同时可以维持较高的器件反向耐压值。
本发明采用如下技术方案：
一种低导通电阻的异质结半导体器件，包括：金属漏电极，在金属漏电极上设有衬底，在衬底上设有缓冲层，在缓冲层内设有电流阻挡层，在电流阻挡层上设有栅极结构，所述栅极结构包括金属栅电极，所述金属栅电极上方设有金属源电极，在金属栅电极与金属源电极之间设有第一钝化层，在金属栅电极和所述缓冲层之间设有第二钝化层，其特征在于，所述电流阻挡层包括由上向下顺序排列的第一级环形电流阻挡层、第二级环形电流阻挡层和第三级环形电流阻挡层且各层的对称中心共线，第一级环形电流阻挡层的环形内口大于第二级环形电流阻挡层的环形内口，第二级环形电流阻挡层的环形内口大于第三级环形电流阻挡层的环形内口，呈现逐级缩小的趋势。
优选的，所述栅极结构包括立于缓冲层上表面上的GaN柱，在GaN柱侧表面包裹有AlGaN层，并由相接触的GaN柱和AlGaN层的界面处形成垂直沟道，所述金属栅电极位于AlGaN层(的外侧，所述金属源电极位于GaN柱和AlGaN层的上表面上，金属源电极与AlGaN层之间形成肖特基接触。
优选的，所述电流阻挡层还包括第四级环形电流阻挡层且第四级环形电流阻挡层对称中心与第三级环形电流阻挡层的对称中心共线，所述第四级环形电流阻挡层的环形内口小于所述第三级环形电流阻挡层的环形内口。
优选的，所述AlGaN层的横截面呈正六边形，在缓冲层上表面上至少设有4个内有N型掺杂的GaN柱的AlGaN层且呈蜂窝状分布排列。
优选的，所述金属栅电极层下表面与所述缓冲层上表面垂直距离为0.25-0.4μm，所述金属栅电层厚度为0.2μm。
与现有技术相比，本发明具有如下优点：
(1)本发明采用GaN柱和AlGaN层相接触形成二维电子气，极大减少了器件所需要的横向占用面积，同时GaN柱的侧壁与AlGaN层均存在接触面，GaN柱在水平剖面上呈圆形，所以在GaN柱的侧壁都存在电流导通路径，增加了沟道密度且有效提高了电流能力，使得器件在导通时获得更高的开态电流，从而降低了器件的导通电阻。
(2)本发明的GaN柱及AlGaN层在缓冲层上表面呈蜂窝状分布，符合了工艺要求中通孔最小尺寸要求，可以最大程度利用器件的横向面积。在缓冲层上存在多个分立GaN柱，产生多段沟道电流，有效提高了电流能力，使得器件在导通时获得更高的开态电流，从而降低了器件的导通电阻。
(3)本发明采用的电流阻挡层分多级电流阻挡层，其中每一级电流阻挡层在各级所在水平面呈“口”字形分布且环形内口逐级减小，同时各级电流阻挡层在缓冲层中相互平行且呈阶梯状分布。阶梯状的电流阻挡层可以有效改善电场分布使得电场峰值远离沟道，提高平均电场，保证了器件耐压能力；靠近GaN柱的电流阻挡层的环形内口较大，通过沟道进入缓冲层的电流较大，随着电流阻挡层级数增加，环形内口减小，耗尽层限制电流流通路径，只能从最小通道口流通。如图8所示，比较了两种“口”字分布的电流阻挡层的电场分布图(环形内口逐级减小型和环形内口逐级增大型)，环形内口逐级减小的阶梯状的电流阻挡层很好的限制了峰值电场远离GaN柱一侧，在提高器件的耐压能力的同时尽可能的减少对器件正向导通电流能力的牺牲；此外，常规电流阻挡层的工艺方法式为Mg离子注入，Mg离子注入会造成一定的晶格损伤，特别是对电流阻挡层会造成较大的漏电，另一方面Mg具有很强的记忆效应，在二次外延过程中有很大的扩散作用，阶梯状电流阻挡层特别是靠近GaN柱的电流阻挡层所占面积较小，可以减少Mg离子注入对沟道层和势垒层的影响，减少漏电同时缓解一定的电流崩塌效应。
(4)本发明采用垂直GaN柱和AlGaN层相接触形成二维电子气，沟道长度不受器件本身横向面积的影响，克服了短沟道效应，使得器件的特征频率显著提高，充分发挥了GaN材料较高工作频率的优势。
(5)常规异质结半导体结构会在高压下存在明显的电流崩塌现象，本发明的特点在于纵向沟道与衬底不在同一方向，衬底部分的缺陷在高压下对于器件沟道处的影响很小，本发明结构能有效缓解电流崩塌效应。
附图说明
图1是常规垂直异质结半导体器件的正视截面剖视图。
图2是本发明的低导通电阻异质结半导体器件结构立体图。
图3是本发明的低导通电阻异质结半导体器件的简化结构立体图。图中未示出器件的钝化层以及金属源电极部分。
图4是本发明的低导通电阻异质结半导体器件的简化结构正剖立体图。图中未示出器件的钝化层以及金属源电极部分。
图5是本发明的低导通电阻异质结半导体器件的正视剖面图。
图6是本发明的低导通电阻异质结半导体器件的俯视剖面图。图中未示出器件的钝化层及金属源电极部分。
图7是本发明的低导通电阻异质结半导体器件缓冲层中电流阻挡层部分的俯视剖面图。
图8是两种不同阶梯分布状(电流阻挡层自上而下环形内口逐级减小型和环形内口逐级增大型)的电流阻挡层在高漏压下的电场分布图。
图9图示了根据一种实施案例的栅极结构为矩阵式排列的低导通电阻异质结半导体器件的正视剖面图。图中未示出器件的钝化层以及金属源电极部分。
图10图示了根据一种实施案例的包括P型栅的低导通电阻异质结半导体器件的简化结构正剖立体图。图中未示出器件的钝化层以及金属源电极部分。
图11图示了根据一种实施案例的包括P型栅的低导通电阻异质结半导体器件的正视剖面图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
实施例1
参照图4、图5，图4示出了一种低导通电阻的异质结半导体器件的正剖立体示意图，图5示出了一种低导通电阻的异质结半导体器件的正视剖面图，本例器件包括：
一种低导通电阻的异质结半导体器件，包括：金属漏电极1，在金属漏电极1上设有衬底2，在衬底2上设有缓冲层3，在缓冲层3内设有电流阻挡层4，在电流阻挡层4上设有栅极结构，所述栅极结构包括金属栅电极10，在金属栅电极10上方设有金属源电极8，在金属栅电极10与金属源电极8之间设有第一钝化层11a，在金属栅电极10和缓冲层3之间设有第二钝化层11b，所述电流阻挡层4包括由上向下顺序排列的第一级环形电流阻挡层4a、第二级环形电流阻挡层4b和第三级环形电流阻挡层4c且各层的对称中心共线，第一级环形电流阻挡层4a的环形内口大于第二级环形电流阻挡层4b的环形内口，第二级环形电流阻挡层4b的环形内口大于第三级环形电流阻挡层4c的环形内口，呈现逐级缩小的趋势。在本实施例中，
所述栅极结构包括立于缓冲层3上表面上的GaN柱5，在GaN柱5侧表面包裹有AlGaN层6，并由相接触的GaN柱5和AlGaN层6的界面处形成垂直沟道7，所述金属栅电极10位于AlGaN层6的外侧，所述金属源电极8位于GaN柱5和AlGaN层6的上表面上，金属源电极8与AlGaN层6之间形成肖特基接触。
所述电流阻挡层4可以包括3级、4级、5级甚至更多级，本实施例采用3级，具体来说，所述电流阻挡层4还包括第四级环形电流阻挡层且第四级环形电流阻挡层对称中心与第三级环形电流阻挡层4c的对称中心共线，所述第四级环形电流阻挡层的环形内口小于所述第三级环形电流阻挡层4c的环形内口。
所述AlGaN层6在水平剖面形状包括且不仅限于六边形，包括其他任意多边形结构或圆形结构，所述GaN柱5在水平剖面形状包括且不仅限于圆形，包括其它任意多边形结构。本实施例中的AlGaN层6的横截面呈正六边形，在缓冲层3上表面上至少设有4个内有N型掺杂的GaN柱5的AlGaN层6且呈蜂窝状分布排列。
金属栅电极10层下表面与所述缓冲层3上表面垂直距离为0.25-0.4μm，所述金属栅电极10层厚度为0.2μm。
实施例2
参照图9，与实施例1相比，本例的栅极结构为矩阵式排列分布。GaN柱和AlGaN层在缓冲层上方按矩阵式排列分布，GaN柱和AlGaN层的水平剖面图均为矩形。其它结构与实施例1相同。
实施例3
参照图10、图11所示，与实施例1相比，本例的栅极结构P型栅式。金属栅电极10与势垒层之6间存在P型GaN帽层13，其它结构与实施例1相同。P型栅结构实现了常关型沟道。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (5)

1.一种低导通电阻的异质结半导体器件，包括：金属漏电极(1)，在金属漏电极(1)上设有衬底(2)，在衬底(2)上设有缓冲层(3)，在缓冲层(3)内设有电流阻挡层(4)，在缓冲层(3)上设有栅极结构，所述栅极结构包括金属栅电极(10)，所述金属栅电极(10)上方设有金属源电极(8)，在金属栅电极(10)与金属源电极(8)之间设有第一钝化层(11a)，在金属栅电极(10)和所述缓冲层(3)之间设有第二钝化层(11b)，其特征在于，所述电流阻挡层(4)包括由上向下顺序排列的第一级环形电流阻挡层(4a)、第二级环形电流阻挡层(4b)和第三级环形电流阻挡层(4c)且各层的对称中心共线，第一级环形电流阻挡层(4a)的环形内口大于第二级环形电流阻挡层(4b)的环形内口，第二级环形电流阻挡层(4b)的环形内口大于第三级环形电流阻挡层(4c)的环形内口，呈现逐级缩小的趋势。
2.根据权利要求1所述的低导通电阻的异质结半导体器件，其特征在于，所述栅极结构包括立于缓冲层(3)上表面上的GaN柱(5)，在GaN柱(5)侧表面包裹有AlGaN层(6)，并由相接触的GaN柱(5)和AlGaN层(6)的界面处形成垂直沟道(7)，所述金属栅电极(10)位于AlGaN层(6)的外侧，所述金属源电极(8)位于GaN柱(5)和AlGaN层(6)的上表面上，金属源电极(8)与AlGaN层(6)之间形成肖特基接触。
3.根据权利要求1所述的一种低导通电阻的异质结半导体器件，其特征在于，电流阻挡层(4)还包括第四级环形电流阻挡层且第四级环形电流阻挡层对称中心与第三级环形电流阻挡层(4c)的对称中心共线，所述第四级环形电流阻挡层的环形内口小于所述第三级环形电流阻挡层(4c)的环形内口。
4.根据权利要求2所述的一种低导通电阻的异质结半导体器件，其特征在于，AlGaN层(6)的横截面呈正六边形，在缓冲层(3)上表面上至少设有4个内有N型掺杂的GaN柱(5)的AlGaN层(6)且呈蜂窝状分布排列。
5.根据权利要求1所述的一种低导通电阻的异质结半导体器件，其特征在于所述，金属栅电极(10)层下表面与所述缓冲层(3)上表面垂直距离为0.25-0.4μm，所述金属栅电极(10)层厚度为0.2μm。
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