JP7273971B2 - 低いオン抵抗を有するヘテロ接合半導体デバイス - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 62
- 230000000903 blocking effect Effects 0.000 claims description 121
- 229910052751 metal Inorganic materials 0.000 claims description 59
- 239000002184 metal Substances 0.000 claims description 59
- 229910002704 AlGaN Inorganic materials 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 7
- 229910001425 magnesium ion Inorganic materials 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 4
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 238000004804 winding Methods 0.000 claims 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 29
- 229910002601 GaN Inorganic materials 0.000 description 28
- 230000005684 electric field Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 238000009826 distribution Methods 0.000 description 6
- 238000007142 ring opening reaction Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000005533 two-dimensional electron gas Effects 0.000 description 4
- 230000036961 partial effect Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003446 memory effect Effects 0.000 description 2
- 230000037230 mobility Effects 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Description
図2~6を参照すると、図4は、低いオン抵抗を有するヘテロ接合半導体デバイスの正面部分斜視図であり、図5は、低いオン抵抗を有するヘテロ接合半導体デバイスの正面断面図である。この実施形態では、低いオン抵抗を有するヘテロ接合半導体デバイスは、金属ドレイン電極1と、金属ドレイン電極1上に配設された基板2と、基板2上に配設された緩衝層3と、緩衝層3内部に配設された電流ブロック層4と、電流ブロック層4上に配設されたゲート構造と、を含み、そして、金属ゲート電極10と、金属ゲート電極10上方に配設された金属ソース電極8と、金属ゲート電極10と金属ソース電極8との間に配設された第1不活性化層11aと、金属ゲート電極10と緩衝層3との間に配設された第2不活性化層11bと、を含む。また、図7を参照すると、電流ブロック層4は、第1段の環状電流ブロック層4aと、第2段の環状電流ブロック層4bと、第3段の環状電流ブロック層4cと、を含み、これらは、最上部から底部まで順に配列されており、層のそれぞれの対称中心は共線的である。第1段の環状電流ブロック層4aの環内開口は、第2段の環状電流ブロック層4bの環内開口よりも大きく、そして、第2段の環状電流ブロック層4bの環内開口は、第3段の環状電流ブロック層4cの環内開口よりも大きく、段毎により小さくなる傾向を示す。
図8を参照して、実施形態1と比較すると、この実施形態のゲート構造がマトリクス状に配列されて分布させられている。GaNピラーとAlGaN層とが緩衝層上方でマトリクス状に配列されて分布させられ、そして、GaNピラーとAlGaN層とは、水平断面が長方形である。別の構造は、実施形態1のものと同じである。
図9及び10を参照して、実施形態1と比較すると、この実施形態のゲート構造は、P型ゲート構造である。P型GaNキャップ層13は、金属ゲート電極10とAlGaN層6との間に存在し、そして、別の構造は、実施形態1のそれらと同じである。P型ゲート構造は、ノーマリーオフチャネルを実現する。
Claims (15)
- 金属ドレイン電極(1)と、前記金属ドレイン電極(1)上に配設された基板(2)と、前記基板(2)上に配設された緩衝層(3)と、前記緩衝層(3)内部に配設された電流ブロック層(4)と、前記緩衝層(3)上に配設され金属ゲート電極(10)を備えるゲート構造と、前記金属ゲート電極(10)上方に配設された金属ソース電極(8)と、前記金属ゲート電極(10)と前記金属ソース電極(8)との間に配設された第1不活性化層(11a)と、前記金属ゲート電極(10)と前記緩衝層(3)との間に配設された第2不活性化層(11b)と、を備え、前記ゲート構造内にヘテロ接合構造が形成されており、前記電流ブロック層(4)は、最上部から底部まで順に配列されている、第1段の環状電流ブロック層(4a)と、第2段の環状電流ブロック層(4b)と、第3段の環状電流ブロック層(4c)と、を備え、前記第1段の環状電流ブロック層(4a)は、全体として形成されると共に環内開口を1だけ有し、前記第2段の環状電流ブロック層(4b)は、全体として形成されると共に環内開口を1つだけ有し、前記第3段の環状電流ブロック層(4c)は、全体として形成されると共に環内開口を1つだけ有し、前記第1段の環状電流ブロック層(4a)、前記第2段の環状電流ブロック層(4b)及び前記第3段の環状電流ブロック層(4c)の対称中心が共線的であり、前記第1段の環状電流ブロック層(4a)の前記環内開口が、前記第2段の環状電流ブロック層(4b)の前記環内開口よりも大きく、前記第2段の環状電流ブロック層(4b)の前記環内開口は、前記第3段の環状電流ブロック層(4c)の前記環内開口よりも大きく、前記環内開口は、段毎により小さくなる傾向を表す、低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記ゲート構造は、前記緩衝層(3)の上面上に立設されているGaNピラー(5)と、前記GaNピラー(5)の側面上に巻かれたAlGaN層(6)と、を備え、垂直チャネル(7)が、互いに接触している前記GaNピラー(5)と前記AlGaN層(6)との間の界面に形成されており、前記金属ゲート電極(10)は、前記AlGaN層(6)の外側に位置し、前記金属ソース電極(8)は、前記GaNピラー(5)及び前記AlGaN層(6)の上面上に位置し、ショットキー接触が、前記金属ソース電極(8)と前記AlGaN層(6)との間に形成されており、前記GaNピラー(5)及び前記AlGaN層(6)は前記ヘテロ接合構造を形成している、前記請求項1に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記電流ブロック層(4)は、前記第3段の環状電流ブロック層(4c)より下方に形成された第4段の環状電流ブロック層を更に備え、前記第4段の環状電流ブロック層の対称中心が、前記第3段の環状電流ブロック層(4c)の前記対称中心と共線的であり、前記第4段の環状電流ブロック層の環内開口が、前記第3段の環状電流ブロック層(4c)の前記環内開口よりも小さい、請求項1に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記AlGaN層(6)の断面が正六角形形状であり、N型ドープGaNピラー(5)をその中に有する少なくとも4つのAlGaN層(6)が、前記緩衝層(3)の前記上面上に配設され、ハニカム形状に分布させられ配列されている、請求項2に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記金属ゲート電極(10)の下面と前記緩衝層(3)の上面との間の垂直距離が、0.25μm~0.4μmであり、前記金属ゲート電極(10)の厚さが、0.2μmである、請求項1に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 金属ドレイン電極(1)と、
前記金属ドレイン電極(1)上に配設された基板(2)と、
前記基板(2)上に配設された緩衝層(3)と、
前記緩衝層(3)内部に配設された電流ブロック層(4)と、
前記緩衝層(3)上に配設されたゲート構造と、
前記緩衝層(3)上に配設された金属ソース電極(8)と、を備え、
ヘテロ接合構造が前記ゲート構造内に形成され、
前記電流ブロック層(4)は、最上部から底部まで順に配列されている、第1段の環状電流ブロック層(4a)と、第2段の環状電流ブロック層(4b)と、第3段の環状電流ブロック層(4c)と、を備え、前記第1段の環状電流ブロック層(4a)は、全体として形成されると共に環内開口を1だけ有し、前記第2段の環状電流ブロック層(4b)は、全体として形成されると共に環内開口を1つだけ有し、前記第3段の環状電流ブロック層(4c)は、全体として形成されると共に環内開口を1つだけ有し、前記第1段の環状電流ブロック層(4a)、前記第2段の環状電流ブロック層(4b)及び前記第3段の環状電流ブロック層(4c)の対称中心が共線的であり、前記第1段の環状電流ブロック層(4a)の前記環内開口が、前記第2段の環状電流ブロック層(4b)の前記環内開口よりも大きく、前記第2段の環状電流ブロック層(4b)の前記環内開口は、前記第3段の環状電流ブロック層(4c)の前記環内開口よりも大きい、低いオン抵抗を有するヘテロ接合半導体デバイス。 - 前記ゲート構造は、
前記緩衝層(3)の上面上に立設されているGaNピラー(5)と、
前記GaNピラー(5)の側面上の、前記GaNピラー(5)を巻いているAlGaN層(6)であって、垂直チャネル(7)が、互いに接触している前記AlGaN層(6)と前記GaNピラー(5)の間の界面に形成されている、AlGaN層(6)と、
前記AlGaN層(6)の外側に配設された金属ゲート電極(10)と、
を更に備え、
前記金属ソース電極(8)は、前記金属ゲート電極(10)上方で、前記GaNピラー(5)及び前記AlGaN層(6)の上面上に位置し、ショットキー接触が、前記金属ソース電極(8)と前記AlGaN層(6)との間に形成されており、前記GaNピラー(5)及び前記AlGaN層(6)は前記ヘテロ接合構造を形成している、請求項6に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。 - 前記金属ゲート電極(10)と前記金属ソース電極(8)との間に配設された第1不活性化層(11a)と、
前記金属ゲート電極(10)と前記緩衝層(3)との間に配設された第2不活性化層(11b)と、
を更に備える、請求項7に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。 - 前記AlGaN層(6)の断面は、正六角形形状であり、GaNピラー(5)をその中に有する少なくとも4つのAlGaN層(6)が、前記緩衝層(3)の上面上に配設され、前記AlGaN層(6)のそれぞれは、ハニカム形状に分布させられ配列されている、請求項7に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記GaNピラー(5)は、N型ドープGaNピラーである、請求項9に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記GaNピラー(5)及び前記AlGaN層(6)は、前記緩衝層(3)上方にマトリクス状に配列されており、前記GaNピラー(5)及び前記AlGaN層(6)は、水平断面が長方形である、請求項7に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記ゲート構造は、前記金属ゲート電極(10)と前記AlGaN層(6)との間に配設されたP型ドープGaNキャップ層(13)を更に備える、請求項7に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記金属ゲート電極(10)の下面と前記緩衝層(3)の上面との間の垂直距離が、0.25μm~0.4μmであり、前記金属ゲート電極(10)の厚さが、0.2μmである、請求項7に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記電流ブロック層(4)は、Mgイオン注入によって形成されている、請求項6に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
- 前記電流ブロック層(4)は、前記第3段の環状電流ブロック層(4c)下方に位置する第4段の環状電流ブロック層を更に備え、前記第4段の環状電流ブロック層の対称中心が、前記第3段の環状電流ブロック層(4c)の前記対称中心と共線的であり、前記第4段の環状電流ブロック層の環内開口が、前記第3段の環状電流ブロック層(4c)の前記環内開口よりも小さい、請求項6に記載の低いオン抵抗を有するヘテロ接合半導体デバイス。
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Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090078971A1 (en) | 2007-09-20 | 2009-03-26 | Infineon Technologies Austria Ag | Semiconductor device with structured current spread region and method |
JP2011135094A (ja) | 2011-02-25 | 2011-07-07 | Sumitomo Electric Ind Ltd | 半導体装置およびその製造方法 |
US20110169012A1 (en) | 2007-10-04 | 2011-07-14 | Hersee Stephen D | NANOWIRE AND LARGER GaN BASED HEMTS |
JP2011142200A (ja) | 2010-01-07 | 2011-07-21 | Toyota Central R&D Labs Inc | 電界効果トランジスタ |
JP2012156250A (ja) | 2011-01-25 | 2012-08-16 | Toyota Motor Corp | p型のIII族窒化物半導体層を含む半導体装置とその製造方法 |
CN103329276A (zh) | 2011-01-25 | 2013-09-25 | 住友电气工业株式会社 | 氮化物半导体元件的制造方法 |
CN104167442A (zh) | 2014-08-29 | 2014-11-26 | 电子科技大学 | 一种具有P型GaN岛的垂直氮化镓基异质结场效应晶体管 |
CN105845724A (zh) | 2016-06-17 | 2016-08-10 | 电子科技大学 | 一种积累型垂直hemt器件 |
WO2016147541A1 (ja) | 2015-03-17 | 2016-09-22 | パナソニック株式会社 | 窒化物半導体装置 |
CN106340535A (zh) | 2016-08-01 | 2017-01-18 | 苏州捷芯威半导体有限公司 | 一种半导体器件及其制造方法 |
CN107146811A (zh) | 2017-03-29 | 2017-09-08 | 西安电子科技大学 | 基于阻挡层调制结构的电流孔径功率晶体管及其制作方法 |
US20180151715A1 (en) | 2016-11-28 | 2018-05-31 | Srabanti Chowdhury | Diamond based current aperture vertical transistor and methods of making and using the same |
CN108649070A (zh) | 2018-05-14 | 2018-10-12 | 电子科技大学 | 一种GaN异质结电导调制场效应管 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6181723B1 (en) * | 1997-05-07 | 2001-01-30 | Sharp Kabushiki Kaisha | Semiconductor light emitting device with both carbon and group II element atoms as p-type dopants and method for producing the same |
US7098093B2 (en) * | 2004-09-13 | 2006-08-29 | Northrop Grumman Corporation | HEMT device and method of making |
JP4189415B2 (ja) * | 2006-06-30 | 2008-12-03 | 株式会社東芝 | 半導体装置 |
JP5208463B2 (ja) * | 2007-08-09 | 2013-06-12 | ローム株式会社 | 窒化物半導体素子および窒化物半導体素子の製造方法 |
JP4737471B2 (ja) * | 2009-10-08 | 2011-08-03 | 住友電気工業株式会社 | 半導体装置およびその製造方法 |
US8809987B2 (en) * | 2010-07-06 | 2014-08-19 | The Hong Kong University Of Science And Technology | Normally-off III-nitride metal-2DEG tunnel junction field-effect transistors |
CN102881716A (zh) * | 2012-09-27 | 2013-01-16 | 电子科技大学 | 一种场致隧穿增强型hemt器件 |
CN102945859A (zh) * | 2012-11-07 | 2013-02-27 | 电子科技大学 | 一种GaN异质结HEMT器件 |
EP2884538A1 (en) * | 2013-12-16 | 2015-06-17 | ABB Technology AB | Power semiconductor device |
CN104992971B (zh) * | 2015-06-29 | 2020-01-24 | 电子科技大学 | 具有复合低k电流阻挡层的垂直氮化镓基异质结场效应管 |
CN105304707A (zh) * | 2015-10-28 | 2016-02-03 | 电子科技大学 | 一种增强型hemt器件 |
CN105762078B (zh) * | 2016-05-06 | 2018-11-16 | 西安电子科技大学 | GaN基纳米沟道高电子迁移率晶体管及制作方法 |
CN107154435B (zh) * | 2017-03-29 | 2019-10-08 | 西安电子科技大学 | 阶梯电流阻挡层垂直型功率器件 |
CN107170820B (zh) * | 2017-03-29 | 2020-04-14 | 西安电子科技大学 | 弧形栅-漏复合场板电流孔径异质结器件 |
JP7157138B2 (ja) * | 2018-03-22 | 2022-10-19 | パナソニックホールディングス株式会社 | 窒化物半導体装置 |
CN108598163A (zh) * | 2018-05-14 | 2018-09-28 | 电子科技大学 | 一种GaN异质结纵向功率器件 |
US10741494B2 (en) * | 2018-11-07 | 2020-08-11 | Semiconductor Components Industries, Llc | Electronic device including a contact structure contacting a layer |
-
2018
- 2018-12-24 CN CN201811585004.5A patent/CN111354777A/zh active Pending
-
2019
- 2019-12-19 JP JP2021536808A patent/JP7273971B2/ja active Active
- 2019-12-19 US US17/417,663 patent/US20220069115A1/en active Pending
- 2019-12-19 EP EP19904187.2A patent/EP3905339A4/en active Pending
- 2019-12-19 WO PCT/CN2019/126517 patent/WO2020135207A1/zh unknown
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090078971A1 (en) | 2007-09-20 | 2009-03-26 | Infineon Technologies Austria Ag | Semiconductor device with structured current spread region and method |
US20120225526A1 (en) | 2007-10-04 | 2012-09-06 | Stc.Unm | NANOWIRE AND LARGER GaN BASED HEMTS |
US20110169012A1 (en) | 2007-10-04 | 2011-07-14 | Hersee Stephen D | NANOWIRE AND LARGER GaN BASED HEMTS |
JP2011142200A (ja) | 2010-01-07 | 2011-07-21 | Toyota Central R&D Labs Inc | 電界効果トランジスタ |
CN103329276A (zh) | 2011-01-25 | 2013-09-25 | 住友电气工业株式会社 | 氮化物半导体元件的制造方法 |
JP2012156250A (ja) | 2011-01-25 | 2012-08-16 | Toyota Motor Corp | p型のIII族窒化物半導体層を含む半導体装置とその製造方法 |
JP2011135094A (ja) | 2011-02-25 | 2011-07-07 | Sumitomo Electric Ind Ltd | 半導体装置およびその製造方法 |
CN104167442A (zh) | 2014-08-29 | 2014-11-26 | 电子科技大学 | 一种具有P型GaN岛的垂直氮化镓基异质结场效应晶体管 |
WO2016147541A1 (ja) | 2015-03-17 | 2016-09-22 | パナソニック株式会社 | 窒化物半導体装置 |
CN105845724A (zh) | 2016-06-17 | 2016-08-10 | 电子科技大学 | 一种积累型垂直hemt器件 |
CN106340535A (zh) | 2016-08-01 | 2017-01-18 | 苏州捷芯威半导体有限公司 | 一种半导体器件及其制造方法 |
US20180151715A1 (en) | 2016-11-28 | 2018-05-31 | Srabanti Chowdhury | Diamond based current aperture vertical transistor and methods of making and using the same |
CN107146811A (zh) | 2017-03-29 | 2017-09-08 | 西安电子科技大学 | 基于阻挡层调制结构的电流孔径功率晶体管及其制作方法 |
CN108649070A (zh) | 2018-05-14 | 2018-10-12 | 电子科技大学 | 一种GaN异质结电导调制场效应管 |
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