CN108172609A - 具有周边深沟槽保护环和接地环的碳化硅悬浮结mosfet器件 - Google Patents

具有周边深沟槽保护环和接地环的碳化硅悬浮结mosfet器件 Download PDF

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CN108172609A
CN108172609A CN201711400459.0A CN201711400459A CN108172609A CN 108172609 A CN108172609 A CN 108172609A CN 201711400459 A CN201711400459 A CN 201711400459A CN 108172609 A CN108172609 A CN 108172609A
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deep trench
silicon carbide
mosfet device
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node mosfet
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袁俊
黄兴
倪炜江
孙安信
耿伟
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Century Goldray Semiconductor Co Ltd
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Abstract

本发明公开了一种具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，该器件的外延层中分布着一层或多层掩埋构造的多个悬浮P+区构成的均匀离散结构，器件的周边JTE或者场限环到划片道之间设置有若干个深沟槽保护结构；深沟槽保护结构垂直穿透均匀离散结构。本申请通过在碳化硅MOSFET器件元胞中结合掩埋悬浮结构和与其相连的周边深沟槽保护结构，能进一步增强悬浮结MOSFET器件的耐压能力和抗干扰能力，减少边缘漏电。该申请的器件结构的周边深沟槽还可以作为seal ring保护芯片内部有源区，使划片的损伤裂纹等终止在沟槽区域，多个深沟槽保护环也可以有助于防止水汽和离子对于芯片有源区域的侵蚀，有利于增长器件的可靠性。

Description

具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件
技术领域
本发明涉及半导体器件技术领域，具体涉及一种具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件。
背景技术
SiC作为近十几年来迅速发展的宽禁带半导体材料，与其它半导体材料，比如Si，GaN及GaAs相比，SiC材料具有宽禁带、高热导率、高载流子饱和迁移率、高功率密度等优点。SiC可以热氧化生成二氧化硅，使得SiC MOSFET及SBD等功率器件和电路的实现成为可能。自20世纪90年代以来，SiC MOSFET和SBD等功率器件已在开关稳压电源、高频加热、汽车电子以及功率放大器等方面取得了广泛的应用。
目前碳化硅MOSFET器件，尤其是高压MOSFET器件，其击穿电压和导通电阻的优化设计是互相影响和相互矛盾的，获得高击穿电压一般就很难获得低的导通电阻。业界针对传统的器件结构已经提出了一些在保持击穿电压不变的情况下来降低导通电阻的方法，其中一种是利用分裂的掩埋悬浮结构来实现的。
掩埋悬浮结构相对于超结结构在浮空埋层的杂质浓度范围要求没超结结构电荷平衡那么高，这是掩埋悬浮结构的最大优点，并且在外延层数较少时工艺实现难度相对较小。但是，为了保证有效的耐压，掩埋悬浮结构需要延伸到结终端区域外围，通过划片道来有效的切断空间电荷的电力线，即掩埋悬浮结构的浮空埋层与芯片的划片道是相连接的。这将导致掩埋悬浮结构器件在耐受反向高压时，浮空埋层空间耗尽层必然会与具有高缺陷密度的划片道交叠而导致器件反向漏电增加，本发明的目的就是提出了一种解决这种问题的方法。
发明内容
针对现有技术中存在的问题，本发明的目的在于提供一种具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，其通过在碳化硅MOSFET器件元胞中结合掩埋悬浮结构和与其相连的周边深沟槽保护结构，能进一步增强悬浮结MOSFET器件的耐压能力和抗干扰能力，减少边缘漏电。
为实现上述目的，本发明采用以下技术方案：
一种具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，所述碳化硅悬浮结MOSFET器件的外延层中分布着一层或多层掩埋构造的多个悬浮P+区构成的均匀离散结构，碳化硅悬浮结MOSFET器件的周边JTE或者场限环到划片道之间设置有若干个深沟槽保护结构；所述深沟槽保护结构垂直穿透所述均匀离散结构；深沟槽保护结构的深沟槽中填充高介电常数介质、多晶硅或金属。
进一步，所述均匀离散结构的顶层与所述碳化硅悬浮结MOSFET器件的P-Well注入区的垂直距离为0.5-10um。
进一步，所述均匀离散结构为P+方块状阵列结构、P+圆柱状阵列结构、P+六边形阵列结构、P+环块状阵列结构、P+三角形框状结构或P+四角形框状结构。
进一步，所述悬浮P+区是碳化硅N型外延片P+注入后二次外延N-epi形成，或者是碳化硅N型外延片直接高能量注入形成的掩埋P+结。
进一步，所述高介电常数介质为SiO2、SiNx、Al2O3、AlN、HfO2、MgO、Sc2O3、Ga2O3、AlHFOx、HFSiON材料中的一种或任意几种的组合。
进一步，所述金属为钨或钛。
本发明具有以下有益技术效果：
本申请的碳化硅悬浮结MOSFET器件的周边JTE或者场限环到划片道之间有多个深沟槽保护结构，沟槽结构垂直穿透整个悬浮P+区，深沟槽中填充高介电常数介质，多晶硅或金属，形成对器件内部栅极结构的封闭耐压保护圈；深沟槽中填充多晶硅或金属时最外圈的沟槽可以接地构成器件的防干扰屏蔽圈，有助于屏蔽和吸收开关过程中Vds的高频振荡干扰。通过在碳化硅MOSFET器件元胞中结合掩埋悬浮结构和与其相连的周边深沟槽保护结构，能进一步增强悬浮结MOSFET器件的耐压能力和抗干扰能力，减少边缘漏电。该申请的器件结构的周边深沟槽还可以作为seal ring保护芯片内部有源区，使划片的损伤裂纹等终止在沟槽区域，多个深沟槽保护环也可以有助于防止水汽和离子对于芯片有源区域的侵蚀，有利于增长器件的可靠性。
附图说明
图1为现有技术中碳化硅MOSFET器件的结构示意图；
图2为本发明的具有周边深沟槽保护环和接地环结构的碳化硅悬浮结MOSFET器件结构示意图；
图3为本发明的一种通过二次外延构造掩埋悬浮P+区均匀离散结构的工艺方法示意图；
图4为本发明的掩埋悬浮P+区不同掩埋结构的注入掩膜版图示意图。
具体实施方式
下面，参考附图，对本发明进行更全面的说明，附图中示出了本发明的示例性实施例。然而，本发明可以体现为多种不同形式，并不应理解为局限于这里叙述的示例性实施例。而是，提供这些实施例，从而使本发明全面和完整，并将本发明的范围完全地传达给本领域的普通技术人员。
如图1所示，现有技术中碳化硅SBD器件包括源极1、栅极2、漏极3、N+-Sub层、N—-epi层以及P-Well注入区。
如图2所示，本发明提供了一种具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，该碳化硅悬浮结MOSFET器件的外延层中分布着一层或多层掩埋构造的多个悬浮P+区4构成的均匀离散结构，碳化硅悬浮结MOSFET器件的周边JTE或者场限环到划片道5之间设置有若干个深沟槽保护结构6；深沟槽保护结构垂直穿透所述均匀离散结构；深沟槽保护结构的深沟槽中填充高介电常数介质、多晶硅或致密性孔洞填充特性好的金属，如钨和钛。
均匀离散结构的顶层与碳化硅悬浮结MOSFET器件的P-Well注入区的垂直距离为0.5-10um。
如图3所示，悬浮P+区4是碳化硅N型外延片P+注入后二次外延N-epi形成，或者是碳化硅N型外延片直接高能量注入形成的掩埋P+结。
如图4所示，均匀离散结构为P+方块状阵列结构、P+圆柱状阵列结构、P+六边形阵列结构、P+环块状阵列结构、P+三角形框状结构或P+四角形框状结构。
高介电常数介质为SiO2、SiNx、Al2O3、AlN、HfO2、MgO、Sc2O3、Ga2O3、AlHFOx、HFSiON材料中的一种或任意几种的组合。
本申请通过在碳化硅MOSFET器件元胞中结合掩埋悬浮结构和与其相连的周边深沟槽保护结构，能进一步增强悬浮结MOSFET器件的耐压能力和抗干扰能力，减少边缘漏电。该申请的器件结构的周边深沟槽还可以作为seal ring保护芯片内部有源区，使划片的损伤裂纹等终止在沟槽区域，多个深沟槽保护环也可以有助于防止水汽和离子对于芯片有源区域的侵蚀，有利于增长器件的可靠性。
上面所述只是为了说明本发明，应该理解为本发明并不局限于以上实施例，符合本发明思想的各种变通形式均在本发明的保护范围之内。

Claims (6)

1.一种具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，其特征在于，所述碳化硅悬浮结MOSFET器件的外延层中分布着一层或多层掩埋构造的多个悬浮P+区构成的均匀离散结构，碳化硅悬浮结MOSFET器件的周边JTE或者场限环到划片道之间设置有若干个深沟槽保护结构；所述深沟槽保护结构垂直穿透所述均匀离散结构；深沟槽保护结构的深沟槽中填充高介电常数介质、多晶硅或金属。
2.根据权利要求1所述的具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，其特征在于，所述均匀离散结构的顶层与所述碳化硅悬浮结MOSFET器件的P-Well注入区的垂直距离为0.5-10um。
3.根据权利要求1所述的具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，其特征在于，所述均匀离散结构为P+方块状阵列结构、P+圆柱状阵列结构、P+六边形阵列结构、P+环块状阵列结构、P+三角形框状结构或P+四角形框状结构。
4.根据权利要求1所述的具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，其特征在于，所述悬浮P+区是碳化硅N型外延片P+注入后二次外延N-epi形成，或者是碳化硅N型外延片直接高能量注入形成的掩埋P+结。
5.根据权利要求1所述的具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，其特征在于，所述高介电常数介质为SiO2、SiNx、Al2O3、AlN、HfO2、MgO、Sc2O3、Ga2O3、AlHFOx、HFSiON材料中的一种或任意几种的组合。
6.根据权利要求1所述的具有周边深沟槽保护环和接地环的碳化硅悬浮结MOSFET器件，其特征在于，所述金属为钨或钛。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216272A (zh) * 2018-09-04 2019-01-15 盛世瑶兰（深圳）科技有限公司 一种晶圆结构及其处理方法
WO2020181732A1 (zh) * 2019-03-12 2020-09-17 南京芯舟科技有限公司 半导体器件及其结边缘区
WO2021022614A1 (zh) * 2019-08-07 2021-02-11 南京芯舟科技有限公司 半导体器件及其结边缘区
WO2024026904A1 (zh) * 2022-08-03 2024-02-08 上海维安半导体有限公司 一种低压超结沟槽mos器件的制备方法及结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096715A1 (en) * 2001-01-25 2002-07-25 Wataru Sumida Semiconductor device
CN103413822A (zh) * 2013-08-22 2013-11-27 中国电子科技集团公司第二十四研究所 降低浮空埋层半导体器件漏电流的方法
CN104380472A (zh) * 2012-07-25 2015-02-25 住友电气工业株式会社 碳化硅半导体器件
EP2889915A1 (en) * 2013-12-30 2015-07-01 ABB Technology AG Power semiconductor device
CN105190899A (zh) * 2013-03-11 2015-12-23 住友电气工业株式会社 碳化硅半导体器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096715A1 (en) * 2001-01-25 2002-07-25 Wataru Sumida Semiconductor device
CN104380472A (zh) * 2012-07-25 2015-02-25 住友电气工业株式会社 碳化硅半导体器件
CN105190899A (zh) * 2013-03-11 2015-12-23 住友电气工业株式会社 碳化硅半导体器件
CN103413822A (zh) * 2013-08-22 2013-11-27 中国电子科技集团公司第二十四研究所 降低浮空埋层半导体器件漏电流的方法
EP2889915A1 (en) * 2013-12-30 2015-07-01 ABB Technology AG Power semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216272A (zh) * 2018-09-04 2019-01-15 盛世瑶兰（深圳）科技有限公司 一种晶圆结构及其处理方法
WO2020181732A1 (zh) * 2019-03-12 2020-09-17 南京芯舟科技有限公司 半导体器件及其结边缘区
WO2021022614A1 (zh) * 2019-08-07 2021-02-11 南京芯舟科技有限公司 半导体器件及其结边缘区
WO2024026904A1 (zh) * 2022-08-03 2024-02-08 上海维安半导体有限公司 一种低压超结沟槽mos器件的制备方法及结构

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