WO2024026904A1 - 一种低压超结沟槽mos器件的制备方法及结构 - Google Patents

一种低压超结沟槽mos器件的制备方法及结构 Download PDF

Info

Publication number
WO2024026904A1
WO2024026904A1 PCT/CN2022/110909 CN2022110909W WO2024026904A1 WO 2024026904 A1 WO2024026904 A1 WO 2024026904A1 CN 2022110909 W CN2022110909 W CN 2022110909W WO 2024026904 A1 WO2024026904 A1 WO 2024026904A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
trench
epitaxial layer
conductivity type
shallow
Prior art date
Application number
PCT/CN2022/110909
Other languages
English (en)
French (fr)
Inventor
刘厚超
黄宇萍
马一洁
张雨
苏亚兵
苏海伟
Original Assignee
上海维安半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海维安半导体有限公司 filed Critical 上海维安半导体有限公司
Publication of WO2024026904A1 publication Critical patent/WO2024026904A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a method for preparing a low-voltage superjunction trench MOS device and the structure of a low-voltage superjunction trench MOS device prepared using the method.
  • Trench MOS devices are based on charge balance technology, which develops the original triangular electric field into a trapezoidal electric field, which can achieve higher withstand voltage values on the epitaxial layer with a certain doping concentration. This is an important development direction of the current trench MOS device structure. ;Similarly, with the support of the analog electric field that introduces charge balance technology, an epitaxial layer with a higher ion doping concentration can be used while meeting the device voltage requirements, thereby greatly reducing the device's characteristic on-resistance Rsp, characteristic On-resistance is the on-resistance per unit area of the chip, which is an important indicator for measuring power MOS devices.
  • the low-voltage trench device structure that is widely used in charge balancing technology is the split-gate trench MOS device (Shield Gate Trench MOSFET, SGT MOSFET), which is characterized by the use of a deep trench shielded gate structure to achieve a thick oxide layer and epitaxial layer of the shielded gate.
  • SGT MOSFET Shid Gate Trench MOSFET
  • the present invention provides a preparation method and structure of a low-voltage superjunction trench MOS device.
  • a method for preparing a low-voltage superjunction trench MOS device including:
  • Step S1 providing a first conductivity type substrate, and forming an epitaxial layer of the first conductivity type on the substrate;
  • Step S2 Perform photolithography of at least one pillar area of the second conductivity type in the active area of the epitaxial layer, and each pillar area is formed according to a first preset number of injections;
  • Step S3 Perform photolithography of floating islands of the second conductivity type in the peripheral area of the epitaxial layer.
  • the floating islands are formed according to a second preset number of injections, and then the pillar areas and the floating islands are annealed. ;
  • Step S4 Form shallow trenches in the active area of the epitaxial layer.
  • the shallow trenches are located on both sides of the pillar area, and a hard mask layer with a predetermined thickness is provided at the bottom of the shallow trench.
  • the sidewalls of the shallow trench are provided with a gate oxide layer;
  • a deep trench is formed in the peripheral area of the epitaxial layer, the bottom and side walls of the deep trench are provided with a field oxide layer, and a polysilicon layer is formed in the shallow trench and the deep trench;
  • Step S5 Perform self-aligned implantation and annealing of the body region of the second conductivity type above the pillar region and the floating island, and then implant and anneal the implantation region of the first conductivity type above the body region. annealing;
  • Step S6 Deposit a dielectric layer and etch a plurality of contact holes above the device.
  • the plurality of contact holes extend downward from the upper surface of the dielectric layer to the body region and close to the active into the first deep trench in the area; subsequently, a metal layer is deposited and etched.
  • the step S4 specifically includes:
  • Step S41 Etch shallow trenches in the active region of the epitaxial layer, and the shallow trenches are located on both sides of the pillar region;
  • Step S42 deposit a hard masking layer above the epitaxial layer and in the shallow trench;
  • Step S43 using the hard masking layer as a mask, etching deep trenches in the peripheral area of the epitaxial layer, and growing a field oxide layer on the bottom and side walls of the deep trenches;
  • Step S44 perform a first deposition of polysilicon, and then perform etching or grinding to remove excess polysilicon above the hard mask layer;
  • Step S45 perform wet etching on the hard mask layer, leaving a preset thickness of the hard mask layer at the bottom of the shallow trench;
  • Step S46 Grow a gate oxide layer on the sidewall of the shallow trench, and then perform a second polysilicon deposition and reverse etching to make the polysilicon flush with the epitaxial layer.
  • photolithography of at least one pillar region of the second conductivity type in the active region of the epitaxial layer also includes:
  • a photoresist layer is formed above the epitaxial layer.
  • step S2 the first preset number of times is 3 to 6 times;
  • the injection energy is [300KEV, 3MEV].
  • step S3 the second preset number of times is 1 to 4 times;
  • the implanted impurity of the floating island is B;
  • the annealing temperature is 1000°C and the annealing time is 60 minutes.
  • the depth of the shallow trench is [0.9um, 1.8um].
  • the deposition thickness of the polysilicon layer is [0.8um, 1.2um].
  • the preset thickness is
  • step S4 the growth thickness of the gate oxide layer is
  • the invention also provides a structure of a low-voltage superjunction trench MOS device, which is prepared by the above-mentioned preparation method of a low-voltage superjunction trench MOS device, including:
  • An epitaxial layer of a first conductivity type is disposed above the substrate;
  • At least one pillar region of the second conductivity type is formed in the active region of the epitaxial layer, and each of the pillar regions is formed according to a first preset number of injections;
  • Floating islands of the second conductivity type are formed in the peripheral area of the epitaxial layer, and the floating islands are formed according to a second preset number of injections;
  • Shallow trenches are formed on both sides of each pillar area.
  • a hard mask layer with a predetermined thickness is provided at the bottom of the shallow trenches, and a gate oxide layer is provided on the sidewalls of the shallow trenches;
  • a deep trench is formed in the peripheral area of the epitaxial layer, and a field oxide layer is provided on the bottom and side walls of the deep trench;
  • Polysilicon layers are respectively provided in the shallow trenches and the deep trenches;
  • a body region of a second conductivity type is formed above the pillar region and the floating island;
  • An injection region of a first conductivity type is formed above the body region
  • a plurality of contact holes extending downward from the upper surface of the dielectric layer into the body region and the first deep trench close to the active region;
  • the active area of the device of the present invention has an alternating P/N pillar structure, and the peripheral area adopts a hybrid design of floating islands and deepened trenches.
  • the floating islands provide a longitudinal junction terminal extension structure JTE, and the deep trenches cut off the junction surface, making the device
  • the breakdown voltage is very close to the ideal breakdown voltage; the epitaxial layer with smaller resistivity is used to bear the pressure, thereby reducing the characteristic on-resistance of the device;
  • the device of the present invention compared with the shielded gate (SGT) technology, the device of the present invention has a wider safety Working area, larger overcurrent capability, smaller gate charge Qg and reverse recovery charge Qrr, while satisfying switching power supply applications and short-circuit capability applications, it is also particularly suitable for motor control and overcurrent protection related applications. It greatly reduces the peak voltage Vspike and ringing phenomenon generated when the switch is turned off, which helps to improve the electromagnetic interference EMI.
  • Figure 1 is a structural cross-sectional view of a multi-layer pillar region injected in a preferred embodiment of the present invention
  • Figure 2 is a structural cross-sectional view of the pillar area and the floating island after annealing in a preferred embodiment of the present invention
  • Figure 3 is a cross-sectional view of the structure after shallow trench etching
  • Figure 4 is a cross-sectional view of the structure after etching of the hard mask layer
  • Figure 5 is a cross-sectional view of the structure after deep trench etching and field oxide layer growth in the deep trench;
  • Figure 6 is a cross-sectional view of the structure after the first deposition of polysilicon
  • Figure 7 is a structural cross-sectional view of polysilicon after reverse etching
  • Figure 8 is a cross-sectional view of the structure after wet etching
  • Figure 9 is a cross-sectional view of the structure after the second deposition of polysilicon
  • Figure 10 is a cross-sectional view of the structure after forming the body region and the injection region;
  • Figure 11 is a cross-sectional view of the structure after forming the dielectric layer, contact holes and metal layer.
  • the conductivity type includes a first conductivity type and a second conductivity type, and the first conductivity type and the second conductivity type are opposite, for example:
  • the second conductivity type is P type (this is used as an example below);
  • the second conductivity type is N type.
  • the N+ type and N type mentioned below refer to different conditions of doping concentration. Specifically, the doping concentration of the N type is smaller than that of the N+ type.
  • embodiments of the present invention provide a method for preparing a low-voltage superjunction trench MOS device. The specific steps are as follows:
  • Step S1 as shown in Figure 1, provides a first conductivity type substrate 1, and forms a first conductivity type epitaxial layer 2 on the substrate 1;
  • a heavily doped N+ type substrate 1 is provided, and an N-type epitaxial layer 2 is formed on the substrate 1.
  • the resistivity of the epitaxial layer is reduced, achieving the same impact compared to traditional trench MOS devices.
  • the resistivity of the epitaxial layer of the superjunction structure of the present invention can be 50% or less of the former.
  • Step S2 as shown in Figure 1, perform photolithography of at least one pillar area 3 of the second conductivity type in the active area of the epitaxial layer 2, and each pillar area 3 is formed according to a first preset number of injections;
  • the first preset number of times is 3 to 6 times
  • the injection energy is [300KEV, 3MEV].
  • photolithography and implantation of the superjunction P-type pillar region 3 are performed on the epitaxial layer 2.
  • the P-type pillar region 3 is divided into three to six injections, and each injection energy ranges from 300KEV to 3MEV. The specific number of injections and energy depends on the rated voltage.
  • this embodiment includes two P-type pillar areas 3.
  • Each P-type pillar area 3 is formed by injecting B three times. The multiple times of energy are divided into high, medium and low energy levels, and the injection is used in combination to form the P-type pillar area. 3.
  • Step S3 photolithography is performed on the floating islands 5 of the second conductivity type in the peripheral area of the epitaxial layer 2.
  • the floating islands 5 are formed according to a second preset number of injections, and then the pillar areas 3 and the floating islands are formed. 5 perform annealing;
  • the second preset number of times is 1 to 4 times
  • the implanted impurity of floating island 5 is B;
  • the annealing temperature is 1000°C and the annealing time is 60 minutes.
  • photolithography and implantation of the P-type floating island 5 are performed on the epitaxial layer 2, and the floating island 5 is used as a pressure limiting ring.
  • the implanted impurity of the P-type floating island 5 is B, which is divided into one to four. Step injection, the specific number of injections depends on the rated voltage.
  • the p-type column area 3 and the P-type floating island 5 are injected and annealed.
  • the annealing temperature is 1000°C and the annealing time is 60 minutes.
  • Step S4 Form shallow trenches 6 in the active area of the epitaxial layer 2.
  • the shallow trenches 6 are located on both sides of the pillar area 3, and a hard mask layer 7 with a predetermined thickness is provided at the bottom of the shallow trench 6.
  • the shallow trench 6 The sidewall of 6 is provided with a gate oxide layer 61; and
  • a deep trench 8 is formed in the peripheral area of the epitaxial layer 2.
  • the bottom and side walls of the deep trench 8 are provided with a field oxide layer 81.
  • a polysilicon layer 9 is formed in the shallow trench 6 and the deep trench 8;
  • step S4 specifically includes:
  • Step S41 as shown in Figure 3, etching shallow trenches 6 in the active area of the epitaxial layer 2, and the shallow trenches 6 are located on both sides of the pillar area 3;
  • the shallow trench 6 in the cell active area (abbreviation: active area) is etched.
  • the depth of the shallow trench 6 is [0.9um, 1.8um]. The specific depth depends on Depends on rated voltage.
  • Step S42 deposit a hard masking layer 7 above the epitaxial layer 2 and in the shallow trench 6;
  • silicon dioxide is used to deposit the hard masking layer 7, and the thickness of the hard masking layer 7 is not less than
  • the hard mask layer 7 is photolithographed and etched to transfer the photoresist pattern of the deep trench 8 below to the hard mask layer 7 .
  • Step S43 as shown in Figure 5, use the hard mask layer 7 as a mask to etch the deep trench 8 in the peripheral area of the epitaxial layer 2, and grow a field oxide layer 81 on the bottom and side walls of the deep trench 8;
  • step S43 a thermal oxidation method or a chemical vapor deposition method is used to grow and form the field oxide layer 81;
  • the growth thickness of the field oxide layer 81 is
  • the hard masking layer 7 is used as a mask to perform dry etching of the deep trench 8 of the pressure limiting ring in the peripheral area; at the same time, the hard masking layer 7 is used as an oxidation mask, and in the deep trench 8
  • the growth methods generally include thermal oxidation and chemical vapor deposition.
  • the growth thickness of the field oxide layer 81 is between to The specific growth thickness is modulated according to the device voltage.
  • the floating island 5 is close to the main junction, and the deep trench 8 expands in the peripheral area.
  • the positions of the floating island 5 and the deep trench 8 are fixed. If the positions are changed, the electric field cannot effectively and safely drop and cut off.
  • Step S44 as shown in Figures 6 and 7, performs the first deposition of polysilicon, and then etches or grinds to remove excess polysilicon above the hard mask layer 7;
  • polysilicon is deposited in the deep trench 8, and the thickness of the polysilicon layer 9 after the first deposition is [0.8um, 1.2um];
  • the polysilicon is etched or polished, leaving only the polysilicon in the deep trench 8.
  • Step S45 as shown in Figure 8, perform wet etching on the hard masking layer 7, leaving a predetermined thickness of the hard masking layer 7 at the bottom of the shallow trench 6;
  • step S45 the preset thickness is
  • the hard masking layer 7 is wet etched, and by controlling the etching time, approximately Thick oxygen remains, the thickness of the remaining hard mask layer 7 is modulated with different voltage devices, and the rest of the hard mask is removed;
  • the polysilicon layer 9 is flush with the hard mask layer 7, or lower than the height of the hard mask layer 7, but the etching or polishing The final polysilicon layer 9 will completely cover the field oxide layer 81 in the deep trench 8 , so that the field oxide layer 81 in the deep trench 8 can remain under the shielding protection of the polysilicon layer 9 .
  • the field oxide layer 81 is formed by high-temperature thermal growth in the furnace tube, if there is no shielding by the hard mask layer 7 (silicon dioxide), all exposed silicon surfaces, including the bottom of the deep trench 8 and the sides of the deep trench 8, will be exposed.
  • the hard mask layer 7 silicon dioxide
  • the field oxide layer 81 grows on the entire surface of the wall and the platform, and it is impossible to accurately realize the field oxide layer 81 with a thick oxygen structure at the bottom and side walls of the deep trench, and the requirement that a thick oxygen structure only exists at the bottom of the shallow trench; the present invention utilizes filling in the shallow trench 6
  • the hard masking layer 7 uses the hard masking layer 7 as a barrier to grow the field oxide layer 81 only in the deep trench 8; the polysilicon layer 9 filled in the deep trench 8 is used as a barrier to retain the thick oxide structure at the bottom of the shallow trench 6. This special sequence of processes is cleverly composed and reduces the preparation cost of the device.
  • Step S46 as shown in FIG. 9 , the gate oxide layer 61 is grown on the sidewall of the shallow trench 6 , and then a second polysilicon deposition and reverse etching are performed to make the polysilicon flush with the epitaxial layer 2 .
  • step S4 the growth thickness of the gate oxide layer 61 is
  • thermal oxidation growth of the gate oxide layer 61 in the shallow trench 6 in the active area is performed.
  • the gate oxide layer 61 is located on the inner sidewall of the shallow trench 6.
  • the growth thickness of the gate oxide layer 61 is Then, polysilicon deposition and reverse etching in the shallow trench 6 in the active area are performed.
  • the hard mask layer 7 at the bottom of the shallow trench 6 has a thick oxide structure
  • the sidewall gate oxide layer 61 has a thin oxide structure, which is used for functional capacitance control
  • the field oxide layer inside the deep trench 8 81 is a thick oxygen structure, used as a pressure resistance.
  • the floating island 5 is formed first, and then the hard masking layer 7 is formed.
  • the floating island 5 is implanted immediately after the P-type pillar region 3 is injected, so that the floating island 5 can be in contact with the P-type pillar region 3.
  • a furnace tube thermal process can be shared; if the hard masking layer 7 is formed first and then the floating island 5 is formed, another furnace tube thermal process needs to be added specifically for annealing the floating island 5, which increases unnecessary thermal budget and production costs.
  • Step S5 as shown in Figure 10, perform self-aligned implantation and annealing of the body region 10 of the second conductivity type above the pillar region 3 and the floating island 5, and then perform implantation of the first conductivity type above the body region 10. Implantation and annealing of zone 11;
  • the P-type body region 10 is located above the P-type pillar region 3 and between two adjacent shallow trenches 6 . During the period, both ends of the P-type body region 10 are in contact with the outer walls of the shallow trenches 6 on both sides; after the P-type body region 10 is formed, the N+-type implantation region 11 (i.e., the source region) is implanted and annealed.
  • the N+-type implantation The region 11 is located above the P-type body region 10 and between two adjacent shallow trenches 6. The two ends of the N+-type implanted region 11 are in contact with the outer walls of the shallow trenches 6 on both sides.
  • Step S6 as shown in FIG. 11, the dielectric layer 12 is deposited and a plurality of contact holes 13 are etched above the device.
  • the plurality of contact holes 13 extend downward from the upper surface of the dielectric layer 12 to the body region 10 and In the first deep trench 8 close to the active area; subsequently, the metal layer 14 is deposited and etched.
  • the isolation dielectric layer 12 is deposited and the plurality of contact holes 13 are etched, and then the metal layer 14 is deposited and etched.
  • the metal layer 14 is the source of the device. pole; wherein, the dielectric layer 12 covers the upper surface of the device prepared in step S5, and then etches windows corresponding to the above-mentioned N+ type injection region 11 and the first deep trench 8 in the dielectric layer 12, and deposits to form contacts. Hole 13.
  • the body region 10 above the floating island 5 and the first deep trench 8 close to the active region need to be short-circuited with the metal layer 14 through the contact hole 13 .
  • step S2 photolithography of at least one pillar region 3 of the second conductivity type is performed in the active region of the epitaxial layer 2, as shown in Figure 1, which also includes:
  • a photoresist layer 4 is formed above the epitaxial layer 2 .
  • a photoresist layer 4 needs to be formed above the epitaxial layer.
  • the photoresist layer 4 covers the entire upper surface of the epitaxial layer 2, and then the photoresist layer 4 is A window corresponding to the P-type pillar region 3 is etched in the resist layer 4 through a photolithography process.
  • the process uses multiple high-energy injections and annealing with different energies to generate the P-type pillar region 3, and multiple high-energy injections to achieve the pressure-limiting structure of the floating island 5;
  • the hard mask layer 7 is used as a shield to create deep trenches
  • the field oxide layer 81 in the deep trench 8 is generated, and the polysilicon layer 9 in the deep trench 8 is used as a shield to remove the hard mask layer 7 in the shallow trench 6.
  • the hard mask layer 7 in the shallow trench 6 is removed. Control, the remaining part of the hard masking layer 7 serves as the thick oxygen region at the bottom of the shallow trench 6 .
  • the resistivity specification of the epitaxial layer 2 of the ordinary trench MOS device is less than 50%, and the thickness of the epitaxial layer 2 is 80 % or less, thereby obtaining a characteristic on-resistance that is relatively significantly better than that of conventional trench MOS by 50% or more; using a denser and thinner epitaxy to bear the pressure, thereby reducing the characteristic on-resistance of the device.
  • the N-type epitaxial layer in the active area of the device is isolated and pinched into N-type pillar areas by the P-type pillar area, forming an alternating P/N pillar structure.
  • space charge balance technology is used to efficiently achieve reverse blocking capability.
  • the peripheral area of the device adopts a hybrid design of P-type floating island 5 and deep trench 8.
  • P-type floating island 5 provides longitudinal JTE, and deep trench 8 cuts off the junction surface, which can make the breakdown voltage of the device very close to the ideal breakdown voltage.
  • the device characteristics have a wider safe operating area, larger overcurrent capability, smaller Qg and Qrr, and are particularly suitable for applications related to motor control and overcurrent protection.
  • the present invention also provides a structure of a low-voltage superjunction trench MOS device, which is prepared by the above-mentioned preparation method of a low-voltage superjunction trench MOS device, see Figures 1-11, and includes:
  • a first conductivity type substrate 1 A first conductivity type substrate 1;
  • the epitaxial layer 2 of the first conductivity type is disposed above the substrate 1;
  • At least one pillar region 3 of the second conductivity type is formed in the active region of the epitaxial layer 2, and each pillar region 3 is implanted according to a first preset number of times;
  • the floating islands 5 of the second conductivity type are formed in the peripheral area of the epitaxial layer 2, and the floating islands 5 are formed according to a second preset number of injections;
  • Shallow trenches 6 are formed on both sides of each pillar area 3.
  • the bottom of the shallow trenches 6 is provided with a hard mask layer 7 of a predetermined thickness, and the side walls of the shallow trenches 6 are provided with a gate oxide layer 61;
  • the deep trench 8 is formed in the peripheral area of the epitaxial layer 2, and the bottom and side walls of the deep trench 8 are provided with a field oxide layer 81;
  • Polysilicon layer 9 is provided in shallow trench 6 and deep trench 8 respectively;
  • the body region 10 of the second conductivity type is formed above the pillar region 3 and the floating island 5;
  • the first conductive type injection region 11 is formed above the body region 10;
  • Dielectric layer 12 is formed above the epitaxial layer 2;
  • a plurality of contact holes 13 extending downward from the upper surface of the dielectric layer 12 into the body area 10 and the first deep trench 8 close to the active area;
  • Metal layer 14 covers the top of the device.
  • the breakdown voltage of the device prepared using the low-voltage superjunction trench MOS device preparation method in Embodiment 1 is 30-200V, in which the device carrier is single crystal silicon, including substrate 1 and epitaxial layer 2.
  • the device structure is mainly in the epitaxial layer 2, specifically including the active area and the peripheral area.
  • the active area is the device functional area, and the peripheral area assists the main junction voltage of the active area;
  • the active area includes a shallow trench 6, a P-type body area 10, and a P-type pillar area 3.
  • the shallow trench 6 has a bottom hard mask layer 7, a sidewall gate oxide layer 61 and a polysilicon layer 9.
  • the hard mask layer 7 is Thick oxide structure
  • the above-mentioned gate oxide layer 61 is a thin oxide structure
  • the P-type body region 10 combines with the sidewall gate oxide layer 61 of the shallow trench 6 to form a conductive channel
  • the P-type pillar region 3 combines with the thick gate oxide layer 61 at the bottom of the shallow trench 6
  • the oxygen structure enables the cell area to withstand pressure;
  • the peripheral area consists of floating island area 5 and deep trench area 8.
  • Floating island area 5 includes P-type floating island 5 and P-type body area 10.
  • Deep trench area 8 contains at least one deep trench 8, and the bottom of deep trench 8 There is a field oxide layer 81 on the side wall.
  • the field oxide layer 81 has a thick oxygen structure.
  • the floating island area 5 and the deep trench area 8 are combined to cut off and limit the electric field of the cell; it is close to the first deep trench in the cell area.
  • the voltage limiting ring of slot 8 adopts the contact hole 13 and the source metal layer 14 to be at the same potential.
  • the device features of this invention combine the on-resistance of SGT MOSFET and the wide safe operating area of Planar MOSFET, which can simultaneously meet switching power supply applications, over-current protection applications and short-circuit capability applications. Its excellent characteristics are attributed to the device design concept that is different from SGT-MOSFET.
  • SGT-MOSFET optimizes the characteristic on-resistance by reducing the resistivity of the epitaxial layer 2 by reducing the lateral element pitch (cell pitch). The reduced cell pitch increases the cell density, making it difficult to dissipate heat.
  • the thermal resistance increases, the overcurrent capability decreases sharply, and the safe working area Narrow structure is not suitable for high current-related applications; while the low-voltage superjunction structure of the present invention uses the longitudinal junction depth to reduce the epitaxial resistivity, which can be achieved without reducing the cell pitch.

Abstract

本发明涉及一种低压超结沟槽MOS器件的制备方法及结构，涉及半导体技术领域，包括：步骤S1，于衬底上形成外延层；步骤S2，于外延层中形成至少一个柱区；步骤S3，于外延层中形成浮岛；步骤S4，于外延层中形成浅沟槽，且浅沟槽的底部设有硬掩蔽层，浅沟槽的侧壁设有栅氧化层；以及于外延层中形成深沟槽，深沟槽的底部和侧壁设有场氧化层，浅沟槽和深沟槽内形成多晶硅层；步骤S5，于柱区和浮岛的上方形成体区，然后于体区的上方形成注入区；步骤S6，进行介质层的淀积和多个接触孔的刻蚀，进行金属层的淀积和刻蚀。本发明器件的安全工作区更宽，过电流能力更大，栅极电荷及反向恢复电荷更小，特征导通电阻较低。

Description

一种低压超结沟槽MOS器件的制备方法及结构 技术领域
本发明涉及半导体技术领域，尤其涉及一种低压超结的沟槽MOS器件的制备方法及应用该方法制备得到的低压超结沟槽MOS器件的结构。
背景技术
沟槽MOS器件基于电荷平衡技术，使得原有三角形电场发展为类梯形电场，可以在一定掺杂浓度的外延层上实现更高的耐压值，是目前沟槽MOS器件结构的一个重要发展方向；同样地，在引入电荷平衡技术的类体型电场的支持下，可在满足器件耐压要求的同时采用离子掺杂浓度更浓的外延层，继而大幅度降低器件的特征导通电阻Rsp，特征导通电阻是芯片单位面积上的导通电阻，这是衡量功率MOS器件的一项重要指标。
目前电荷平衡技术应用比较广泛的低压沟槽器件结构是分裂栅沟槽MOS器件(Shield Gate Trench MOSFET，SGT MOSFET)，其特点是采用深沟槽屏蔽栅结构，实现屏蔽栅厚氧化层和外延层之间的平衡耗尽，实现二维电场的搭建，可以大幅度降低外延层电阻率，实现大幅优化特征导通电阻的目的；同时分裂栅结构的引入大幅度地削减栅极-漏极电容Cgd的接触面积，同时获得很小的米勒级的电容Cgd，使得器件开关过程中具有较短时间的米勒平台过渡，极大地加快了器件的开关速度，降低了开关损耗，非常适合开关式电源应用(SMPS)。 但任何事情都有两面性，但面对MOSFET应用在过流保护，短路保护等相关领域，过短的米勒平台，使得dv/dt过大，瞬态功率急速拉升，器件在短路保护关断过程中易发生热电烧毁，限制了器件过流保护领域的安全工作区，因此针对以上问题，有必要设计出一种低特征导通电阻、EMI特性优越的低压超结的沟槽MOS器件的制备方法及结构，同时具有屏蔽栅MOS很低的特征导通电阻和planar MOS较宽的安全工作区，以满足特定应用场景的需要。
发明内容
为了解决以上技术问题，本发明提供了一种低压超结沟槽MOS器件的制备方法及结构。
本发明所解决的技术问题可以采用以下技术方案实现：
一种低压超结沟槽MOS器件的制备方法，包括：
步骤S1，提供一第一导电类型的衬底，并于所述衬底上形成第一导电类型的外延层；
步骤S2，于所述外延层的有源区进行至少一个第二导电类型的柱区的光刻，每一所述柱区按照一第一预设次数注入形成；
步骤S3，于所述外延层的外围区进行第二导电类型的浮岛的光刻，所述浮岛按照一第二预设次数注入形成，然后对所述柱区和所述浮岛进行退火；
步骤S4，于所述外延层的有源区形成浅沟槽，所述浅沟槽位于所述柱区的两侧，且所述浅沟槽的底部设有一预设厚度的硬掩蔽层，所述浅沟槽的侧壁设有栅氧化层；以及
于所述外延层的外围区形成深沟槽，所述深沟槽的底部和侧壁设 有场氧化层，所述浅沟槽和所述深沟槽内形成多晶硅层；
步骤S5，于所述柱区和所述浮岛的上方进行第二导电类型的体区的自对准注入和退火，然后于所述体区的上方进行第一导电类型的注入区的注入和退火；
步骤S6，于器件的上方进行介质层的淀积和多个接触孔的刻蚀，多个所述接触孔自所述介质层的上表面向下延伸至所述体区和靠近所述有源区的第一个所述深沟槽内；随后，进行金属层的淀积和刻蚀。
上述的一种低压超结沟槽MOS器件的制备方法，所述步骤S4具体包括：
步骤S41，于所述外延层的有源区进行浅沟槽的刻蚀，所述浅沟槽位于所述柱区的两侧；
步骤S42，于所述外延层的上方和所述浅沟槽内淀积形成硬掩蔽层；
步骤S43，以所述硬掩蔽层为掩蔽，于所述外延层的外围区进行深沟槽的刻蚀，并于所述深沟槽的底部和侧壁生长场氧化层；
步骤S44，进行第一次多晶硅的淀积，然后进行刻蚀或研磨，去除所述硬掩蔽层上方的多余的所述多晶硅；
步骤S45，对所述硬掩蔽层进行湿法腐蚀，于所述浅沟槽的槽底残留一预设厚度的所述硬掩蔽层；
步骤S46，于所述浅沟槽的侧壁进行栅氧化层的生长，然后进行第二次多晶硅的淀积和反刻，使所述多晶硅与所述外延层齐平。
上述的一种低压超结沟槽MOS器件的制备方法，所述步骤S2中，于所述外延层的有源区进行至少一个第二导电类型的柱区的光刻，之前还包括：
于所述外延层的上方形成光阻层。
上述的一种低压超结沟槽MOS器件的制备方法，所述步骤S2中，所述第一预设次数为3～6次；
注入能量为[300KEV，3MEV]。
上述的一种低压超结沟槽MOS器件的制备方法，所述步骤S3中，所述第二预设次数为1～4次；
所述浮岛的注入杂质为B；
退火温度为1000℃，退火时间为60min。
上述的一种低压超结沟槽MOS器件的制备方法，所述步骤S4中，所述浅沟槽的深度为[0.9um，1.8um]。
上述的一种低压超结沟槽MOS器件的制备方法，所述步骤S44中，所述多晶硅层的淀积厚度为[0.8um，1.2um]。
上述的一种低压超结沟槽MOS器件的制备方法，所述步骤S45中，所述预设厚度为
Figure PCTCN2022110909-appb-000001
上述的一种低压超结沟槽MOS器件的制备方法，所述步骤S4中，所述栅氧化层的生长厚度为
Figure PCTCN2022110909-appb-000002
本发明还提供一种低压超结沟槽MOS器件的结构，采用如上述的低压超结沟槽MOS器件的制备方法制备得到，包括：
第一导电类型的衬底；
第一导电类型的外延层，设置于所述衬底的上方；
至少一个第二导电类型的柱区，形成于所述外延层的有源区，且每一所述柱区按照一第一预设次数注入形成；
第二导电类型的浮岛，形成于所述外延层的外围区，且所述浮岛按照一第二预设次数注入形成；
浅沟槽，形成于每一所述柱区的两侧，所述浅沟槽的底部设有一预设厚度的硬掩蔽层，所述浅沟槽的侧壁设有栅氧化层；
深沟槽，形成于所述外延层的外围区，所述深沟槽的底部和侧壁设有场氧化层；
多晶硅层，分别设置于所述浅沟槽和所述深沟槽内；
第二导电类型的体区，形成于所述柱区和所述浮岛的上方；
第一导电类型的注入区，形成于所述体区的上方；
介质层，形成于所述外延层的上方；
多个接触孔，多个所述接触孔自所述介质层的上表面向下延伸至所述体区和靠近所述有源区的第一个所述深沟槽内；
金属层，覆盖器件的上方。
本发明技术方案的有益效果在于：
本发明器件有源区为P/N柱(pillar)交替结构，外围区采用浮岛加深沟槽的混合型设计，浮岛提供纵向的结终端延伸结构JTE，深沟槽截断结曲面，使得器件的击穿电压非常接近理想击穿电压；采用电阻率更小的外延层来承压，从而降低器件的特征导通电阻；相较于屏蔽栅(SGT)技术，本发明器件具有更宽的安全工作区，更大的过电流能力，更小的栅极电荷Qg及反向恢复电荷Qrr，在满足开关式电源应用以及短路能力应用的同时，还特别适合马达控制及过流保护的相关应用，大幅减小开关关断时产生的尖峰电压Vspike及振铃现象，有助于电磁干扰EMI的改善。
附图说明
图1为本发明较佳的实施例中，注入多层柱区的结构剖面图；
图2为本发明较佳的实施例中，柱区和浮岛退火后的结构剖面图；
图3为浅沟槽刻蚀后的结构剖面图；
图4为硬掩蔽层刻蚀后的结构剖面图；
图5为深沟槽刻蚀和深沟槽内生长场氧化层后的结构剖面图；
图6为第一次淀积多晶硅后的结构剖面图；
图7为多晶硅反刻后的结构剖面图；
图8为湿法腐蚀后的结构剖面图；
图9为第二次淀积多晶硅后的结构剖面图；
图10为形成体区和注入区后的结构剖面图；
图11为形成介质层、接触孔和金属层后的结构剖面图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。
下面结合附图和具体实施例对本发明作进一步说明，但不作为本发明的限定。
本发明实施例中导电类型包括第一导电类型和第二导电类型，第一导电类型和第二导电类型相反，例如：
若第一导电类型为N型，则第二导电类型为P型(下文中以此为例)；
若第一导电类型为P型，则第二导电类型为N型。
其中，下文中所提及的N+型以及N型均指掺杂浓度的不同情况，具体地，N型的掺杂浓度小于N+型。
实施例一
参照图1-11，本发明实施例提供一种低压超结沟槽MOS器件的制备方法，具体步骤如下：
步骤S1，如图1所示，提供一第一导电类型的衬底1，并于衬底1上形成第一导电类型的外延层2；
具体的，在本实施例中，提供重掺杂的N+型衬底1，并在衬底1上形成N型外延层2，外延层的电阻率降低，相对传统沟槽MOS器件，达到相同击穿电压时，本发明超结结构的外延层的电阻率可以为前者的50％及以下。
步骤S2，如图1所示，于外延层2的有源区进行至少一个第二导电类型的柱区3的光刻，每一柱区3按照一第一预设次数注入形成；
作为优选的实施方式，其中，步骤S2中，第一预设次数为3～6次；
注入能量为[300KEV，3MEV]。
具体的，在本实施例中，在外延层2上进行超结P型柱区3的光刻和注入，P型柱区3分为三至六次注入，每次注入能量介于300KEV～3MEV之间，具体注入次数和注入能量视额定电压而定。优选的，本实施例包括两个P型柱区3，每一P型柱区3分别分3次注入B形成，多次能量分开高、中、低能量档，搭配使用注入形成P 型柱区3。
步骤S3，如图2所示，于外延层2的外围区进行第二导电类型的浮岛5的光刻，浮岛5按照一第二预设次数注入形成，然后对柱区3和浮岛5进行退火；
作为优选的实施方式，其中，步骤S3中，第二预设次数为1～4次；
浮岛5的注入杂质为B；
退火温度为1000℃，退火时间为60min。
具体的，在本实施例中，在外延层2上进行P型浮岛5的光刻和注入，采用浮岛5作为限压环，P型浮岛5的注入杂质为B，分为一至四步注入，具体注入次数视额定电压而定，对p型柱区3和P型浮岛5注入进行退火，退火温度为1000℃，退火时间为60min。
步骤S4，于外延层2的有源区形成浅沟槽6，浅沟槽6位于柱区3的两侧，且浅沟槽6的底部设有一预设厚度的硬掩蔽层7，浅沟槽6的侧壁设有栅氧化层61；以及
于外延层2的外围区形成深沟槽8，深沟槽8的底部和侧壁设有场氧化层81，浅沟槽6和深沟槽8内形成多晶硅层9；
作为优选的实施方式，其中，步骤S4具体包括：
步骤S41，如图3所示，于外延层2的有源区进行浅沟槽6的刻蚀，浅沟槽6位于柱区3的两侧；
具体的，在本实施例中，进行元胞有源区(简称：有源区)内的浅沟槽6的刻蚀，浅沟槽6的深度为[0.9um，1.8um]，具体深度视额定电压而定。
步骤S42，如图4所示，于外延层2的上方和浅沟槽6内淀积形 成硬掩蔽层7；
具体的，在本实施例中，采用二氧化硅进行硬掩蔽层7的淀积，硬掩蔽层7的淀积厚度不低于
Figure PCTCN2022110909-appb-000003
进一步的，对硬掩蔽层7的光刻，刻蚀，将下文中的深沟槽8的光刻板图形转移到硬掩蔽层7上。
步骤S43，如图5所示，以硬掩蔽层7为掩蔽，于外延层2的外围区进行深沟槽8的刻蚀，并于深沟槽8的底部和侧壁生长场氧化层81；
作为优选的实施方式，其中，步骤S43中，采用热氧化法或化学气相淀积法生长形成场氧化层81；
场氧化层81的生长厚度为
Figure PCTCN2022110909-appb-000004
具体的，在本实施例中，以硬掩蔽层7为掩蔽，进行外围区限压环的深沟槽8的干法刻蚀；同时以硬掩蔽层7为氧化掩蔽，在深沟槽8内进行具体限压作用的场氧化层81的生长，生长方法一般包括热氧化法和化学气相淀积法两种，场氧化层81的生长厚度在
Figure PCTCN2022110909-appb-000005
至
Figure PCTCN2022110909-appb-000006
之间，具体生长厚度依据器件电压的不同进行调制。
进一步的，浮岛5靠近主结，深沟槽8在外围区扩展，浮岛5和深沟槽8的位置是固定的，如果更换位置，电场不能有效安全降落截止。
步骤S44，如图6和图7所示，进行第一次多晶硅的淀积，然后进行刻蚀或研磨，去除硬掩蔽层7上方的多余的多晶硅；
具体的，在本实施例中，进行深沟槽8内的多晶硅淀积，第一次淀积后的多晶硅层9的淀积厚度为[0.8um，1.2um]；
进一步的，进行多晶硅的刻蚀或研磨，只在深沟槽8内留下多晶 硅。
步骤S45，如图8所示，对硬掩蔽层7进行湿法腐蚀，于浅沟槽6的槽底残留一预设厚度的硬掩蔽层7；
作为优选的实施方式，其中，步骤S45中，预设厚度为
Figure PCTCN2022110909-appb-000007
具体的，在本实施例中，对硬掩蔽层7进行湿法腐蚀，通过控制腐蚀时间，在浅沟槽6的底部形成约
Figure PCTCN2022110909-appb-000008
的厚氧残留，残留的硬掩蔽层7的厚度随不同电压器件不同而调制，其余部分硬掩蔽均去除；
进一步的，由于硬掩蔽层7的存在，使得步骤S44中对多晶硅进行刻蚀或研磨后，多晶硅层9与硬掩蔽层7齐平，或者低于硬掩蔽层7的高度，但是刻蚀或研磨后的多晶硅层9会完全覆盖住深沟槽8内的场氧化层81，使得深沟槽8内的场氧化层81在多晶硅层9的掩蔽保护下得以留存。
由于场氧化层81的形成是在炉管高温热生长进行，如果没有硬掩蔽层7(二氧化硅)的屏蔽，会在所有裸漏的硅表面包括深沟槽8底部，深沟槽8侧壁，平台表面全部生长场氧化层81，无法精准实现深槽底部和侧壁具有厚氧结构的场氧化层81，浅槽只有底部存在厚氧结构的要求；本发明利用浅沟槽6中填充硬掩蔽层7以硬掩蔽层7为阻挡，只在深沟槽8生长场氧化层81；以深沟槽8内的多晶硅层9填充为阻挡，进行浅沟槽6底部的厚氧结构的保留，该种特殊顺序的工艺巧妙组成，降低了器件的制备成本。
步骤S46，如图9所示，于浅沟槽6的侧壁进行栅氧化层61的生长，然后进行第二次多晶硅的淀积和反刻，使多晶硅与外延层2齐平。
作为优选的实施方式，其中，步骤S4中，栅氧化层61的生长厚度为
Figure PCTCN2022110909-appb-000009
具体的，在本实施例中，进行有源区浅沟槽6内的栅氧化层61的热氧化生长，栅氧化层61位于浅沟槽6的内侧侧壁，栅氧化层61的生长厚度为
Figure PCTCN2022110909-appb-000010
然后，进行有源区浅沟槽6内的多晶硅淀积和反刻。
进一步的，本发明中浅沟槽6的底部的硬掩蔽层7为厚氧结构，侧壁栅氧化层61为薄氧结构，作为功能性电容控制使用；而深沟槽8内地的场氧化层81为厚氧结构，作为耐压使用。
需注意的是，本发明实施例中先形成浮岛5，再形成硬掩蔽层7，在P型柱区3注入后即进行浮岛5注入，使得浮岛5可以与P型柱区3在退火时可以共用一道炉管热过程；如果先形成硬掩蔽层7，再形成浮岛5，需要再增加一道专门针对浮岛5退火的炉管热过程，增加不必要的热预算和生产成本。
步骤S5，如图10所示，于柱区3和浮岛5的上方进行第二导电类型的体区10的自对准注入和退火，然后于体区10的上方进行第一导电类型的注入区11的注入和退火；
具体的，在本实施例中，进行P型体区10的自对准注入和退火，P型体区10位于位于P型柱区3的上方，且位于相邻的两个浅沟槽6之间，P型体区10的两端与两侧的浅沟槽6的外壁相接触；形成P型体区10之后，进行N+型注入区11(即源区)的注入和退火，N+型注入区11位于位于P型体区10的上方，且位于相邻的两个浅沟槽6之间，N+型注入区11的两端与两侧的浅沟槽6的外壁相接触。
步骤S6，如图11所示，于器件的上方进行介质层12的淀积和 多个接触孔13的刻蚀，多个接触孔13自介质层12的上表面向下延伸至体区10和靠近有源区的第一个深沟槽8内；随后，进行金属层14的淀积和刻蚀。
具体的，在本实施例中，进行隔离作用的介质层12的淀积和多个接触孔13的刻蚀，然后进行金属层14的淀积和刻蚀，该金属层14即为器件的源极；其中，介质层12覆盖上述步骤S5制备得到器件的上表面，然后在介质层12中刻蚀出对应上述N+型注入区11、以及第一个深沟槽8的窗口，淀积形成接触孔13。
需注意的是，浮岛5上方的体区10和靠近有源区的第一个深沟槽8需要通过接触孔13与金属层14短接。
作为优选的实施方式，其中，步骤S2中，于外延层2的有源区进行至少一个第二导电类型的柱区3的光刻，如图1所示，之前还包括：
于外延层2的上方形成光阻层4。
具体的，在本实施例中，在进行P型柱区3的光刻之间，需要在外延层的上方形成光阻层4，光阻层4覆盖整个外延层2的上表面，然后在光阻层4中通过光刻工艺刻蚀出对应P型柱区3的窗口。
于上述较佳的实施例中，在制备低压超结结构的沟槽MOS器件的方法过程中，将各类工艺巧妙组合，不需要额外的特殊工艺和多层外延技术，最大化降低工艺复杂性和光刻版层数；工序采用多次不同能量高能注入和退火实现P型柱区3的生成，多次高能注入实现浮岛5的限压结构；以硬掩蔽层7为遮挡进行深沟槽8内的场氧化层81的生成，以深沟槽8内的多晶硅层9为屏蔽进行浅沟槽6内硬掩蔽层7的去除，同时在浅沟槽6内的硬掩蔽层7去除时进行时间控制，残 留部分的硬掩蔽层7作为浅沟槽6底部厚氧区。
本发明制备得到的低压超结结构的沟槽MOS器件在承受相同器件击穿耐压的前提下，采用相对普通沟槽MOS器件的外延层2的电阻率规格50％以下，外延层2厚度80％以下，从而获得相对显著优异于常规沟槽MOS 50％及以上的特征导通电阻；采用浓度更浓、厚度更薄的外延来承压，从而降低器件的特征导通电阻。
器件有源区的N型外延层被P型柱区隔离夹断成一个个N型柱区，形成P/N柱(pillar)交替结构，同时采用空间电荷平衡技术高效地实现反向阻断能力。器件外围区采用P型浮岛5和深沟槽8的混合型设计，P型浮岛5提供纵向JTE，深沟槽8截断结曲面，可使器件的击穿电压非常接近理想击穿电压。器件特性相较于SGT技术，具有更宽的安全工作区，更大的过电流能力，更小的Qg及Qrr，特别适合马达控制及过流保护的相关应用。
实施例二
本发明还提供一种低压超结沟槽MOS器件的结构，采用如上述的低压超结沟槽MOS器件的制备方法制备得到，参见图1-11，包括：
第一导电类型的衬底1；
第一导电类型的外延层2，设置于衬底1的上方；
至少一个第二导电类型的柱区3，形成于外延层2的有源区，且每一柱区3按照一第一预设次数注入形成；
第二导电类型的浮岛5，形成于外延层2的外围区，且浮岛5按照一第二预设次数注入形成；
浅沟槽6，形成于每一柱区3的两侧，浅沟槽6的底部设有一预 设厚度的硬掩蔽层7，浅沟槽6的侧壁设有栅氧化层61；
深沟槽8，形成于外延层2的外围区，深沟槽8的底部和侧壁设有场氧化层81；
多晶硅层9，分别设置于浅沟槽6和深沟槽8内；
第二导电类型的体区10，形成于柱区3和浮岛5的上方；
第一导电类型的注入区11，形成于体区10的上方；
介质层12，形成于外延层2的上方；
多个接触孔13，多个接触孔13自介质层12的上表面向下延伸至体区10和靠近有源区的第一个深沟槽8内；
金属层14，覆盖器件的上方。
具体的，采用实施例一中的低压超结沟槽MOS器件的制备方法制备得到的器件的击穿电压为30～200V，其中，器件载体为单晶硅，包含衬底1和外延层2，器件结构主要在外延层2中，具体包括有源区和外围区，有源区为器件功能区，外围区辅助有源区主结耐压；
有源区包括浅沟槽6、P型体区10、P型柱区3，浅沟槽6内具有底部硬掩蔽层7、侧壁栅氧化层61以及多晶硅层9，上述硬掩蔽层7为厚氧结构，，上述栅氧化层61为薄氧结构，P型体区10结合浅沟槽6的侧壁栅氧化层61形成导电沟道，P型柱区3结合浅沟槽6底部的厚氧结构实现元胞区耐压；
外围区以浮岛5区和深沟槽8区，浮岛5区包括P型浮岛5和P型体区10，深沟槽8区至少含有一个深沟槽8，深沟槽8的底部和侧壁具有场氧化层81，该场氧化层81为厚氧结构，浮岛5区和深沟槽8区结合起来进行元胞电场的截止和限压；靠近元胞区第一道深沟槽8限压环采用接触孔13与源极金属层14等电位。
本发明器件特征结合了SGT MOSFET的导通电阻和Planar MOSFET的宽安全工作区，可同时满足开关式电源应用，过流保护应用以及短路能力应用。其优异的特性归因于器件设计理念有别于SGT-MOSFET。SGT-MOSFET凭借缩小横向元件间距(cell pitch)降低外延层2的电阻率来优化特征导通电阻，cell pitch缩小元胞密度增加，散热不易热阻增大，过电流能力锐减，安全工作区狭窄不适合大电流相关应用；而本发明的低压超结结构则是利用纵向结深降低外延电阻率，不需靠缩小cell pitch即可达到目的。
通过说明和附图，给出了具体实施方式的特定结构的典型实施例，基于本发明精神，还可作其他的转换。尽管上述发明提出了现有的较佳实施例，然而，这些内容并不作为局限。
对于本领域的技术人员而言，阅读上述说明后，各种变化和修正无疑将显而易见。因此，所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。在权利要求书范围内任何和所有等价的范围与内容，都应认为仍属本发明的意图和范围内。

Claims (10)

  1. 一种低压超结沟槽MOS器件的制备方法，其特征在于，包括：
    步骤S1，提供一第一导电类型的衬底，并于所述衬底上形成第一导电类型的外延层；
    步骤S2，于所述外延层的有源区进行至少一个第二导电类型的柱区的光刻，每一所述柱区按照一第一预设次数注入形成；
    步骤S3，于所述外延层的外围区进行第二导电类型的浮岛的光刻，所述浮岛按照一第二预设次数注入形成，然后对所述柱区和所述浮岛进行退火；
    步骤S4，于所述外延层的有源区形成浅沟槽，所述浅沟槽位于所述柱区的两侧，且所述浅沟槽的底部设有一预设厚度的硬掩蔽层，所述浅沟槽的侧壁设有栅氧化层；以及
    于所述外延层的外围区形成深沟槽，所述深沟槽的底部和侧壁设有场氧化层，所述浅沟槽和所述深沟槽内形成多晶硅层；
    步骤S5，于所述柱区和所述浮岛的上方进行第二导电类型的体区的自对准注入和退火，然后于所述体区的上方进行第一导电类型的注入区的注入和退火；
    步骤S6，于器件的上方进行介质层的淀积和多个接触孔的刻蚀，多个所述接触孔自所述介质层的上表面向下延伸至所述体区和靠近所述有源区的第一个所述深沟槽内；随后，进行金属层的淀积和刻蚀。
  2. 根据权利要求1所述的一种低压超结沟槽MOS器件的制备方法，其特征在于，所述步骤S4具体包括：
    步骤S41，于所述外延层的有源区进行浅沟槽的刻蚀，所述浅沟槽位于所述柱区的两侧；
    步骤S42，于所述外延层的上方和所述浅沟槽内淀积形成硬掩蔽 层；
    步骤S43，以所述硬掩蔽层为掩蔽，于所述外延层的外围区进行深沟槽的刻蚀，并于所述深沟槽的底部和侧壁生长场氧化层；
    步骤S44，进行第一次多晶硅的淀积，然后进行刻蚀或研磨，去除所述硬掩蔽层上方的多余的所述多晶硅；
    步骤S45，对所述硬掩蔽层进行湿法腐蚀，于所述浅沟槽的槽底残留一预设厚度的所述硬掩蔽层；
    步骤S46，于所述浅沟槽的侧壁进行栅氧化层的生长，然后进行第二次多晶硅的淀积和反刻，使所述多晶硅与所述外延层齐平。
  3. 根据权利要求1所述的一种低压超结沟槽MOS器件的制备方法，其特征在于，所述步骤S2中，于所述外延层的有源区进行至少一个第二导电类型的柱区的光刻，之前还包括：
    于所述外延层的上方形成光阻层。
  4. 根据权利要求1所述的一种低压超结沟槽MOS器件的制备方法，其特征在于，所述步骤S2中，所述第一预设次数为3～6次；
    注入能量为[300KEV，3MEV]。
  5. 根据权利要求1所述的一种低压超结沟槽MOS器件的制备方法，其特征在于，所述步骤S3中，所述第二预设次数为1～4次；
    所述浮岛的注入杂质为B；
    退火温度为1000℃，退火时间为60min。
  6. 根据权利要求1所述的一种低压超结沟槽MOS器件的制备方法，其特征在于，所述步骤S4中，所述浅沟槽的深度为[0.9um，1.8um]。
  7. 根据权利要求2所述的一种低压超结沟槽MOS器件的制备方 法，其特征在于，所述步骤S44中，所述多晶硅层的淀积厚度为[0.8um，1.2um]。
  8. 根据权利要求2所述的一种低压超结沟槽MOS器件的制备方法，其特征在于，所述步骤S45中，所述预设厚度为
    Figure PCTCN2022110909-appb-100001
  9. 根据权利要求1所述的一种低压超结沟槽MOS器件的制备方法，其特征在于，所述步骤S4中，所述栅氧化层的生长厚度为
    Figure PCTCN2022110909-appb-100002
    Figure PCTCN2022110909-appb-100003
  10. 一种低压超结沟槽MOS器件的结构，其特征在于，采用如权利要求1-9任意一项所述的低压超结沟槽MOS器件的制备方法制备得到，包括：
    第一导电类型的衬底；
    第一导电类型的外延层，设置于所述衬底的上方；
    至少一个第二导电类型的柱区，形成于所述外延层的有源区，且每一所述柱区按照一第一预设次数注入形成；
    第二导电类型的浮岛，形成于所述外延层的外围区，且所述浮岛按照一第二预设次数注入形成；
    浅沟槽，形成于每一所述柱区的两侧，所述浅沟槽的底部设有一预设厚度的硬掩蔽层，所述浅沟槽的侧壁设有栅氧化层；
    深沟槽，形成于所述外延层的外围区，所述深沟槽的底部和侧壁设有场氧化层；
    多晶硅层，分别设置于所述浅沟槽和所述深沟槽内；
    第二导电类型的体区，形成于所述柱区和所述浮岛的上方；
    第一导电类型的注入区，形成于所述体区的上方；
    介质层，形成于所述外延层的上方；
    多个接触孔，多个所述接触孔自所述介质层的上表面向下延伸至所述体区和靠近所述有源区的第一个所述深沟槽内；
    金属层，覆盖器件的上方。
PCT/CN2022/110909 2022-08-03 2022-08-08 一种低压超结沟槽mos器件的制备方法及结构 WO2024026904A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210924492.8 2022-08-03
CN202210924492.8A CN115020240B (zh) 2022-08-03 2022-08-03 一种低压超结沟槽mos器件的制备方法及结构

Publications (1)

Publication Number Publication Date
WO2024026904A1 true WO2024026904A1 (zh) 2024-02-08

Family

ID=83065781

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/110909 WO2024026904A1 (zh) 2022-08-03 2022-08-08 一种低压超结沟槽mos器件的制备方法及结构

Country Status (2)

Country Link
CN (1) CN115020240B (zh)
WO (1) WO2024026904A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117080075A (zh) * 2023-08-28 2023-11-17 深圳市美浦森半导体有限公司 一种新型的sgt制作方法及结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102760647A (zh) * 2012-07-26 2012-10-31 上海宏力半导体制造有限公司 超结功率器件制造方法以及半导体器件制造方法
CN102856380A (zh) * 2011-06-27 2013-01-02 力士科技股份有限公司 一种沟槽式金属氧化物半导体场效应管
CN103035673A (zh) * 2011-10-06 2013-04-10 飞兆半导体公司 用于功率半导体装置的边缘终端结构
CN108172609A (zh) * 2017-12-22 2018-06-15 北京世纪金光半导体有限公司 具有周边深沟槽保护环和接地环的碳化硅悬浮结mosfet器件
CN114464667A (zh) * 2021-12-27 2022-05-10 龙腾半导体股份有限公司 一种可优化终端电场的屏蔽栅沟槽mosfet结构及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4907862B2 (ja) * 2004-12-10 2012-04-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4955958B2 (ja) * 2005-08-04 2012-06-20 ルネサスエレクトロニクス株式会社 半導体装置
US7790549B2 (en) * 2008-08-20 2010-09-07 Alpha & Omega Semiconductor, Ltd Configurations and methods for manufacturing charge balanced devices
CN102214689B (zh) * 2010-04-06 2012-11-07 上海华虹Nec电子有限公司 超级结器件的终端保护结构及其制造方法
CN102947928B (zh) * 2010-06-17 2015-04-01 富士电机株式会社 半导体器件及其制造方法
JP2012074441A (ja) * 2010-09-28 2012-04-12 Toshiba Corp 電力用半導体装置
JP6139356B2 (ja) * 2013-09-24 2017-05-31 トヨタ自動車株式会社 半導体装置
CN105895520A (zh) * 2015-01-26 2016-08-24 中航（重庆）微电子有限公司 超结器件制备工艺
US10263070B2 (en) * 2017-06-12 2019-04-16 Alpha And Omega Semiconductor (Cayman) Ltd. Method of manufacturing LV/MV super junction trench power MOSFETs
JP6870546B2 (ja) * 2017-09-14 2021-05-12 株式会社デンソー 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856380A (zh) * 2011-06-27 2013-01-02 力士科技股份有限公司 一种沟槽式金属氧化物半导体场效应管
CN103035673A (zh) * 2011-10-06 2013-04-10 飞兆半导体公司 用于功率半导体装置的边缘终端结构
CN102760647A (zh) * 2012-07-26 2012-10-31 上海宏力半导体制造有限公司 超结功率器件制造方法以及半导体器件制造方法
CN108172609A (zh) * 2017-12-22 2018-06-15 北京世纪金光半导体有限公司 具有周边深沟槽保护环和接地环的碳化硅悬浮结mosfet器件
CN114464667A (zh) * 2021-12-27 2022-05-10 龙腾半导体股份有限公司 一种可优化终端电场的屏蔽栅沟槽mosfet结构及其制造方法

Also Published As

Publication number Publication date
CN115020240B (zh) 2023-03-28
CN115020240A (zh) 2022-09-06

Similar Documents

Publication Publication Date Title
TWI441340B (zh) 無需利用附加遮罩來製造的積體有肖特基二極體的平面ｍｏｓｆｅｔ及其佈局方法
JP4028482B2 (ja) トレンチゲート電極を有するパワーｍｏｓｆｅｔ及びその製造方法
JP3413250B2 (ja) 半導体装置及びその製造方法
US7489011B2 (en) Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics
US10211333B2 (en) Scalable SGT structure with improved FOM
US20150380544A1 (en) Device structure and methods of making high density mosfets for load switch and dc-dc applications
JP2006510198A (ja) 注入されたドレインドリフト領域を有するトレンチｍｏｓｆｅｔおよびこれを製造するための工程
CN108447911B (zh) 一种深浅沟槽半导体功率器件及其制备方法
WO2018082455A1 (zh) 功率器件及其制造方法
CN111081779A (zh) 一种屏蔽栅沟槽式mosfet及其制造方法
CN114937692A (zh) 一种具有沟道二极管的阶梯沟槽栅SiC MOSFET结构及其制备方法
CN116110944A (zh) 一种基于Resurf效应的屏蔽栅沟槽型MOSFET器件及其制备方法
CN113555354A (zh) 一种集成sbd的沟槽终端结构及其制备方法
CN116154000A (zh) 多级沟槽型SiC MOSFET器件及其制造方法
WO2024026904A1 (zh) 一种低压超结沟槽mos器件的制备方法及结构
CN117410344A (zh) 一种π型沟槽栅碳化硅MOSFET器件及其制备方法
CN114068721B (zh) 双梯形槽保护梯形槽碳化硅mosfet器件及制造方法
CN113488389B (zh) 一种沟槽栅双层超结vdmosfet半导体器件及其制备方法
CN116936626A (zh) Igbt器件及其制造方法
CN115458599A (zh) 一种sgt-mosfet元胞及其制造方法和一种电子装置
CN115188812A (zh) 具有分离平面栅结构的金属氧化物半导体场效应晶体管
CN211017082U (zh) 一种超结型mosfet器件
CN113611598A (zh) 一种分裂闸型沟槽半导体功率器件的制备方法
CN112687735A (zh) 一种屏蔽栅功率器件及其制备方法
CN110931548A (zh) 一种半导体器件结构及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22953703

Country of ref document: EP

Kind code of ref document: A1