WO2020181732A1 - 半导体器件及其结边缘区 - Google Patents

半导体器件及其结边缘区 Download PDF

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Publication number
WO2020181732A1
WO2020181732A1 PCT/CN2019/103087 CN2019103087W WO2020181732A1 WO 2020181732 A1 WO2020181732 A1 WO 2020181732A1 CN 2019103087 W CN2019103087 W CN 2019103087W WO 2020181732 A1 WO2020181732 A1 WO 2020181732A1
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region
semiconductor device
grooves
insulating medium
junction edge
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PCT/CN2019/103087
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English (en)
French (fr)
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杜文芳
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南京芯舟科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

Definitions

  • This application relates to semiconductor devices, especially semiconductor devices and junction edge regions related to high voltage and/or power devices.
  • the junction edge area of the device Between the cell area of the power semiconductor device (the cell area is also called the active area) and the dicing groove is the junction edge area of the device (the junction edge is also called the junction terminal).
  • the junction edge area When the device has an applied voltage, the junction edge area will withstand all the applied voltage. Therefore, the withstand voltage characteristics of the junction edge area affect the withstand voltage characteristics of the device.
  • the structure of the junction edge is also diverse.
  • the commonly used junction edge currently adopts the field limiting ring (FLR) technology.
  • the field limiting ring is to form one or more rings with the same doping around it while diffusing to form the PN main junction, so that the applied voltage is distributed to the main junction and the PN junction formed by the ring and the substrate, reducing the surface of the main junction.
  • the electric field is concentrated to increase the breakdown voltage of the device.
  • the design requirements for the size and doping of the field limiting loop have become more stringent.
  • the main influencing factors include the doping concentration of the substrate, the junction depth of the field limiting ring, the window size of the field limiting ring, the distance between the ring and the ring, and the surface charge... and many more.
  • the strong electric field on the surface severely limits the robustness and reliability of the device.
  • the purpose of this application is to provide a semiconductor device and its junction edge region to reduce the influence of surface charges on the breakdown voltage.
  • the junction edge region includes more than one ring unit, and the ring unit includes: a semiconductor substrate of a first conductivity type; and a plurality of grooves arranged in the semiconductor On one side of the substrate, a conductive material is arranged inside the plurality of grooves, and the conductive material is isolated from the semiconductor substrate by a first insulating medium; a plurality of floating regions of the second conductivity type are adjacent to the The first insulating medium is correspondingly disposed at the bottom of the plurality of grooves; the second insulating medium is disposed on the surface of the semiconductor substrate to cover, abut or be adjacent to the first insulating medium.
  • the conductive material includes polysilicon.
  • the first insulating medium includes silicon dioxide.
  • the conductive material is replaced with the first insulating medium.
  • it further includes a first metal layer
  • the second insulating medium is provided with openings at the notches of the plurality of grooves
  • the first metal layer is provided on the second insulating medium. And contact with the conductive material through the opening, and are isolated from the semiconductor substrate by the second insulating medium.
  • it further includes at least one upper region of the second conductivity type, and the at least one upper region is disposed in a part or all of the groove intervals of the plurality of grooves.
  • the at least one upper region is isolated from the conductive material by the first insulating medium.
  • the at least one upper region is arranged adjacent to or adjacent to the notches of the plurality of grooves.
  • the plurality of grooves include two boundary grooves, and the at least one upper region is selectively disposed outside at least one of the two boundary grooves.
  • it further includes a first metal layer, and the first metal layer is disposed on the second insulating medium.
  • the second insulating medium is provided with openings at the notches of the plurality of grooves, and the first metal layer contacts the conductive material through the openings.
  • an opening is provided on the second insulating medium, and the first metal layer is in contact with a part or all of the at least one upper region through the opening.
  • the at least one upper region includes a sub-doped region.
  • the secondary doped region is a heavily doped region or a lightly doped region.
  • the sub-doped region and the at least one upper region have the same or different conductivity types.
  • the second metal layer is provided at the bottom of the semiconductor device, and a doped region is provided between the semiconductor substrate and the second metal layer.
  • the doped region is of the first conductivity type or the second conductivity type.
  • the doped region is a composite structure, and the composite structure includes a first region and a second region of different conductivity types.
  • the first area and the second area are in a stacked configuration or adjacent to each other in the same layer.
  • the first conductivity type is N type and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.
  • the number of the plurality of grooves is 2, 3, or 4, but it is not limited thereto.
  • a semiconductor device includes an active region and a junction edge region, wherein the junction edge region includes more than one ring unit, and the ring unit includes: an N-type semiconductor substrate; A groove is arranged on one side of the N-type semiconductor substrate, and polysilicon is arranged inside the plurality of grooves. The polysilicon is isolated from the N-type semiconductor substrate by a first insulating medium.
  • Each groove includes two boundary grooves; a plurality of P-type floating regions, adjacent to the first insulating medium and correspondingly arranged at the bottom of the plurality of grooves; at least one P-type upper region, arranged in the plurality of grooves Part or all of the groove interval and the outer side of the two boundary grooves; a second insulating medium arranged on the surface of the semiconductor substrate with openings; and a first metal layer arranged on the second insulating medium Above, the first metal layer is in contact with a part or all of the at least one P-type upper region through the opening, and the first metal layer is in contact with the polysilicon through the opening, or the The first metal layer is isolated from the polysilicon by the second insulating medium.
  • FIG. 1 is a schematic diagram of an exemplary semiconductor device structure
  • FIG. 2 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the application.
  • FIG. 3 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of a semiconductor device according to an embodiment of the application.
  • 5a and 5b are schematic diagrams of the configuration of the upper area of an embodiment of the application.
  • 6a to 6c are schematic diagrams of the configuration of the upper area outside the boundary groove of the embodiment of the application.
  • FIG. 7a to FIG. 7e are schematic diagrams of the configuration of the metal layer according to the embodiment of the application.
  • FIG. 8 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the application.
  • 9a and 9b are schematic diagrams of the doped region structure of the composite structure according to the embodiment of the application.
  • FIG. 1 is a schematic diagram of the structure of an exemplary semiconductor device.
  • the semiconductor device includes a semiconductor substrate 001 of a first conductivity type (N-type), and a doped region 002 is provided at the bottom thereof, the doped region 002 contacts a second metal layer 300, and the second metal layer 300 serves as a first electrode .
  • the semiconductor device includes an active area (the structure is only shown briefly, but not limited to this, and may be a diode, MOSFET, IGBT, or thyristor) and its peripheral junction edge area.
  • the active area includes a semiconductor substrate 001 and a second conductivity type (P-type) metal contact area 200, the metal contact area 200 is in contact with a metal layer 500, the metal layer 500 serves as a second electrode, and the semiconductor substrate 001 A PN-Main-Junction 901 is formed with the metal contact area 200.
  • the structure of the junction edge area adopts a field limiting ring (Field Limiting Ring, FLR for short) technology.
  • the first conductivity type is N type and the second conductivity type is P type as an example here, the first conductivity type is P type and the second conductivity type is N type is also applicable.
  • the field limiting ring 202 is diffused to form the PN main junction, while one or more field limiting rings 202 doped around the PN main junction are made to distribute the applied voltage to the PN main junction and the field limit.
  • the electric field concentration on the surface of the PN main junction is reduced, and the breakdown voltage of the semiconductor device is improved.
  • a metal (or polysilicon) field plate (the first metal layer 501 described later) is provided in the junction edge area to reduce the influence of surface charges, when the device is subjected to withstand voltage, the junction edge Only the PN junction formed by the field limiting ring 202 and the semiconductor substrate 001 bears the withstand voltage, and the electric field is almost concentrated on the bottom of the field limiting ring 202, which will cause the local electric field to be too high, causing the semiconductor device to form a breakdown in the junction edge region.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • FIG. 2 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the application.
  • the junction edge region of the semiconductor device includes more than one ring unit 100, and the ring unit 100 includes: a semiconductor substrate 001 of the first conductivity type; a plurality of grooves 110 arranged on one side of the semiconductor substrate 001, A conductive material 111 is provided in the plurality of grooves, and the conductive material 111 is isolated from the semiconductor substrate 001 by a first insulating medium 112; a plurality of floating regions 101 of the second conductivity type are adjacent to the first
  • the insulating medium 112 is correspondingly disposed (or closely attached) to the bottom of the plurality of grooves 110; the second insulating medium 016 is disposed on the surface of the semiconductor substrate 001 to cover, abut or be adjacent to the first insulating medium 112.
  • the conductive material 111 includes polysilicon.
  • the first insulating medium 112 includes silicon dioxide, benzocyclobutene (BCB) or polyimide (PI).
  • the second insulating medium 016 includes silicon dioxide or a composite layer of silicon dioxide and other substances, such as a composite layer of silicon dioxide and silicon nitride, silicon dioxide and polyimide ( PI) composite layer...etc.
  • the semiconductor substrate 001 and the metal contact area 200 all are partially exhausted.
  • V app a positive voltage difference
  • the depletion region in the semiconductor substrate 001 will sequentially reach the first ring unit 100a, the second ring unit 100b, and the third ring unit 100c from left to right.
  • the floating area 101 at the bottom of each groove 110 will also be partially depleted, and the partially depleted floating area 101 and the partially depleted semiconductor substrate 001 of each ring unit 100 will bear part of the V app value.
  • each ring unit 100 and the semiconductor substrate 001 is at the bottom of the groove 110 far away from the upper surface of the semiconductor substrate 001, thus avoiding the presence of a strong electric field on the upper surface of the semiconductor substrate 001, and improving The effect of surface charge on withstand voltage and device reliability and robustness.
  • each ring unit 100 has multiple floating areas 101, which can improve the withstand voltage of each ring unit 100.
  • FIG. 3 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the application.
  • the conductive material 111 can be replaced with the first insulating medium 112, that is, the first insulating medium 112 is filled in the plurality of grooves 110.
  • FIG. 4 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the application.
  • it further includes a first metal layer 501
  • the second insulating medium 016 is provided with openings at the notches of the plurality of grooves 110
  • the first metal layer 501 is provided on the The second insulating medium 016 is in contact with the conductive material 111 through the opening, and is isolated from the semiconductor substrate 001 by the second insulating medium 016.
  • the electric field distribution at the edge of the junction can be adjusted to further improve the withstand voltage characteristics of the device.
  • Figures 5a and 5b are schematic diagrams of the configuration of the upper area of an embodiment of the application. In some embodiments, it further includes at least one upper region 202 of the second conductivity type, and the at least one upper region 202 is disposed in a part or all of the groove intervals of the plurality of grooves 110.
  • the first ring unit 100a has two grooves, and an upper region 202 is provided in the groove interval between the two grooves.
  • the second ring unit 100b has three grooves, and two upper regions 202 are arranged between the two grooves.
  • the third ring unit 100c has four grooves, and three upper regions 202 are arranged between the three grooves.
  • the analogy is not limited to the illustrations and examples.
  • the second ring unit 100b has three grooves, and an upper region 202 is selectively provided in the interval between the two grooves.
  • the third ring unit 100c has four grooves, and one upper zone 202 or two upper zones 202 are selectively provided in the three groove intervals.
  • the analogy is not limited to the illustrations and examples.
  • 6a to 6c are schematic diagrams of the configuration of the upper area outside the boundary groove of the embodiment of the application.
  • the plurality of grooves includes two boundary grooves, and the at least one upper region is selectively disposed outside at least one of the two boundary grooves.
  • the outer sides of the two outermost boundary grooves of the ring unit 100 are both provided with upper regions.
  • the outer side of the leftmost left boundary groove of the ring unit 100 is provided with an upper area.
  • the outer side of the right boundary groove on the rightmost side of the ring unit 100 is provided with an upper area.
  • each ring unit 100 can be determined according to the functions and requirements of the semiconductor device, and is not limited to the number and arrangement of 2, 3, and 4 described above.
  • the plurality of grooves are the aforementioned two boundary grooves.
  • the at least one upper region 202 is isolated from the conductive material 111 by the first insulating medium 112.
  • the at least one upper region 202 is located adjacent to or adjacent to the notches of the plurality of grooves 110.
  • the at least one upper region 202 can be exposed on the surface of the semiconductor substrate 001 to be adjacent to the notch, or buried in the semiconductor substrate 001 and adjacent to the notch.
  • the semiconductor substrate 001 when a positive voltage difference V app is applied between the first electrode (ie, the second metal layer 300) and the second electrode (ie, the metal layer 500), the semiconductor substrate 001 is in contact with the metal Area 200 is partially exhausted. As the value of V app increases, the depletion region in the semiconductor substrate 001 will sequentially reach the first ring unit 100a, the second ring unit 100b, and the third ring unit 100c from left to right. At this time, the floating area 101 and the upper area 202 at the bottom of each tank 110 will also be partially depleted.
  • the PN junction formed by the floating region 101 and the upper region 202 with the semiconductor substrate 001, respectively, will share the V app value of the bearing part, and according to the number and position of the upper region 202, the electric field distribution at the junction edge and the breakdown voltage can be adjusted The vertical pressure and horizontal pressure.
  • FIG. 7a to FIG. 7e are schematic diagrams of the configuration of the metal layer according to the embodiment of the application.
  • it further includes a first metal layer 501, and the first metal layer 501 is disposed on the second insulating medium 016.
  • the second insulating medium 016 is provided with openings at the notches of the plurality of grooves 110, and the first metal layer 501 passes through the openings and The conductive material 111 is in contact, and is selectively isolated from the upper region 202 by the second insulating medium 501.
  • the second insulating medium 016 is provided with openings at the notches of the plurality of grooves 110, and the first metal layer 501 is in contact with the conductive material 111 through the openings , And is isolated from the conductive material 111 by the second insulating medium 016.
  • the floating region 101 and the upper region 202 respectively form a PN junction with the semiconductor substrate 001, which will share the V app value of the bearing part, and at the same time, the first metal layer 501 reduces the influence of the surface charge.
  • an opening is provided on the second insulating medium 016, and the first metal layer 501 is connected to part or all of the at least one through the opening.
  • An upper region 202 is in contact.
  • the first metal layer 501 is in contact with the upper region 202 in the groove interval, but is isolated from the conductive material 111 to form a structure, function, and PN The similar ring structure of the main knot.
  • the conductive material 111 and the upper region 202 in the groove interval are electrically coupled through the first metal layer 501, so the conductive material 111 and the The upper region 202 has the same potential.
  • the upper region 202 and the floating region 101 are respectively close to the first insulating medium 112 in the groove.
  • the contact area between the bottom of the floating region 101 and the semiconductor substrate 001 is relatively large, so a relatively large radius of curvature can be obtained to achieve a relatively low electric field peak value under the same V app .
  • the conductive material 111 is electrically coupled to all the upper regions 202 through the first metal layer 501.
  • the at least one upper region 202 includes a sub-doped region 203.
  • the secondary doped region 203 is a heavily doped region or a lightly doped region.
  • the sub-doped region 203 and the upper region are of the same or different conductivity types.
  • the sub-doped region 203 is selectively formed in a part or all of the at least one upper region 202.
  • the second metal layer 300 is disposed at the bottom of the semiconductor device, and a doped region 002 is disposed between the semiconductor substrate 001 and the second metal layer 300.
  • the doped region 002 is of the first conductivity type or the second conductivity type.
  • the doped region 002 and the semiconductor substrate 001 have the same first conductivity type, but the doping concentration is different.
  • Fig. 8 is a schematic diagram showing the structure of a semiconductor device according to an embodiment of the present application. The difference from Fig. 2 is that the doped region 002 is of the second conductivity type. Similarly, it is also applicable to the doped region 002 in FIGS. 3 to 7e.
  • FIGS. 9a and 9b are schematic diagrams of the doped region structure of the composite structure according to the embodiment of the application.
  • the doped region is a composite structure, and the composite structure includes a first region and a second region of different conductivity types.
  • the first area and the second area are in a stacked configuration, for example, the first area is an N-type area 004, and the second area is a P-type area 003.
  • An N-type region 004 is included between the N-type semiconductor substrate 001 and the P-type region 003 to form a junction edge structure of a field-stop bipolar device.
  • the first area and the second area are adjacent to each other in the same layer.
  • the first area is an N+ type area 002
  • the second area is a P type area 003.
  • the lower surface of the N-type semiconductor substrate 001 is not only in contact with the N+-type region 002 but also with the P-type region 003, and both the N+-type region 002 and the P-type region 003 are in contact with the second metal layer 300.
  • the junction edge structure of the bipolar device with the anode short-circuited is formed.
  • a semiconductor device includes an active region and a junction edge region.
  • the feature is that the junction edge region includes more than one ring unit 100, and
  • the ring unit 100 includes: an N-type semiconductor substrate 001; a plurality of grooves 110 are arranged on one side of the N-type semiconductor substrate 001, and polysilicon (that is, the aforementioned conductive material 111) is arranged inside the plurality of grooves 110, The polysilicon is isolated from the N-type semiconductor substrate 001 by a first insulating medium 112.
  • the plurality of grooves 110 include two boundary grooves; and a plurality of P-type floating regions 101 are adjacent to the first insulating medium.
  • the dielectric 016 is disposed on the surface of the N-type semiconductor substrate 001 and is provided with an opening; and, the first metal layer 501 is disposed on the second insulating dielectric 016, and the first metal layer 501 passes through the opening And part or all of the at least one P-type upper region 202 is in contact, and the first metal layer 501 is in contact with the polysilicon through the opening, or the first metal layer 501 is in contact with the second
  • the insulating medium 016 is isolated from the polysilicon.
  • the first conductivity type is different from the second conductivity type.
  • the first conductivity type is P-type and the second conductivity type is N-type; or, the first conductivity type is N-type and the second conductivity type is It is P-type, that is, the N-type and P-type in the above description can be interchanged, and the corresponding electrons and holes can also be interchanged. After the interchange, the principles of this application still apply.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

Abstract

本申请是一种半导体器件及其结边缘区，所述结边缘区包括一个以上的环单元，所述环单元包括半导体衬底，所述半导体衬底上设置多个槽，每一槽底对应设置与所述半导体衬底相异导电类型的浮空区。所述多个槽内部设置导电材料，通过第一绝缘介质而与所述半导体衬底及所述浮空区相隔离。所述半导体衬底表面设置第二绝缘介质，其覆盖、邻接或邻近所述第一绝缘介质。

Description

半导体器件及其结边缘区 技术领域
本申请涉及半导体器件，特别是关于高压和/或功率器件的半导体器件及结边缘区。
背景技术
功率半导体器件的元胞区(元胞区也称有源区)和划片槽之间是器件的结边缘区(结边缘也称结终端)。当器件有外加电压时，结边缘区将承受全部外加电压，因此，结边缘区的耐压特性影响了器件的耐压特性。根据器件击穿电压等级的不同，结边缘的结构也有多种多样，目前普遍采用的结边缘是采用场限环(Field Limiting Ring，简称FLR)的技术。场限环是在扩散形成PN主结的同时，在其周围做同样掺杂的一个或多个环，使得外加电压分配到主结和环与衬底构成的PN结上，降低主结表面的电场集中，提高器件的击穿电压。
技术问题
随着器件耐压等级的提高，场限环的尺寸和掺杂的设计要求也愈加严苛。影响结边缘区耐压的因素多种多样，其主要的影响因素包括衬底的掺杂浓度、场限环的结深、场限环的窗口尺寸、环与环之间的间距以及表面电荷…等等。特别是表面存在的强电场使得器件鲁棒性与可靠性严重受限，同时在器件制造的过程中极容易引入表面电荷，这些电荷的存在改变了结边缘的电场分布而导致击穿电压的改变，使得器件的可靠性和一致性降低。
发明内容
技术解决方案
为了解决上述技术问题，本申请的目的在于，提供一种半导体器件及其结边缘区，以降低表面电荷对击穿电压的影响。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。
依据本申请提出的一种半导体器件的结边缘区，所述结边缘区包括一个以上的环单元，所述环单元包括：第一导电类型的半导体衬底；多个槽，设置于所述半导体衬底的一侧，所述多个槽的内部设置有导电材料，所述导电材料通过第一绝缘介质而与所述半导体衬底相隔离；第二导电类型的多个浮空区，邻接所述第一绝缘介质而对应设置于所述多个槽的底部；第二绝缘介质，设置于所述半导体衬底的表面，以覆盖、邻接或邻近所述第一绝缘介质。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，所述导电材料包括多晶硅。
在本申请的一实施例中，所述第一绝缘介质包括二氧化硅。
在本申请的一实施例中，所述导电材料替換为所述第一绝缘介质。
在本申请的一实施例中，还包括第一金属层，所述第二绝缘介质在所述多个槽的槽口处设置有开口，所述第一金属层设置于所述第二绝缘介质上，且通过所述开口与所述导电材料相接触，并通过所述第二绝缘介质而与所述半导体衬底相隔离。
在本申请的一实施例中，还包括第二导电类型的至少一个上部区，所述至少一个上部区设置于所述多个槽的局部或全部的槽间隔中。
在本申请的一实施例中，所述至少一个上部区通过所述第一绝缘介质而与所述导电材料相隔离。
在本申请的一实施例中，所述至少一个上部区设置位置邻近或邻接所述多个槽的槽口。
在本申请的一实施例中，所述多个槽包括两个边界槽，所述至少一个上部区选择性的设置于所述两个边界槽中至少其一的外侧。
在本申请的一实施例中，还包括第一金属层，所述第一金属层设置于所述第二绝缘介质上。
在本申请的一实施例中，所述第二绝缘介质在所述多个槽的槽口处设置有开口，所述第一金属层通过所述开口与所述导电材料相接触。
在本申请的一实施例中，所述第二绝缘介质上设置有开口，所述第一金属层通过所述开口而与局部或全部的所述至少一个上部区相接触。
在本申请的一实施例中，所述至少一个上部区包括次掺杂区。
在本申请的一实施例中，所述次掺杂区为重掺杂区或轻掺杂区。
在本申请的一实施例中，所述次掺杂区与所述至少一个上部区为相同或相异的导电类型。
在本申请的一实施例中，第二金属层设置于所述半导体器件底部，所述半导体衬底与所述第二金属层之间设置有掺杂区域。
在本申请的一实施例中，所述掺杂区域为第一导电类型或第二导电类型。
在本申请的一实施例中，所述掺杂区域为复合结构，所述复合结构包括相异导电类型的第一区域与第二区域。
在本申请的一实施例中，所述第一区域与所述第二区域为叠层配置或同层邻接配置。
在本申请的一实施例中，所述第一导电类型为N型，所述第二导电类型为P型；或者，所述第一导电类型为P型，所述第二导电类型为N型
在本申请的一实施例中，所述多个槽的数量为2、3或4，但不以此为限。
本申请的另一目的的一种半导体器件，包括有源区与结边缘区，其特征在于，所述结边缘区包括一个以上的环单元，所述环单元包括：N型半导体衬底；多个槽，设置于所述N型半导体衬底的一侧，所述多个槽的内部设置有多晶硅，所述多晶硅通过第一绝缘介质而与所述N型半导体衬底相隔 离，所述多个槽包括两个边界槽；P型多个浮空区，邻接所述第一绝缘介质而对应设置于所述多个槽的底部；至少一个P型上部区，设置于所述多个槽的局部或全部的槽间隔及所述两个边界槽的外侧；第二绝缘介质，设置于所述半导体衬底的表面，设置有开口；以及，第一金属层，设置于所述第二绝缘介质上，所述第一金属层通过所述开口而与局部或全部的所述至少一个P型上部区相接触，及所述第一金属层通过所述开口与所述多晶硅相接触，或所述第一金属层通过所述第二绝缘介质与所述多晶硅相隔离。
有益效果
本申请较能在有源区施加电压而产生部分耗尽时，通过多个深沟槽结合其底部的终止区配合此部分耗尽，且承受部分电压，较能有效降低表面电荷对击穿电压的影响。
附图说明
为了能更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为范例性半导体器件结构示意图；
图2为本申请实施例的半导体器件结构示意图；
图3为本申请实施例的半导体器件结构示意图；
图4为本申请实施例的半导体器件结构示意图；
图5a与图5b为本申请实施例的上部区配置示意图；
图6a至图6c为本申请实施例边界槽外侧配置上部区示意图；
图7a至图7e为本申请实施例配置金属层示意图；
图8为本申请实施例的半导体器件结构示意图；
图9a与图9b为本申请实施例复合结构的掺杂区域结构示意图。
具体实施方式
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本申请具体实施例，其不应被视为限制本申请未在此详述的其它具体实施例。
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
本申请的说明书和权利要求书以及上述附图中的述语“第一”、“第二”、“第三”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情 形下可以互换。此外，术语“包括”和“具有”以及他譬的变形，意图在于覆盖不排他的包含。
本申请说明书中使用的术语仅用来描述特定实施方式，而并不意图显示本申请的概念。除非上下文中有明确不同的意义，否则，以单数形式使用的表达涵盖具有多个的形式的表达。在本申请说明书中，应理解，诸如“包括”、“具有”以及“含有”等术语意图说明存在本申请说明书中揭示的特征、数字、步骤、动作或其组合的可能性，而并不意图排除可存在或可添加一个或多个其他特征、数字、步骤、动作或其组合的可能性。附图中的相同参考标号指代相同部分。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰、理解和便于描述，夸大设备、系统、组件、电路的配置范围。将理解的是，当组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体实施例，对依据本申请提出的一种半导体器件及其结边缘区，其具体实施方式、结构、特征及其功效，详细说明如后。
图1为范例性半导体器件结构示意图。半导体器件包括第一导电类型(N型)的半导体衬底001，其底部设置有掺杂区域002，所述掺杂区域002接触第二金属层300，所述第二金属层300作为第一电极。所述半导体器件包括有源区(结构仅简示，但不以此为限，可以是二极管或MOSFET或IGBT或晶闸管)与其外围的结边缘区。所述有源区包括半导体衬底001与第二导电类型(P型)的金属接触区200，金属接触区200与金属层500相接触，所述金属层500作为第二电极，半导体衬底001与金属接触区200用以形成的PN主结(PN-Main-Junction)901。所述结边缘区的结构采用场限环(Field Limiting Ring，简称FLR)的技术。此处虽以第一导电类型为N型，第二导电类型为P型为例，但第一导电类型为P型，第二导电类型为N型亦适用。
如图1所示，场限环202是在扩散形成PN主结的同时，在PN主结周围做同样掺杂的一个或多个场限环202，使得外加电压分配到PN主结和场限环202与半导体衬底001构成的PN结上，降低PN主结表面的电场集中，提高半导体器件针对击穿电压的耐压程度。但在半导体器件制造的过程中极容易引入表面电荷，这些电荷的存在改变了结边缘的电场分布而导致击穿电压的改变，使得半导体器件的可靠性和一致性降低。
虽然，在结边缘区设置金属(或多晶硅)场板(Field Plate)(结构相同或相类似后述的第一金属层501)可以降低表面电荷的影响，但器件在承受耐压时，结边缘区只有场限环202和半导体衬底001形成的PN结承受耐压，电场几乎集中于场限环202的底部，这样会使局部电场过高，导致半导体器件在结边缘区形成击穿。
以下各实施例，请参考图1以利于理解有关范例性的半导体器件结构。同时为方便说明，以下暂以第一导电类型为N型，第二导电类型为P型进行说明。
图2为本申请一实施例的半导体器件结构示意图。在本申请一实施例中。半导体器件的结边缘区包括一个以上的环单元100，所述环单元100包括：第一导电类型的半导体衬底001；多个槽110，设置于所述半导体衬底001的一侧，所述多个槽的内部设置有导电材料111，所述导电材料111通过第一绝缘介质112而与所述半导体衬底001相隔离；第二导电类型的多个浮空区101，邻接所述第一绝缘介质112而对应设置(或紧贴)于所述多个槽110的底部；第二绝缘介质016，设置于所述半导体衬底001的表面，以覆盖、邻接或邻近所述第一绝缘介质112。
在本申请的一实施例中，所述导电材料111包括多晶硅。
在本申请的一实施例中，所述第一绝缘介质112包括二氧化硅或苯环丁烯(BCB)或聚酰亚胺(PI)。
在本申请的一实施例中，所述第二绝缘介质016包括二氧化硅或其与其它物质的复合层，例如二氧化硅与氮化硅的复合层、二氧化硅与聚酰亚胺(PI)的复合层…等。
在本申请的一实施例中，当第一电极(第二金属层300)与第二电极(金属层500)之间加有正的电压差V app时，半导体衬底001与金属接触区200均有部分耗尽。随着V app的值增加，半导体衬底001内的耗尽区将从左往右依次到达第一个环单元100a、第二个环单元100b、第三个环单元100c。此时，每个槽110底部的浮空区101也将部分耗尽，每个环单元100的部分耗尽的浮空区101与部分耗尽的半导体衬底001将承受部分的V app值。
在本申请的一实施例中，各个环单元100与半导体衬底001的耐压区在远离半导体衬底001上表面的槽110底部，因此避免了半导体衬底001上表面存在强电场，改善了表面电荷对耐压的影响以及器件可靠性与鲁棒性。同时每个环单元100具备多个浮空区101，较能提升每个环单元100承受的耐压值。
图3为本申请一实施例的半导体器件结构示意图。在本申请的一实施例中，所述导电材料111可改用所述第一绝缘介质112，即所述多个槽110中皆填满所述第一绝缘介质112。
图4为本申请一实施例的半导体器件结构示意图。在本申请的一实施例中，还包括第一金属层501，所述第二绝缘介质016在所述多个槽110的槽口处设置有开口，所述第一金属层501设置于所述第二绝缘介质016上，且通过所述开口与所述导电材料111相接触，并通过所述第二绝缘介质016 而与所述半导体衬底001相隔离。通过所述第一金属层501上重新分布的电荷，可以调节结边缘的电场分布，进一步改善器件的耐压特性。
图5a与图5b为本申请实施例的上部区配置示意图。在一些实施例中，还包括第二导电类型的至少一个上部区202，所述至少一个上部区202设置于所述多个槽110的局部或全部的槽间隔中。
如图5a所绘示，第一个环单元100a具有两个槽，两个槽的槽间隔中设置有一个上部区202。第二个环单元100b具有三个槽，两个槽间隔之间设置有二个上部区202。第三个环单元100c具有四个槽，三个槽间隔之间设置有三个上部区202。以此类推，并不以图示及示例为限。
如图5b所绘示，第二个环单元100b具有三个槽，两个槽间隔中选择性的设置一个上部区202。第三个环单元100c具有四个槽，三个槽间隔中选择性的设置一个上部区202或两个上部区202。以此类推，并不以图示及示例为限。
图6a至图6c为本申请实施例边界槽外侧配置上部区示意图。在一些实施例中，所述多个槽包括两个边界槽，所述至少一个上部区选择性的设置于所述两个边界槽中至少其一的外侧。
如图6a所绘示，环单元100的最外侧的两边界槽的外侧皆设有上部区。
如图6b所绘示，环单元100的最左侧的左边界槽的外侧设有上部区。
如图6c所绘示，环单元100的最右侧的右边界槽的外侧设有上部区。
上述的左与右是以图示为例，亦可依据位置或轴向而采用上与下、内与外…此等同义性说明，不以此为限。而且，每一环单元100的槽数量可依据半导体器件的功能与需求而定，不以前述2、3、4个的数量与排列方式为限。此外，所述多个槽的数量为2时，所述多个槽即为前述的两个边界槽。
如图5a至图6c，在本申请的一实施例中，所述至少一个上部区202通过所述第一绝缘介质112而与所述导电材料111相隔离。
如图5a至图6c，在本申请的一实施例中，所述至少一个上部区202设置位置邻近或邻接所述多个槽110的槽口。也就是说，所述至少一个上部区202可设置显露于所述半导体衬底001的表面以邻接槽口，或是设置于埋于所述半导体衬底001之中而邻近槽口。
在本申请的一实施例中，当第一电极(即第二金属层300)与第二电极(即金属层500)之间加有正的电压差V app时，半导体衬底001与金属接触区200均有部分耗尽。随着V app的值增加，半导体衬底001内的耗尽区将从左往右依次到达第一个环单元100a、第二个环单元100b、第三个环单元100c。此时，每个槽110底部的浮空区101与上部区202也会有部分耗尽。浮空区101与上部区202分别与半导体衬底001形成的PN结，将分担承受部分的V app值，而且依据上部区202的数量与位置，可以调节结边缘的电场分布，以及击穿电压的垂直压及水平压。
图7a至图7e为本申请实施例配置金属层示意图。在一些实施例中，还包括第一金属层501，所 述第一金属层501设置于所述第二绝缘介质016上。
如图7a所绘示，在本申请的一实施例中，所述第二绝缘介质016在所述多个槽110的槽口处设置有开口，所述第一金属层501通过所述开口与所述导电材料111相接触，且选择性的通过所述第二绝缘介质501与所述上部区202相隔离。
在本申请的一实施例中，所述第二绝缘介质016在所述多个槽110的槽口处设置有开口，所述第一金属层501通过所述开口与所述导电材料111相接触，并通过所述第二绝缘介质016与所述导电材料111相隔离。浮空区101与上部区202分别与半导体衬底001形成的PN结，将分担承受部分的V app值，同时通过所述第一金属层501降低表面电荷对的影响。
如图7b至图7e所示，在本申请的一实施例中，所述第二绝缘介质016上设置有开口，所述第一金属层501通过所述开口而与局部或全部的所述至少一个上部区202相接触。
如图7b所绘示，在本申请的一实施例中，所述第一金属层501与槽间隔中所述上部区202接触，但与所述导电材料111相隔离，形成结构、功能与PN主结的相近似的环结构。
如图7c所绘示，在本申请的一实施例中，导电材料111及槽间隔中所述上部区202，通过所述第一金属层501形成电性耦接，因此导电材料111与所述上部区202具有相同的电位。又由于所述上部区202与所述浮空区101各自紧贴槽内的第一绝缘介质112。此外，所述浮空区101底部与半导体衬底001的接触面积较大，故能获得较大的曲率半径，以在相同的V app下取得相对较低的电场峰值。
如图7d所绘示，在本申请的一实施例中，导电材料111是通过所述第一金属层501电性耦接全部所述上部区202。
如图7e所绘示，在本申请的一实施例中，在本申请的一实施例中，所述至少一个上部区202包括次掺杂区203。
在本申请的一实施例中，所述次掺杂区203为重掺杂区或轻掺杂区。
在本申请的一实施例中，所述次掺杂区203与所述上部区为相同或相异的导电类型。
在本申请的一实施例中，所述次掺杂区203选择性的形成于局部或全部的所述至少一个上部区202。
在本申请的一实施例中，第二金属层300设置于所述半导体器件底部，所述半导体衬底001与所述第二金属层300之间设置有掺杂区域002。
在本申请的一实施例中，所述掺杂区域002为第一导电类型或第二导电类型。
如图2至图7e所示，所述掺杂区域002与所述半导体衬底001同为第一导电类型，但掺杂浓度不同。
如图8绘示本申请一实施例的半导体器件结构示意图，与图2不同在于，所述掺杂区域002为第 二导电类型。相类似的，亦适用于图3至图7e中所述掺杂区域002。
图9a与图9b为本申请实施例复合结构的掺杂区域结构示意图。所述掺杂区域为复合结构，所述复合结构包括相异导电类型的第一区域与第二区域。
如图9a所示，在本申请的一实施例中，所述第一区域与所述第二区域为叠层配置，例如第一区域为N型区域004，第二区域为P型区域003。在N型半导体衬底001与P型区域003之间包含一个N型区域004，从而形成场截止型的双极型器件的结边缘结构。
如图9b所示，在本申请的一实施例中，所述第一区域与所述第二区域为同层邻接配置，例如第一区域为N+型区域002，第二区域为P型区域003。N型半导体衬底001的下表面不仅与N+型区域002相接触，还与P型区域003相接触，N+型区域002与P型区域003都与第二金属层300相接触。从而形成阳极短路的双极型器件的结边缘结构。
如图7b至图7e所示，在本申请的一实施例，一种半导体器件，包括有源区与结边缘区，其特征在于，所述结边缘区包括一个以上的环单元100，所述环单元100包括：N型半导体衬底001；多个槽110，设置于所述N型半导体衬底001的一侧，所述多个槽110的内部设置有多晶硅(即前述导电材料111)，所述多晶硅通过第一绝缘介质112而与所述N型半导体衬底001相隔离，所述多个槽110包括两个边界槽；P型多个浮空区101，邻接所述第一绝缘介质112而对应设置于所述多个槽110的底部；至少一个P型上部区202，设置于所述多个槽110的局部或全部的槽间隔及所述两个边界槽的外侧；第二绝缘介质016，设置于所述N型半导体衬底001的表面并设置有开口；以及，第一金属层501，设置于所述第二绝缘介质016上，所述第一金属层501通过所述开口而与局部或全部的所述至少一个P型上部区202相接触，及所述第一金属层501通过所述开口与所述多晶硅相接触，或所述第一金属层501通过所述第二绝缘介质016与所述多晶硅相隔离。
本申请较能在有源区施加电压而产生部分耗尽时，通过多个深沟槽结合其底部的终止区配合此部分耗尽，且承受部分电压，较能有效降低表面电荷对击穿电压的影响。
如先前所述，第一导电类型与第二导电类型为相异，例如：第一导电类型为P型，第二导电类型为N型；或者，第一导电类型为N型，第二导电类型为P型，即以上描述中的N型和P型可以互换，对应的电子和空穴也可以互换，互换之后仍然适用本申请的原理。
“在本申请的一实施例中”及“在各种实施例中”等用语被重复地使用。此用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术 方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。
工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (20)

  1. 一种半导体器件的结边缘区，其中，所述结边缘区包括一个以上的环单元，所述环单元包括：
    第一导电类型的半导体衬底；
    多个槽，设置于所述半导体衬底的一侧，所述多个槽的内部设置有导电材料，所述导电材料通过第一绝缘介质而与所述半导体衬底相隔离；
    第二导电类型的多个浮空区，邻接所述第一绝缘介质而对应设置于所述多个槽的底部，所述第二导电类型相异于所述第一导电类型；以及
    第二绝缘介质，设置于所述半导体衬底的表面，以覆盖、邻接或邻近所述第一绝缘介质。
  2. 如权利要求1所述半导体器件的结边缘区，其中，还包括第一金属层，所述第二绝缘介质在所述多个槽的槽口处设置有开口，所述第一金属层设置于所述第二绝缘介质上，且通过所述开口与所述导电材料相接触，并通过所述第二绝缘介质而与所述半导体衬底相隔离。
  3. 如权利要求1所述半导体器件的结边缘区，其中，所述导电材料替換为所述第一绝缘介质。
  4. 如权利要求1所述半导体器件的结边缘区，其中，还包括第二导电类型的至少一上部区，所述至少一个上部区设置于所述多个槽的局部或全部的槽间隔中。
  5. 如权利要求4所述半导体器件的结边缘区，其中，所述至少一个上部区通过所述第一绝缘介质而与所述导电材料相隔离。
  6. 如权利要求4所述半导体器件的结边缘区，其中，所述至少一个上部区设置位置邻近或邻接所述多个槽的槽口。
  7. 如权利要求4所述半导体器件的结边缘区，其中，所述多个槽包括两个边界槽，所述至少一个上部区选择性的设置于所述两个边界槽中至少其一的外侧。
  8. 如权利要求4所述半导体器件的结边缘区，其中，还包括第一金属层，所述第一金属层设置于所述第二绝缘介质上。
  9. 如权利要求8所述半导体器件的结边缘区，其中，所述第二绝缘介质在所述多个槽的槽口处设置有开口，所述第一金属层通过所述开口与所述导电材料相接触。
  10. 如权利要求8所述半导体器件的结边缘区，其中，所述第二绝缘介质上设置有开口，所述第一金属层通过所述开口而与局部或全部的所述至少一个上部区相接触。
  11. 如权利要求4所述半导体器件的结边缘区，其中，所述至少一个上部区包括次掺杂区。
  12. 如权利要求11所述半导体器件的结边缘区，其中，所述次掺杂区为重掺杂区或轻掺杂区。
  13. 如权利要求11所述半导体器件的结边缘区，其中，所述次掺杂区与所述至少一个上部区为相同导电类型或相异导电类型。
  14. 如权利要求1所述半导体器件的结边缘区，其中，所述第一导电类型为N型，所述第二导电类型为P型；或者，所述第一导电类型为P型，所述第二导电类型为N型。
  15. 如权利要求1所述半导体器件的结边缘区，其中，所述第二金属层设置于所述半导体器件底部，所述半导体衬底与所述第二金属层之间设置有掺杂区域。
  16. 如权利要求15所述半导体器件的结边缘区，其中，所述掺杂区域为第一导电类型或第二导电类型。
  17. 如权利要求15所述半导体器件的结边缘区，其中，所述掺杂区域为复合结构，所述复合结构包括相异导电类型的第一区域与第二区域。
  18. 如权利要求15所述半导体器件的结边缘区，其中，所述第一区域与所述第二区域为叠层配置或同层邻接配置。
  19. 如权利要求1所述半导体器件的结边缘区，其中，所述多个槽为2、3或4个。
  20. 一种半导体器件，包括有源区与结边缘区，其中，所述结边缘区包括一个以上的环单元，所述环单元包括：
    N型半导体衬底；
    多个槽，设置于所述N型半导体衬底的一侧，所述多个槽的内部设置有多晶硅，所述多晶硅通过第一绝缘介质而与所述N型半导体衬底相隔离，所述多个槽包括两个边界槽；
    P型多个浮空区，邻接所述第一绝缘介质而对应设置于所述多个槽的底部；
    至少一个P型上部区，设置于所述多个槽的局部或全部的槽间隔及所述两个边界槽的外侧；
    第二绝缘介质，设置于所述半导体衬底的表面，设置有开口；以及
    第一金属层，设置于所述第二绝缘介质上，所述第一金属层通过所述开口而与局部或全部的所述至少一个P型上部区相接触，及所述第一金属层通过所述开口与所述多晶硅相接触，或所述第一金属层通过所述第二绝缘介质与所述多晶硅相隔离。
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