WO2020258496A1 - 元胞结构及其应用的半导体器件 - Google Patents

元胞结构及其应用的半导体器件 Download PDF

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Publication number
WO2020258496A1
WO2020258496A1 PCT/CN2019/103092 CN2019103092W WO2020258496A1 WO 2020258496 A1 WO2020258496 A1 WO 2020258496A1 CN 2019103092 W CN2019103092 W CN 2019103092W WO 2020258496 A1 WO2020258496 A1 WO 2020258496A1
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region
type
semiconductor substrate
semiconductor
semiconductor device
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PCT/CN2019/103092
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English (en)
French (fr)
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杜文芳
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南京芯舟科技有限公司
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Priority to US17/621,970 priority Critical patent/US20220246748A1/en
Publication of WO2020258496A1 publication Critical patent/WO2020258496A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to semiconductor devices related to cell structures and applications thereof.
  • Trench power semiconductor devices have many characteristics such as high integration, high input impedance, low drive power, simple drive circuit, low on-resistance, reduced on-voltage, fast switching speed, low switching loss, etc., and are widely used in various power management And switch conversion.
  • the common insulated gate bipolar transistor (IGBT) which is a composite fully controlled voltage-driven power semiconductor device composed of an insulated gate field effect transistor (MOS) and a bipolar transistor (BJT)
  • MOS insulated gate field effect transistor
  • BJT bipolar transistor
  • the power semiconductor device manufacturing process that combines deep and shallow grooves requires strict adjustment of the concentration and doping degree of semiconductor materials in each part to effectively control the performance of the device, so the process requirements are relatively strict. Especially according to the function of the device, the depth of each groove, the width of the notch, and the arrangement pitch areaki. Once a little error, the function of the device may be different from the pre-design. When the number of grooves is too large, it is difficult to miniaturize the device. Moreover, one of the original deep grooves is intended to cooperate with the minority carrier barrier region to limit holes from flowing out of the device from the P-type source body region.
  • the etching window of the groove is offset, one side of the semiconductor region will be close to the deep groove
  • the local concentration is deviated from the predetermined requirement, resulting in an error in the structure of the deep groove, resulting in a poor conduction path or an unexpected hole channel, which greatly increases the conduction voltage drop of the device.
  • the purpose of the present application is to provide a cell structure and a semiconductor device using the same, which improves the fault tolerance of the trench manufacturing process through the improvement of the cell structure.
  • a cell structure of a semiconductor device proposed according to the present application is characterized in that the cell structure includes: a semiconductor substrate of a first conductivity type; a plurality of first groove units arranged on top of the semiconductor substrate, The plurality of first groove units are arranged separately, the conductive material is arranged in the plurality of first groove units, and is isolated from the semiconductor substrate by the first medium; the carrier barrier region of the first conductivity type, A side edge adjacent to the bottom or close to the bottom of the plurality of first groove units is provided, and is isolated from the conductive material by the first medium; the first source body region of the second conductivity type is provided with the plurality of In the interval of the first groove unit, the first source body region is provided with more than one source region, the first source body region and the source region are both located on the surface of the semiconductor substrate; the first metal layer, Disposed on the top of the semiconductor substrate, the first metal layer is in contact with the first source body region and the source region; a second medium is disposed on the top of the semiconductor substrate, adjacent to or adjacent to
  • the number of the carrier barrier region is one, and the plurality of first groove units jointly contact the carrier barrier region.
  • the number of the carrier barrier regions is multiple, and each of the plurality of first groove units contacts one of the carrier barrier regions.
  • the slot widths of the plurality of first slot units are the same or different.
  • the depths of the plurality of first groove units are the same or different.
  • the side of the first source body region contacts the side of the adjacent first groove unit, and the source region contacts the first medium.
  • the second medium is adjacent to the first metal layer, covers all the notches of the plurality of first groove units, and contacts part or all of the source region.
  • the conductivity type of the source region is equal to the conductivity type of the semiconductor substrate.
  • the conductive material can be connected to the gate electrode of the semiconductor device to form a gate region, or used to design grounding.
  • the source region is a heavily doped region or a lightly doped region.
  • the first conductivity type is N type and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.
  • the first semiconductor region is of the first conductivity type or the second conductivity type.
  • one side of the first semiconductor region is provided with a second semiconductor region of the same or different conductivity type.
  • the same layer side of the first semiconductor region is provided with a third semiconductor region with a different conductivity type.
  • a first electric field shielding structure which includes: the semiconductor substrate; and a first electric field shielding region of the second conductivity type disposed in the semiconductor substrate and having the same or similar depth In the carrier barrier region.
  • the first electric field shielding structure further includes: a plurality of second groove units arranged on the top of the semiconductor substrate and located outside the plurality of first groove units; Conductive material is arranged in each of the second groove units, and is isolated from the semiconductor substrate by a third medium; the first electric field shielding area is arranged adjacent to the bottom of the plurality of second groove units or the side edges close to the bottom , Isolated from the conductive material by the third medium; and, in the second source body region, the second source body region is located in the semiconductor substrate in the interval between the plurality of second groove units The bottom surface.
  • the second source body region is of the first conductivity type or the second conductivity type.
  • the first electric field shielding structure further includes: a third metal layer disposed on the top of the semiconductor substrate, the third metal layer contacting the second source body region; and fourth A medium is disposed on the top of the semiconductor substrate, adjacent to the third metal layer, and the fourth medium covers part or all of the slots of the plurality of second slot units.
  • part or all of the surface of the second source body region is in contact with the third metal layer.
  • the adjacent electric field shielding region and the carrier barrier region are in contact or not in contact with each other.
  • it further includes a second electric field shielding structure, which includes: the semiconductor substrate; a second electric field shielding region of the second conductivity type disposed in the semiconductor substrate; and a fourth metal layer , Arranged on the top of the semiconductor substrate; and, a second conductivity type semiconductor region is formed in the semiconductor substrate in a vertical direction and contacts the second electric field shielding region and the fourth metal layer.
  • a second electric field shielding structure which includes: the semiconductor substrate; a second electric field shielding region of the second conductivity type disposed in the semiconductor substrate; and a fourth metal layer , Arranged on the top of the semiconductor substrate; and, a second conductivity type semiconductor region is formed in the semiconductor substrate in a vertical direction and contacts the second electric field shielding region and the fourth metal layer.
  • the conductive material is polysilicon or a metal material with conductive ability.
  • the aforementioned various types of semiconductor materials include silicon (Si) materials or silicon carbide (SiC) materials.
  • the first medium, the second medium, the third medium and the fourth medium may optionally include silicon dioxide or benzocyclobutene (BCB) or Polyimide (PI), a composite layer of silicon dioxide and other substances, such as a composite layer of silicon dioxide and silicon nitride, a composite layer of silicon dioxide and polyimide (PI)... and other insulating materials.
  • silicon dioxide or benzocyclobutene (BCB) or Polyimide (PI) a composite layer of silicon dioxide and other substances, such as a composite layer of silicon dioxide and silicon nitride, a composite layer of silicon dioxide and polyimide (PI)... and other insulating materials.
  • a semiconductor device of another object of the present application includes a cell region and a terminal region.
  • the cell region includes more than one cell.
  • the structure of the cell includes: an N-type semiconductor substrate;
  • the groove unit is arranged on the top of the N-type semiconductor substrate, the plurality of first groove units are separately arranged, the conductive material is arranged in the plurality of first groove units, and the N-type semiconductor substrate passes through the first medium.
  • the N-type carrier barrier region is arranged adjacent to or near the bottom of the plurality of first groove units, and is isolated from the conductive material by the first medium;
  • P-type first A source body region in the interval between the plurality of first groove units, the first source body region is provided with more than one N-type source region, the P-type first source body region and the N-type source
  • the regions are all located on the surface of the semiconductor substrate;
  • a first metal layer is disposed on the top of the N-type semiconductor substrate, and the first metal layer contacts the P-type first source body region and the N-type source region
  • the second medium is arranged on the top of the N-type semiconductor substrate, adjacent to or adjacent to the first metal layer, the second medium covers part or all of the notches of the plurality of first groove units;
  • P-type The semiconductor region is arranged at the bottom of the N-type semiconductor substrate; and, the second metal layer is arranged to contact the P-type semiconductor region.
  • the carrier barrier region design and the concentration condition higher than the semiconductor substrate can limit the conduction path or hole channel under the premise of maintaining the function of the semiconductor device, and also obtain a lower conduction voltage drop.
  • the outer side of the main structure of the cell structure can be provided with a field limiting ring, a P floating island, or an electric field shielding structure as described above, which can be used as an electric field shielding area, thereby improving the withstand voltage of the semiconductor device.
  • the PMOS composed of the aforementioned electric field shielding structure can not only enhance the efficiency of electric field shielding, but also serve as a hole current channel to prevent parasitic thyristors from turning on, and also improve the robustness of the device (Robust).
  • the main cell structure can also be matched with a three-dimensional doped P-type semiconductor region to form an electric field shielding structure that contacts the cathode of the surface semiconductor device, which can also achieve the effect of electric field shielding and improve the voltage resistance.
  • the number of groove units is designed in parallel with the wider shallow grooves, even if the etching windows of a few grooves are offset, the semiconductor area concentration can be adjusted better to avoid poor conduction paths or unexpected holes aisle.
  • the uniformity of groove specifications, depth and other requirements can simplify the complexity of the manufacturing process and reduce the difficulty of device manufacturing.
  • FIG. 1 is an example diagram of the structure of an exemplary semiconductor device combining deep and shallow grooves
  • FIG. 2 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the application.
  • FIG. 3 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the application.
  • FIG. 4 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the application.
  • FIG. 5 is a schematic diagram of a first electric field shielding structure of a semiconductor device according to an embodiment of the application.
  • FIG. 6 is a schematic diagram of a first electric field shielding structure of a semiconductor device according to an embodiment of the application.
  • FIG. 7 is a schematic diagram of a first electric field shielding structure of a semiconductor device according to an embodiment of the application.
  • FIG. 8 is a schematic diagram of a second electric field shielding structure of a semiconductor device according to an embodiment of the application.
  • FIG. 9 is a schematic diagram of the cell structure of a punch-through type or an electric field cut-off type according to an embodiment of the application.
  • FIG. 10 is a schematic diagram of the structure of a reversed cell according to an embodiment of the application.
  • FIG. 11 is a schematic diagram of a cell structure of an electric field cutoff type combined with a reverse conduction type according to an embodiment of the application.
  • FIG. 1 is a diagram showing an example of the structure of a semiconductor device combining exemplary deep and shallow trenches.
  • This kind of device is a new type of power semiconductor device (MOS Controlled quasi-Thyristor, MCKT for short) that uses a combination of deep and shallow grooves.
  • the device is composed of multiple cell units.
  • Figure 1 illustrates the cross-sectional structure diagram of one of the cells.
  • the cell structure includes: an N-type semiconductor substrate 001, and a P-type first semiconductor region 002 is provided on one side of the N-type semiconductor substrate 001, which serves as an anode region.
  • first groove unit 700 and second groove unit 800 are provided, and the depth of the first groove unit 700 is smaller than that of the second groove unit 800.
  • N-type carrier barrier region 010 with a higher doping concentration than the N-type semiconductor substrate 001, also called a minority carrier barrier region, and at the bottom of the second trench unit 800 There is a P-type electric field shielding area 101.
  • a conductive material is disposed in the first tank unit 700 and the second tank unit 800, and the conductive material can be polysilicon or a material with conductive properties.
  • the conductive material in the first trench unit 700 serves as the first gate region 011, and the conductive material in the second trench unit 800 serves as the second gate region 111.
  • the first gate region 011 and the second gate region 111 are respectively isolated from the N-type semiconductor substrate 001.
  • the side of the N-type carrier barrier region 010 is in contact with the second dielectric 013 of the second groove unit 800.
  • the P-type source body region 202 is disposed between the first tank unit 700 and the second tank unit 800.
  • the P-type source body region 202 is provided with an N-type source region 303, and the N-type source region 303 is close to the first tank unit 700.
  • a P-type floating semiconductor region 203 is provided outside the first tank unit 700 and the second tank unit 800.
  • the first electrode 500 and the second electrode 502 include or are made of metal materials.
  • the first electrode 500 is in contact with at least part of the first gate region 111, at least part of the P-type source body region 202 and at least part of the N-type source region 303, and the second electrode 502 covers the P-type first semiconductor region 002.
  • a third dielectric 015 is provided between the first gate region 011 and the first electrode 500 for isolation; a fourth dielectric 016 is provided between the P-type floating semiconductor region 203 and the first electrode 500 for isolation.
  • the first gate region 011 is the gate electrode of the device, and the first electrode 500 and the second electrode 502 are the cathode and the anode of the device, respectively.
  • the first trench unit 700, the N-type carrier barrier region 010, the P-type source body region 202, and the N-type source region 303 form an NMOS structure.
  • the N-type source region 303 is a source region of NMOS electrons
  • the N-type carrier barrier region 010 is a drain region of NMOS electrons
  • the first gate region 011 is a gate region of NMOS.
  • NMOS trench The channel is opened, and electrons reach the P-type first semiconductor region 002 from the N-type source region 303 through the P-type source body region 202, the N-type carrier barrier region 010, and the N-type semiconductor substrate 001.
  • holes from the P-type first semiconductor region 002 pass through the N-type semiconductor substrate 001 and the P-type electric field shielding region 101 to reach the N-type carrier barrier region 010.
  • the built-in potential formed between the N-type semiconductor substrate 001 and the N-type carrier barrier region 010 hinders the flow of holes to the P-type source and body region 202.
  • the hole concentration in the N-type semiconductor substrate 001 is close to The N-type carrier barrier region 010 will be significantly increased to form a strong conductivity modulation, thereby greatly improving the current density of the device. That is, under the same current density, the device has a lower turn-on voltage V ON than IGBT.
  • the negatively charged ionizing acceptor in the partially depleted P-type electric field shielding region 101 absorbs from the depleted N-type semiconductor substrate 001
  • the electric force lines generated by the positively charged ionization donors cause only a few electric lines to reach the gate region 011. Therefore, the electric field around the dielectric layer at the bottom of the first groove unit 700 and the second groove unit 800 is low, so that high blocking can be obtained Voltage, while improving the life of the dielectric layer, so that the reliability of the device can be improved.
  • the P-type electric field shielding region 101 shields most of the electric force lines from the N-type semiconductor substrate 001, the charge in the first gate region 011 becomes insensitive to changes in the collector potential, which is reflected in the gate-collector capacitance (C GC ) Decrease.
  • the power semiconductor device manufacturing process that combines deep and shallow grooves requires strict adjustment of the concentration and doping degree of semiconductor materials in each part to effectively control the performance of the device, so the process requirements are relatively strict. Harsh. Especially according to the function of the device, the depth of each groove, the width of the notch, and the arrangement pitch areaki. Once a little error, the function of the device may be different from the pre-design. When the number of grooves is too large, it is difficult to miniaturize the device. Moreover, one purpose of the original deep trench is to cooperate with the minority carrier barrier region, thereby limiting holes from flowing out of the device from the P-type source body region 202.
  • the trench etching window is offset, it will also cause the N-type carrier barrier region.
  • 010 has a low concentration on the surface of the dielectric layer 013 on one side, thereby providing a channel for holes to flow out of the device from the P-type source body region 202, so that the device loses the advantage of low on-voltage drop.
  • the cell structure includes: a semiconductor substrate 001 of a first conductivity type; a plurality of first groove units 700 arranged on top of the semiconductor substrate 001, the plurality of first groove units 700 are arranged separately, and the conductive material 011 Are arranged in the plurality of first groove units 700 and are isolated from the semiconductor substrate 001 by a first medium 012; a carrier barrier region 010 of the first conductivity type is arranged adjacent to the plurality of first The groove unit 700 is isolated from the conductive material 011 by the first medium 012; the first source body region 202 of the second conductivity type is arranged in the interval of the plurality of first groove units 700, the first The source body region 202 is provided with more than one source region 303, the first source body region 202 and the source region 303 are both located on the surface of the semiconductor substrate 001; the first metal layer 500 is provided on the second On the top of the semiconductor substrate 002, the first metal layer 500 contacts
  • the conductivity type of each semiconductor region is temporarily the same as that of FIG. 1, the first conductivity type is N type, and the second conductivity type is P type.
  • the electric field shielding region is not provided in the main structure, and the deep groove structure connected to the electric field shielding region is not provided.
  • the semiconductor conductivity type is the same as that of FIG.
  • holes pass from the P-type first semiconductor region 003 and the N-type semiconductor substrate 001 reaches the N-type carrier barrier region.
  • the built-in potential formed between the N-type semiconductor substrate 001 and the N-type carrier barrier region 010 hinders the flow of holes to the P-type source body region 202, so the hole concentration is close to the N-type carrier potential
  • the barrier area 010 and its vicinity will be significantly increased to form a strong conductance modulation, which greatly increases the current density of the device, and at the same time limits the generation position of the electron path and the hole path, even if the deep groove design is not used, the hole path It will not be produced in additional parts.
  • the device has a lower turn-on voltage V ON than IGBT. Even if the etching window of the first trench unit 700 is offset, no additional hole path will be formed, so as to maintain the predetermined low conduction voltage drop function of the semiconductor device.
  • the carrier barrier region 010 is disposed adjacent to the side edge of the plurality of first groove units 700 near the bottom. It also means that the carrier barrier region 010 may be arranged only in the interval of the plurality of first groove units 700, or further arranged on both sides of each first groove unit 700.
  • trenching can be performed first, and then semiconductor doping (implantation) is performed according to the preformed position of the carrier barrier region 010; or, semiconductor doping (implantation) is performed first, and trenching is performed later.
  • the number of the carrier barrier region is one, and the plurality of first groove units jointly contact the carrier barrier region.
  • the number of the carrier barrier regions 010 may also be multiple, and each of the plurality of first groove units 700 corresponds to contacting one of the carrier barrier regions. District 010.
  • the number and configuration of the carrier barrier regions 010 shown in FIG. 2 to FIG. 4 depend on design requirements, and are applicable to the same or similar semiconductor device structure examples, and are not limited thereto.
  • the slot widths of the plurality of first slot units 700 are the same or different.
  • the depths of the plurality of first groove units 700 are the same or different.
  • the side of the first source region 202 contacts the side of the adjacent first groove unit 700, and the source area 303 contacts the side of the adjacent first groove unit 700.
  • the second medium 013 is adjacent to the first metal layer 500, covers the entire notch range of the plurality of first groove units 700, and contacts part or all of the source region 303.
  • the side of the first source body region 202 contacts the side of the adjacent first groove unit 700, and the source region 303 contacts the first medium 012.
  • the source region 303 is of the first conductivity type or the second conductivity type.
  • the source region 303 is a heavily doped region or a lightly doped region.
  • FIG. 5 is a schematic diagram of a first electric field shielding structure of a semiconductor device according to an embodiment of the application.
  • the difference from the previous example is that it also includes a first electric field shielding structure.
  • the first electric field shielding structure is arranged on both outer sides of the cell main structure in FIG.
  • the actual application is not limited to this, and the first electric field shielding structure can be selectively disposed on at least one of the two outer sides of the cell main structure.
  • the first electric field shielding structure includes: the semiconductor substrate 001; the first electric field shielding region 101 of the second conductivity type is disposed in the semiconductor substrate 001 and has the same depth or It is close to the carrier barrier region 010.
  • FIG. 6 is a schematic diagram of a first electric field shielding structure of a semiconductor device according to an embodiment of the application.
  • the first electric field shielding structure further includes: a plurality of second groove units 800 arranged on the top of the semiconductor substrate 001 and located outside the plurality of first groove units 700, A conductive material is arranged in the plurality of second groove units 800, and is isolated from the semiconductor substrate 001 by a second medium 013; the first electric field shielding region 101 is arranged adjacent to the plurality of second groove units 800 The bottom or the side edge close to the bottom is isolated from the conductive material by the third medium 015; and, the second source body region 203 is arranged in the interval of the plurality of second groove units 800, so The second source body region 203 is located on the surface of the semiconductor substrate 001.
  • the second source body region 203 is of the first conductivity type or the second conductivity type. That is, according to the functional requirements of the semiconductor device, the second source body region 203 adopts an N-type source body region or a P-type source body region.
  • it further includes a third metal layer 504 disposed on the top of the semiconductor substrate 001, and the third metal layer 504 contacts the second source body region 203;
  • the fourth medium 016 is disposed on the top of the semiconductor substrate 001 and adjacent to the third metal layer 504, and the fourth medium 016 covers part or all of the notches of the plurality of second groove units 800.
  • part or all of the surface of the second source body region 203 is in contact with the third metal layer 504.
  • the first metal layer 500 and the third metal layer 504 are both connected to the cathode of the semiconductor device.
  • the adjacent first electric field shielding region 101 and the carrier barrier region 010 are not in contact with each other.
  • FIG. 7 is a schematic diagram of a first electric field shielding structure of a semiconductor device according to an embodiment of the application.
  • the first electric field shielding region 101 and the carrier barrier region 010 are arranged at the same or similar depths, and the adjacent first electric field shielding region 101 and the carrier The current barrier regions 010 are in contact with each other.
  • the number and configuration of the first electric field shielding structures shown in FIG. 5 to FIG. 7 are determined according to design requirements, and are applicable to the same or similar semiconductor device structure examples, and are not limited thereto.
  • the first electric field shielding region 101 may still be in contact due to process accuracy.
  • the figure disclosed in this application is a schematic diagram for illustration.
  • the first electric field shielding region 101 and the carrier barrier region 010 may cause position deviation, depth deviation, and range of the semiconductor region due to the accuracy of the doping implantation process. Diffusion and other situations, but the function and operation of the device are regarded as the same as the application in this case in principle.
  • the cell main structure of the semiconductor device can be regarded as the basic unit. Since the carrier barrier region has a higher concentration and the device withstand voltage is also lower, the electric field shielding shown in FIGS. 5 to 7 can be provided. structure.
  • the first electric field shielding region 101 can be a heavily doped region or a lightly doped region, but the heavily doped region has better effects.
  • the first electric field shielding region 101, the semiconductor substrate 001, the second source body region 203, the second trench unit and the conductive material in it form a PMOS structure. When the device is turned off, the PMOS structure will be turned on, and the potential of the first electric field shielding region 101 is close to the potential of the cathode.
  • the first electric field shielding region 101 and the semiconductor substrate 001 form a PN junction reversely biased and begin to deplete each other.
  • the positively charged ionized donors from the semiconductor substrate 001 are absorbed by the negatively charged ionized acceptors in the electric field shielding region, so that the lines of power reaching the source body region 202 are basically shielded, thereby improving the voltage resistance of the semiconductor device.
  • electric field shielding structures are configured on both sides of the main cell structure. After the N region between the two first electric field shielding regions 101 is completely depleted, the power lines emitted from the semiconductor substrate 001 hardly reach the source region. 202. The full shielding effect of the electric field is formed as much as possible, and the semiconductor device has a better withstand voltage.
  • the PMOS formed by the electric field shielding structure can also be used as a hole current channel when the device is turned off, so as to prevent the parasitic thyristor from turning on, thereby improving the robustness of the semiconductor device.
  • FIG. 8 is a schematic structural diagram of a second electric field shielding structure of a semiconductor device according to an embodiment of the application.
  • the cell structure further includes a second electric field shielding structure.
  • the second electric field shielding structure includes: the semiconductor substrate 001; a second electric field shielding region 201 of a second conductivity type disposed in the semiconductor substrate 001; a fourth metal layer 506 disposed on the semiconductor substrate And the second conductive type semiconductor region 102 is formed in the semiconductor substrate 001 in a vertical direction and contacts the second electric field shielding region 201 and the fourth metal layer 506.
  • the fourth medium 016 is disposed on the surface of the semiconductor substrate 001, is located between the fourth metal layer 506 and the semiconductor substrate 001, and partially covers the surface of the semiconductor region 102 The peripheral part.
  • the potential of the second electric field shielding region 201 is close to the potential of the cathode.
  • the second electric field shielding region 201 and the semiconductor substrate 001 form a PN junction reversely biased and begin to deplete each other.
  • the positively charged ionized donors from the semiconductor substrate 001 are absorbed by the negatively charged ionized acceptors in the electric field shielding region, so that the lines of power reaching the source body region 202 are basically shielded, thereby improving the voltage resistance of the semiconductor device.
  • Figure 8 shows only the electric field shielding structure.
  • the electric field shielding structure is configured on both sides of the cell main structure, but the configuration method is that among the aforementioned electric field shielding structures, the electric field shielding structure is selectively arranged in the cell main structure. On both sides.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P type
  • the second conductivity type is N type
  • the source region 303 is of the first conductivity type or the second conductivity type.
  • the source region 303 is a heavily doped region or a lightly doped region.
  • the source region 303 when the source region 303 is N-type, it serves as an electron source region, and when the source region 303 is P-type, it serves as a hole source region.
  • a first semiconductor region 003 is provided between the first semiconductor substrate 001 and the second metal layer 502.
  • the first semiconductor region 003 is of the second conductivity type; or, the conductivity type of the first semiconductor region 003 is equivalent to the first semiconductor substrate 001.
  • One side of the first semiconductor region 003 is provided with a second semiconductor region 004 of the same or different conductivity type.
  • the same layer side of the first semiconductor region 003 is provided with a third semiconductor region 005 of different conductivity type.
  • FIG. 9 is a schematic diagram of a punch-through or electric field cut-off cell structure according to an embodiment of the application.
  • one side of the first semiconductor region 003 is provided with a second semiconductor region 004 of the first conductivity type, which serves as a field stop region, and the doping concentration of the second semiconductor region 004 is higher than that of the first semiconductor region.
  • a semiconductor substrate 001 When the highest voltage is applied between the anode and the cathode, the electric field is cut off in the field cut-off area, and the field cut-off area will not be completely depleted. Therefore, the electric field cut-off structure formed in FIG.
  • the total amount of carriers in the first semiconductor substrate 001 is proportional to the thickness of the first semiconductor substrate 001, so the total amount of carriers can be reduced. Under a certain current, the time required for the semiconductor device to change from the on-state to the off-state or from the off-state to the on-state is shorter, thereby obtaining smaller switching losses.
  • FIG. 10 is a schematic diagram of the structure of a retrograde cell according to an embodiment of the application.
  • a third semiconductor region 005 of the first conductivity type is provided on the same layer side of the first semiconductor region 003. Both the first semiconductor region 003 and the third semiconductor region 005 are in direct contact with the second metal layer 502 to form an anode short (Anode Short) structure.
  • the first conductivity type is N type
  • the second conductivity type is P type.
  • a body diode is composed of a P-type source body region 202, an N-type carrier barrier region 010, an N-type first semiconductor substrate 001, and an N-type third semiconductor region 005, wherein the P-type source body region 202 is the body The anode of the diode, and the N-type third semiconductor region 005 is the cathode of the body diode.
  • the body diode when the potential of the cathode (the first metal layer 500) is higher than that of the anode (the second metal layer 502) At a potential, the body diode is forward biased, and current flows from the P-type source body region 202 to the N-type third semiconductor region 005 through the N-type carrier barrier region 010 and the N-type first semiconductor substrate 001. Due to the existence of the N-type carrier barrier region 010, the anode hole injection efficiency of the body diode is greatly reduced, so that a very low charge concentration is obtained near the anode region when the body diode is turned on, so that a smaller Turn-off loss.
  • FIG. 11 is a schematic diagram of a cell structure of an electric field cut-off type combined with a reverse conduction type according to an embodiment of the application, and the structure shown has the electrical characteristics described in FIG. 9 and FIG. 10, and will not be repeated here.
  • the semiconductor substrate 001 shown in FIGS. 1 to 8 is a non-punch-through type (Non Punch Through), that is, when the highest voltage is applied between the collector and the emitter, the semiconductor substrate 001 will not Depletion;
  • Figure 9 shows a Punch Through or Field Stop cell;
  • Figure 10 shows a Reverse Conduction cell;
  • Figure 11 shows the structure of Figure 9 and Figure 10 combination.
  • the above-mentioned embodiments are not limited to the respective illustrated structures, and each embodiment is applicable to non-punch-through structures, punch-through structures, field-stop types (Field Stop), and anode short-circuits (Anode Short).
  • Type structure or structure equivalent/similar to the above.
  • the conductive material 011, the first metal layer 500, the second metal layer 502, the third metal layer 504, and the fourth metal layer 506 are selectively polysilicon or conductive materials. metallic material.
  • the metal layers are integrally connected or connected through conductive elements, no matter what method is adopted, it does not have much impact on the function of the semiconductor device.
  • the aforementioned various types of semiconductor materials include silicon (Si) materials or silicon carbide (SiC) materials.
  • the first medium 012, the second medium 013, the third medium 015, and the fourth medium 016 may optionally include silica or phenylcyclobutene. (BCB) or polyimide (PI), a composite layer of silicon dioxide and other substances, such as a composite layer of silicon dioxide and silicon nitride, a composite layer of silicon dioxide and polyimide (PI), etc. Insulation Materials.
  • a semiconductor device includes a cell region and a terminal region, wherein the cell region includes more than one cell, and the structure of the cell includes: an N-type semiconductor substrate 001 A plurality of first groove units 700 are arranged on the top of the N-type second semiconductor substrate 002, the plurality of first groove units 700 are separately arranged, and the conductive material 011 is arranged in the plurality of first groove units 700 , Isolated from the N-type semiconductor substrate 001 by the first dielectric 012; the N-type carrier barrier region 010 is arranged adjacent to the bottom of the plurality of first groove units 700 or close to the bottom of the side edge, through The first medium 012 is isolated from the conductive material 011; the P-type first source body region 202 is provided with more than one P-type source body region 202 in the interval between the plurality of first groove units 700 The N-type source region 303, the P-type source body region 202 and the N-type source region 303 are both located on the surface of the N-type second semiconductor
  • the conduction path or channel of the holes can be limited under the premise of maintaining the function of the semiconductor device, so as to obtain a lower conduction voltage drop.
  • the first electric field shielding structure or the second electric field shielding structure as described above can be selectively provided outside the main structure of the cell structure, which can be used as an electric field shielding area, thereby improving the withstand voltage of the semiconductor device.
  • the PMOS composed of the aforementioned first electric field shielding structure can not only produce electric field shielding benefits, but also serve as a hole current channel when the device is turned off, preventing the parasitic thyristor from turning on, and also improving the robustness of the device.
  • the main cell structure can also be matched with a three-dimensional doped P-type semiconductor region to form an electric field shielding structure that contacts the cathode of the surface semiconductor device, which can also achieve the effect of electric field shielding and improve the voltage resistance.
  • the number of groove units is designed in parallel with the wider shallow grooves, even if the etching windows of a few grooves are offset, the semiconductor area concentration can be adjusted better to avoid poor conduction paths or unexpected holes aisle.
  • the uniformity of groove specifications, depth and other requirements can simplify the complexity of the manufacturing process and reduce the difficulty of device manufacturing.
  • the first conductivity type is different from the second conductivity type.
  • the first conductivity type is P-type and the second conductivity type is N-type; or, the first conductivity type is N-type and the second conductivity type is It is P-type, that is, the N-type and P-type in the above description can be interchanged, and the corresponding electrons and holes can also be interchanged. After the interchange, the principles of the present invention still apply.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

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Abstract

本申请是一种元胞结构及其应用的半导体器件，所述元胞结构包括半导体衬底，半导体衬底顶端设置多个槽单元，槽单元底设置对应的载流子势垒区，槽内设置导电材料。源体区设置于相邻槽单元之间，源体区表面紧贴设置有一个以上的源区，其与源体区接触半导体衬底顶部的第一金属层。半导体衬底底部则设置第一半导体区及其接触的第二金属层。本申请通过减化槽设置数量与屏蔽区的设计，在保持功能的同时达到导通或空穴路径设计限定的要求。

Description

元胞结构及其应用的半导体器件 技术领域
本发明涉及半导体技术领域，特别是关于元胞结构及其应用的半导体器件。
背景技术
沟槽功率半导体器件具有集成度高、输入阻抗高、驱动功率小、驱动电路简单、导通电阻低、导通压降低、开关速度快、开关损耗小等诸多特点，广泛应用于各类电源管理及开关转换。例如常见的绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)，其由绝缘栅场效应管(MOS)与双极性晶体管(BJT)组成的复合全控型电压驱动式功率半导体器件，就具备上述特点。为更进一步提高器件的鲁棒性及电流密度，一种应用深浅槽相结合的新型功率半导体器件(MOS Controlled quasi-Thyristor，简称MCKT)被提出。
技术问题
这种深浅槽相结合的功率半导体器件制程，需严格调整各部位半导体材料的浓度及掺杂程度，以有效控制器件的性能，故工艺要求相对较为严苛。尤其依据器件功能，各槽深浅、槽口宽度、排列间距有其讲究，一旦些许误差，即可能造成器件功能与预设计相异，槽数量设计过多时，亦不易器件的微化。而且原深槽其一用意是与少子势垒区配合，从而限定空穴从P型源体区流出器件，若是槽的刻蚀窗口发生套偏时，就会使得某一侧半导体区域靠近深槽处浓度与预定需求有所偏差，造成与深槽配合的结构有误，从而产生较差的导通路径或是产生预想之外的空穴通道，使得器件导通压降大幅增加。
发明内容
技术解决方案
为了解决上述技术问题，本申请的目的在于，提供一种元胞结构及其应用的半导体器件，通过元胞结构的改良而改善沟槽制作工艺的容错性。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。
依据本申请提出的一种半导体器件的元胞结构，其特征在于，所述元胞结构包括：第一导电类型的半导体衬底；多个第一槽单元，设置于所述半导体衬底顶部，所述多个第一槽单元分隔设置，导电材料设置于所述多个第一槽单元内，通过第一介质与所述半导体衬底相隔离；第一导电类型的载流子势垒区，设置邻接于所述多个第一槽单元的底部或接近底部的侧缘，通过所述第一介质与所述导电材料相隔离；第二导电类型的第一源体区，设置所述多个第一槽单元的间隔中，所述第一源体区设置有 一个以上的源区，所述第一源体区及所述源区均位在所述半导体衬底表面；第一金属层，设置于所述半导体衬底顶部，所述第一金属层接触所述第一源体区与所述源区；第二介质，设置于所述半导体衬底顶部，邻近或邻接所述第一金属层，所述第二介质涵盖部分或全部的所述多个第一槽单元的槽口；第一半导体区，设置在所述半导体衬底的底部；以及，第二金属层，设置接触所述第一半导体区。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，所述载流子势垒区的数量为一个，所述多个第一槽单元共同接触所述载流子势垒区。
在本申请的一实施例中，所述载流子势垒区的数量为多个，所述多个第一槽单元每一者均对应接触一个所述载流子势垒区。
在本申请的一实施例中，所述多个第一槽单元的槽口宽度为相同或相异。
在本申请的一实施例中，所述多个第一槽单元的深度为相同或相异。
在本申请的一实施例中，所述第一源体区侧边接触相邻的第一槽单元的侧边，所述源区接触所述第一介质。
在本申请的一实施例中，所述第二介质邻接所述第一金属层，涵盖所述多个第一槽单元的全部槽口范围，并接触部分或全部的所述源区。
在本申请的一实施例中，所述源区的导电类型等同于所述半导体衬底的导电类型。
在本申请的一实施例中，所述导电材料可连接半导体器件的栅电极相连而形成栅极区，或是用以设计接地。
在本申请的一实施例中，所述源区为重掺杂区或轻掺杂区。
在本申请的一实施例中，所述第一导电类型为N型，所述第二导电类型为P型；或者，所述第一导电类型为P型，所述第二导电类型为N型。
在本申请的一实施例中，所述第一半导体区为第一导电类型或第二导电类型。
在本申请的一实施例中，所述第一半导体区的一侧设置有与其导电类型相同或相异的第二半导体区。
在本申请的一实施例中，所述第一半导体区的同层侧边设置有与其导电类型相异的第三半导体区。
在本申请的一实施例中，还包括第一电场屏蔽结构，其包括：所述半导体衬底；第二导电类型的第一电场屏蔽区，设置所述半导体衬底之中且深度相同或相近于所述载流子势垒区。
在本申请的一实施例中，所述第一电场屏蔽结构还包括：多个第二槽单元，设置于所述半导体衬 底顶部并位于所述多个第一槽单元的外侧，所述多个第二槽单元内设置有导电材料，通过第三介质与所述半导体衬底相隔离；所述第一电场屏蔽区设置邻接于所述多个第二槽单元的底部或接近底部的侧缘，通过所述第三介质与所述导电材料相隔离；以及，所述第二源体区，设置所述多个第二槽单元的间隔中，所述第二源体区位在所述半导体衬底表面。
在本申请的一实施例中，所述第二源体区为第一导电类型或第二导电类型。
在本申请的一实施例中，所述第一电场屏蔽结构还包括：第三金属层，设置于所述半导体衬底顶部，所述第三金属层接触所述第二源体区；第四介质，设置于所述半导体衬底顶部，邻接所述第三金属层，所述第四介质涵盖部分或全部的所述多个第二槽单元的槽口。
在本申请的一实施例中，所所述第二源体区部分或全部表面与所述第三金属层接触。
在本申请的一实施例中，相邻的所述电场屏蔽区与所述载流子势垒区为相互接触或不接触。
在本申请的一实施例中，还包括第二电场屏蔽结构，其包括：所述半导体衬底；第二导电类型的第二电场屏蔽区，设置所述半导体衬底之中；第四金属层，设置于所述半导体衬底的顶部；以及，第二导电类型的半导体区域，以垂直方向形成于所述半导体衬底中，且接触所述第二电场屏蔽区与所述第四金属层。
在本申请的一实施例中，所述导电材料为多晶硅或具导电能力的金属材料。
在本申请的一实施例中，前述的各类半导体的材料包括硅(Si)材料或碳化硅(SiC)材料。
在本申请的一实施例中，所述第一介质、所述第二介质、所述第三介质与所述第四介质可选择性的采用包括二氧化硅或苯环丁烯(BCB)或聚酰亚胺(PI)、二氧化硅与其它物质的复合层，例如二氧化硅与氮化硅的复合层、二氧化硅与聚酰亚胺(PI)的复合层…等绝缘材料。
本申请的另一目的的一种半导体器件，包括元胞区与终端区，所述元胞区包括一个以上的元胞，所述元胞的结构包括：N型半导体衬底；多个第一槽单元，设置于所述N型半导体衬底顶部，所述多个第一槽单元分隔设置，导电材料设置于所述多个第一槽单元内，通过第一介质与所述N型半导体衬底相隔离；N型载流子势垒区，设置邻接于所述多个第一槽单元的底部或接近底部的侧缘，通过所述第一介质与所述导电材料相隔离；P型第一源体区，设置所述多个第一槽单元的间隔中，所述第一源体区设置有一个以上的N型源区，所述P型第一源体区及所述N型源区均位在所述半导体衬底表面；第一金属层，设置于所述N型半导体衬底顶部，所述第一金属层接触所述P型第一源体区与所述N型源区；第二介质，设置于所述N型半导体衬底顶部，邻近或邻接所述第一金属层，所述第二 介质涵盖部分或全部的所述多个第一槽单元的槽口；P型半导体区，设置在所述N型半导体衬底的底部；以及，第二金属层，设置接触所述P型半导体区。
有益效果
本申请通过载流子势垒区设计与高于半导体衬底的浓度条件，可在保持半导体器件功能的前提下，限定导通路径或空穴通道，还能获得较低的导通压降。其次，元胞结构的主结构外侧还能设置如场限环、P浮岛、或是如前所述的电场屏敝结构，可作为电场屏敝区域，借此提升半导体器件的耐压性。此外，前述电场屏敝结构构成的PMOS除能加强电场屏敝效益外，还能作为空穴电流通道，避免寄生晶闸管开启，亦提升器件的鲁棒性(Robust)。再者，元胞主结构还能配套三维方向掺杂的P型半导体区域形成接触表面半导体器件阴极的电场屏敝结构，同样能达到电场屏蔽的效果，提升耐压性。而且，槽单元的数量与较为宽泛的浅槽并列设计，即使少数槽的刻蚀窗口发生套偏，较能调节半导体区域浓度，避免产生较差的导通路径或是产生预想之外的空穴通道。甚至，槽的规格、深度等需求一致化，较能简化制造工艺的复杂性，较低器件制作难度。
附图说明
为了能更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为范例性深浅槽相结合的半导体器件结构示例图；
图2为本申请实施例的半导体器件的元胞结构示意图；
图3为本申请实施例的半导体器件的元胞结构示意图；
图4为本申请实施例的半导体器件的元胞结构示意图；
图5为本申请实施例的半导体器件的第一电场屏蔽结构示意图；
图6为本申请实施例的半导体器件的第一电场屏蔽结构示意图；
图7为本申请实施例的半导体器件的第一电场屏蔽结构示意图；
图8为本申请实施例的半导体器件的第二电场屏蔽结构示意图；
图9为本申请实施例的穿通型或电场截止型元胞结构示意图；
图10为本申请实施例的逆导型元胞结构示意图；
图11为本申请实施例的电场截止型结合逆导型的元胞结构示意图。
具体实施方式
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本申请具体实施例，其不应被视为限制本申请未在此详述的其它具体实施例。
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
本申请的说明书和权利要求书以及上述附图中的述语“第一”、“第二”、“第三”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情形下可以互换。此外，术语“包括”和“具有”以及他譬的变形，意图在于覆盖不排他的包含。
本申请说明书中使用的术语仅用来描述特定实施方式，而并不意图显示本申请的概念。除非上下文中有明确不同的意义，否则，以单数形式使用的表达涵盖具有多个的形式的表达。在本申请说明书中，应理解，诸如“包括”、“具有”以及“含有”等术语意图说明存在本申请说明书中揭示的特征、数字、步骤、动作或其组合的可能性，而并不意图排除可存在或可添加一个或多个其他特征、数字、步骤、动作或其组合的可能性。附图中的相同参考标号指代相同部分。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰、理解和便于描述，夸大设备、系统、组件、电路的配置范围。将理解的是，当组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体实施例，对依据本发明提出的一种元胞结构及其应用的半导体器件，其具体实施方式、结构、特征及其功效，详细说明如后。
图1为范例性深浅槽相结合的半导体器件结构示例图。此种器件是应用深浅槽相结合的新型功率半导体器件(MOS Controlled quasi-Thyristor，简称MCKT)。该器件是由多个元胞单位组成。图1示例其中一个元胞的剖面结构图。元胞的结构包括：N型半导体衬底001，N型半导体衬底001的一侧设置有P型第一半导体区002，其作为阳极区。N型半导体衬底001的另一侧设置数量分别为一个以上的第一槽单元700和第二槽单元800，第一槽单元700的深度小于第二槽单元800。在第一槽单元700的底部有比N型半导体衬底001的掺杂浓度更高的N型载流子势垒区010，亦称作少子势垒区， 在第二槽单元800的底部设有P型电场屏蔽区101。第一槽单元700与第二槽单元800内设置有导电材料，导电材料可为多晶硅或是具导电性质的材料。第一槽单元700内的导电材料作为第一栅极区011，第二槽单元800内的导电材料作为第二栅极区111。通过第一介质012及第二介质013，第一栅极区011与第二栅极区111分别与N型半导体衬底001相隔离。N型载流子势垒区010的侧边与第二槽单元800的第二介质013相接触。P型源体区202设置在第一槽单元700和第二槽单元800之间，P型源体区202内设有N型源区303，N型源区303紧贴第一槽单元700的一侧的第一介质012。第一槽单元700和第二槽单元800之外设置有P型浮空半导体区203。第一电极500与第二电极502包括金属材料或由金属材料制成。第一电极500与至少部分的第一栅极区111、至少部分的P型源体区202以及至少部分的N型源区303相接触，第二电极502覆盖P型第一半导体区002。第一栅极区011与第一电极500之间设有第三介质015进行隔离；P型浮空半导体区203与第一电极500之间设有第四介质016进行隔离。第一栅极区011为该器件的栅电极，第一电极500与第二电极502分别为该器件的阴极及阳极。
结合上述可得，第一槽单元700、N型载流子势垒区010、P型源体区202以及N型源区303构成一个NMOS结构。N型源区303是NMOS的电子的源区，N型载流子势垒区010是NMOS的电子的漏区，第一栅极区011是NMOS的栅区。当第二电极502和第一电极500之间的电压V CE大于零，且第一栅极区011和第一电极500之间的电压V CE超过所述NMOS的阈值电压V THN时，NMOS沟道开启，电子自N型源区303通过P型源体区202、N型载流子势垒区010、N型半导体衬底001到达P型第一半导体区002。相对的，空穴自P型第一半导体区002通过N型半导体衬底001、P型电场屏蔽区101到达N型载流子势垒区010。N型半导体衬底001与N型载流子势垒区010之间形成的内建电势阻碍了空穴往P型源体区202的流动，N型半导体衬底001中的空穴浓度在靠近N型载流子势垒区010处会显着提高而形成强烈的电导调制，从而大大地提高了器件的电流密度。即在相同的电流密度下，该器件拥有比IGBT更低的导通压降V ON。
当第二电极502和第一电极500之间的电压V CE较高时,部分耗尽的P型电场屏蔽区101内带负电的电离受主吸收了来自耗尽的N型半导体衬底001内带正电的电离施主产生的电力线，使得只有极少电力线到达栅极区011，因此第一槽单元700与第二槽单元800底部的介质层周围的电场较低，从而可以获得高的阻断电压，同时提高了介质层的寿命，从而使得器件的可靠性得以提高。由于P型电场屏蔽区101屏蔽了来自N型半导体衬底001的大部分电力线，第一栅极区011内电荷对集电极电位的变化变得不敏感，反映为栅-集电极电容(C GC)的减小。
虽然图1所示的器件具有上述优点，这种深浅槽相结合的功率半导体器件制程，需严格调整各部 位半导体材料的浓度及掺杂程度，以有效控制器件的性能，故工艺要求相对较为严苛。尤其依据器件功能，各槽深浅、槽口宽度、排列间距有其讲究，一旦些许误差，即可能造成器件功能与预设计相异，槽数量设计过多时，亦不易器件的微化。而且原深槽其一用意是与少子势垒区配合，从而限定空穴从P型源体区202流出器件，若是槽刻蚀窗口发生套偏时，亦会使得N型载流子势垒区010在一侧介质层013表面浓度较低，从而给空穴提供一个通道从P型源体区202流出器件，使得器件失去低导通压降的优势。
图2至图4为本申请实施例的半导体器件的元胞结构示意图。所述元胞结构包括：第一导电类型的半导体衬底001；多个第一槽单元700，设置于所述半导体衬底001顶部，所述多个第一槽单元700分隔设置，导电材料011设置于所述多个第一槽单元700内，通过第一介质012与所述半导体衬底001相隔离；第一导电类型的载流子势垒区010，设置邻接于所述多个第一槽单元700，通过所述第一介质012与所述导电材料011相隔离；第二导电类型的第一源体区202，设置所述多个第一槽单元700的间隔中，所述第一源体区202设置有一个以上的源区303，所述第一源体区202及所述源区303均位在所述半导体衬底001表面；第一金属层500，设置于所述第二半导体衬底002顶部，所述第一金属层500接触所述第一源体区202与所述源区303；第二介质013，设置于所述第二半导体衬底002顶部，邻近或邻接所述第一金属层500，所述第二介质013涵盖部分或全部的所述多个槽单元770的槽口；第一半导体区003，设置在所述第一半导体衬底001的底部；以及，第二金属层502，设置接触所述第一半导体区003。所述第二金属层502结合第一半导体区003作为阳极区。所述第一金属层500作为相对阳极区的阴极区。
为便于理解，各半导体区域导电类型暂与图1相同，第一导电类型为N型，第二导电类型为P型。
与图1所示器件不同之处在于，本申请实施例的元胞结构，电场屏蔽区不设置于主要结构，同时不设置连接电场屏蔽区的深槽结构。在半导体导电类型等同图1的情形下，当阳极(第二金属层502)和阴极(第一金属层500)之间的电压V CE大于零，且栅极区011和第一金属层500之间的电压V GE超过由第一槽单元700、N型载流子势垒区010、P型源体区202以及N型源区303所构成的NMOS的阈值电压V THN时，NMOS沟道开启，电子自N型源区303通过P型源体区202、N型载流子势垒区010、N型半导体衬底001到达P型第一半导体区003。相对的，空穴自P型第一半导体区003通过、N型半导体衬底001到达N型载流子势垒区。N型半导体衬底001与N型载流子势垒区010之间，形成的内建电势阻碍了空穴往P型源体区202的流动，因此空穴浓度在靠近N型载流子势垒区010及其附近处会显着提高而形成强烈的电导调制，从而大大地提高了器件的电流密度，同时局限电子路径与空穴路径的产生位置，即便不采用深槽设计，空穴路径亦不会在额外部位产生。而且在相同 的电流密度下，该器件拥有比IGBT更低的导通压降V ON。即便第一槽单元700的刻蚀窗口发生套偏，亦不会形成额外空穴通路，从而维持半导体器件的预定的低导通压降的功能性质。
如图2，在一些实施例中，所述载流子势垒区010仅有一个，且设置范围较宽，所述载流子势垒区010设置邻接于所述多个第一槽单元700的底部。
如图3，在一些实施例中，所述载流子势垒区010设置邻接于所述多个第一槽单元700接近底部的侧缘。亦是指，所述载流子势垒区010可以是仅配置于所述多个第一槽单元700间隔内，或是更进一步的设置于每一第一槽单元700的两侧。在制程上，可先挖槽，再依据所述载流子势垒区010预形成位置而进行半导体掺杂(注入)；或者，先进行半导体掺杂(注入)，后进行挖槽。
如图2，在本申请的一实施例中，所述载流子势垒区的数量为一个，所述多个第一槽单元共同接触所述载流子势垒区。
如图4，在一些实施例中，所述载流子势垒区010的数量也可以是多个，所述多个第一槽单元700每一者均对应接触一个所述载流子势垒区010。
图2至图4所示的所述载流子势垒区010，其数量与配置方式视设计需求而定，适用于各相同或相近的半导体器件结构示例中，不以此为限。
在本申请的一实施例中，所述多个第一槽单元700的槽口宽度为相同或相异。
在本申请的一实施例中，所述多个第一槽单元700的深度为相同或相异。
在本申请的一实施例中，所述第一源体区202侧边接触相邻第一槽单元700的侧边，所述源区303接触所述相邻第一槽单元700的所述第一介质012。
在本申请的一实施例中，所述第二介质013邻接所述第一金属层500，涵盖所述多个第一槽单元700的全部槽口范围，并接触部分或全部的所述源区303。
在本申请的一实施例中，所述第一源体区202侧边接触相邻的第一槽单元700的侧边，所述源区303接触所述第一介质012。
在本申请的一实施例中，所述源区303为第一导电类型或第二导电类型。
在本申请的一实施例中，所述源区303为重掺杂区或轻掺杂区。
图5为本申请实施例的半导体器件的第一电场屏蔽结构示意图。与前述示例不同在于，还包括第一电场屏蔽结构，图5虽以第一电场屏蔽结构设置于元胞主结构的两外侧，以虚线作结构区别。但在实际应用上不以此为限，所述第一电场屏蔽结构可选择性的设置于元胞主结构的两外侧中至少一者。在本申请的一实施例中，所述第一电场屏蔽结构包括：所述半导体衬底001；第二导电类型的第一电 场屏蔽区101，设置所述半导体衬底001之中且深度相同或相近于所述载流子势垒区010。
图6为本申请实施例的半导体器件的第一电场屏蔽结构示意图。在本申请的一实施例中，所述第一电场屏蔽结构还包括：多个第二槽单元800，设置于所述半导体衬底001顶部并位于所述多个第一槽单元700的外侧，所述多个第二槽单元800内设置有导电材料，通过第二介质013与所述半导体衬底001相隔离；所述第一电场屏蔽区101设置邻接于所述多个第二槽单元800的底部或接近底部的侧缘，通过所述第三介质015与所述导电材料相隔离；以及，所述第二源体区203，设置所述多个第二槽单元800的间隔中，所述第二源体区203位在所述半导体衬底001表面。
在本申请的一实施例中，所述第二源体区203为第一导电类型或第二导电类型。即是指，依据半导体器件功能需求，所述第二源体区203采用N型源体区或P型源体区。
如图6所示，在本申请的一实施例中，还包括设置于所述半导体衬底001顶部的第三金属层504，所述第三金属层504接触所述第二源体区203；第四介质016，设置于所述半导体衬底001顶部，邻接所述第三金属层504，所述第四介质016涵盖部分或全部的所述多个第二槽单元800的槽口。
在本申请的一实施例中，所述第二源体区203部分表面或全部表面与所述第三金属层504接触。
在一些实施例中，第一金属层500与第三金属层504皆与半导体器件的阴极相连。
在本申请的一实施例中，相邻的所述第一电场屏蔽区101与所述载流子势垒区010为相互不接触。
图7为本申请实施例的半导体器件的第一电场屏蔽结构示意图。在本申请的一实施例中，所述第一电场屏蔽区101与所述载流子势垒区010设置于深度为相同或相近，相邻的所述第一电场屏蔽区101与所述载流子势垒区010为相互接触。
图5至图7所示的第一电场屏蔽结构，其数量与配置方式视设计需求而定，适用于各相同或相近的半导体器件结构示例中，不以此为限。
在实际应用中，即使不欲使所述第一电场屏蔽区101与所述载流子势垒区010相接触，仍可能因为工艺精度而造成两者接触。此外，本申请所揭图示为说明示意图，所述第一电场屏蔽区101与所述载流子势垒区010会因为掺杂注入工艺精度而有可能产生半导体区域位置偏差、深度偏差、范围扩散等情形，但器件功能与运作，原则上视为相同与本案申请。
在一些实施例中，半导体器件的元胞主结构可视为基础单元，由于载流子势垒区浓度较高，器件 耐压亦较低，因此可以配套设置上述图5至图7的电场屏蔽结构。所述第一电场屏蔽区101可为重掺杂区或轻掺杂区，然重掺杂区功效较佳。第一电场屏蔽区101、半导体衬底001、第二源体区203、第二槽单元及其内的导电材料会形成PMOS结构。当器件关断时，所述PMOS结构会开启，第一电场屏蔽区101的电位接近阴极的电位，第一电场屏蔽区101与半导体衬底001形成PN结反偏，开始相互耗尽，大部分从半导体衬底001中带正电的电离施主会被电场屏蔽区中带负电的电离受主所吸收，使得到达源体区202的电力线基本被屏蔽，进而提升半导体器件的耐压性。在一些实施例中，元胞主结构两侧皆配置电场屏蔽结构，两个第一电场屏蔽区101之间的N区被全部耗尽后，半导体衬底001发出的电力线几乎不易到达源体区202，尽可能的形成电场全屏蔽效果，半导体器件耐压效益更佳。
在一些实施例中，所述电场屏蔽结构构成的PMOS，在器件关断的时候亦可作为空穴电流通道，避免寄生晶闸管开启，从而提升半导体器件的鲁棒性(Robust)。
图8为本申请实施例的半导体器件的第二电场屏蔽结构的结构示意图。在本申请的一实施例中，所述元胞结构还包括第二电场屏蔽结构。所述第二电场屏蔽结构包括：所述半导体衬底001；第二导电类型的第二电场屏蔽区201，设置所述半导体衬底001之中；第四金属层506，设置于所述半导体衬底001的顶部；以及，第二导电类型的半导体区域102，以垂直方向形成于所述半导体衬底001中，且接触所述第二电场屏蔽区201与所述第四金属层506。在一些实施例中，第四介质016设置于所述半导体衬底001的表面，并位于所述第四金属层506与所述半导体衬底001之间，同时部分的涵盖所述半导体区域102表面外围部分。
在一些实施例中，受半导体区域102的影响，第二电场屏蔽区201的电位接近阴极的电位，第二电场屏蔽区201与半导体衬底001形成PN结反偏，开始相互耗尽，大部分从半导体衬底001中带正电的电离施主会被电场屏蔽区中带负电的电离受主所吸收，使得到达源体区202的电力线基本被屏蔽，进而提升半导体器件的耐压性。
图8所示仅为说明电场屏蔽结构，在一些实施例中，元胞主结构两侧皆配置电场屏蔽结构，但配置方式为前述数种电场屏蔽结构中，选择性的配置于元胞主结构的两侧。
在本申请的一实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
在本申请的一实施例中，所述第一导电类型为P型，所述第二导电类型为N型。
在本申请的一实施例中，所述源区303为第一导电类型或第二导电类型。
在本申请的一实施例中，所述源区303为重掺杂区或轻掺杂区。
在本申请的一实施例中，所述源区303为N型时作为电子源区，所述源区303为P型时作为空穴源区。
在本申请的一实施例中，所述第一半导体衬底001与所述第二金属层502之间设置有第一半导体区003。如前述，所述第一半导体区003为第二导电类型；或者，所述第一半导体区003的导电类型等同所述第一半导体衬底001。
所述第一半导体区003的一侧设置有与其导电类型相同或相异的第二半导体区004。
在本申请的一实施例中，所述第一半导体区003的同层侧边设置有与其导电类型相异的第三半导体区005。
图9为本申请实施例的穿通型或电场截止型元胞结构示意图。在本申请的一实施例中，所述第一半导体区003的一侧设置有第一导电类型的第二半导体区004，其作为场截止区，第二半导体区004的掺杂浓度高于第一半导体衬底001。在阳极和阴极之间加上最高电压时使得电场在场截止区内截止，且场截止区不会全耗尽。因此图9所形成的电场截止型结构可以获得较小的第一半导体衬底001厚度，从而获得更小的导通压降(V ON)。其次，第一半导体衬底001内载流子总量和第一半导体衬底001厚度成正比，故可使得载流子总量减小。在一定电流下，半导体器件从导通态到关断态或者从关断态到导通态所需的时间更短，进而获得较小的开关损耗。
图10为本申请实施例的逆导型元胞结构示意图。在本申请的一实施例中，所述第一半导体区003的同层侧边设置有第一导电类型的第三半导体区005。第一半导体区003和第三半导体区005均与第二金属层502直接接触，形成阳极短路(Anode Short)结构。同以第一导电类型为N型，第二导电类型为P型作说明。由P型源体区202、N型载流子势垒区010、N型第一半导体衬底001以及N型第三半导体区005构成一个体二极管，其中P型源体区202为所述体二极管的阳极，N型第三半导体区005为所述体二极管的阴极，在本申请的一实施例中，当阴极(第一金属层500)的电位高于阳极(第二金属层502)的电位时，此体二极管正偏，电流从P型源体区202经N型载流子势垒区010、N型第一半导体衬底001流向N型第三半导体区005。由于N型载流子势垒区010的存在，所述体二极管的阳极空穴注入效率被大大降低，从而在体二极管导通时阳极区附近获得极低的电荷浓度，从而可以获得较小的关断损耗。
图11为本申请实施例的电场截止型结合逆导型的元胞结构示意图，其所示结构兼具图9和图10 描述的电学特征，这里不再赘述。
在本申请的一实施例中，图1至图8所示半导体衬底001是非穿通型(Non Punch Through)，即在集电极和发射极之间加上最高电压时半导体衬底001不会全耗尽；图9所示穿通型(Punch Through)或电场截止型(Field Stop)的元胞；图10所示逆导型(Reverse Conduction)的元胞；图11为图9与图10结构的组合。然而，上述实施例不以各自图示结构为限，各实施例均适用非穿通型(Non Punch Through)结构、穿通型(Punch Through)、电场截止型(Field Stop)与阳极短路(Anode Short)型结构，或与上述相等效/相近似的结构。
在本申请的一实施例中，所述导电材料011、第一金属层500、第二金属层502、第三金属层504与第四金属层506，其选择性的采用多晶硅或具导电能力的金属材料。
在本申请的一实施例中，各金属层是一体相连或是通过导电元件连接，不论采用何种方式，对半导体器件的功能没有太大影响。
在本申请的一实施例中，前述的各类半导体的材料包括硅(Si)材料或碳化硅(SiC)材料。
在本申请的一实施例中，所述第一介质012、所述第二介质013、所述第三介质015与所述第四介质016可选择性的采用包括二氧化硅或苯环丁烯(BCB)或聚酰亚胺(PI)、二氧化硅与其它物质的复合层，例如二氧化硅与氮化硅的复合层、二氧化硅与聚酰亚胺(PI)的复合层…等绝缘材料。
本申请的另一目的的一种半导体器件，包括元胞区与终端区，其特征在于，所述元胞区包括一个以上的元胞，所述元胞的结构包括：N型半导体衬底001；多个第一槽单元700，设置于所述N型第二半导体衬底002顶部，所述多个第一槽单元700分隔设置，导电材料011设置于所述多个第一槽单元700内，通过第一介质012与所述N型半导体衬底001相隔离；N型载流子势垒区010，设置邻接于所述多个第一槽单元700的底部或接近底部的侧缘，通过所述第一介质012与所述导电材料011相隔离；P型第一源体区202，设置所述多个第一槽单元700的间隔中，所述P型源体区202设置有一个以上的N型源区303，所述P型源体区202及所述N型源区303均位在所述N型第二半导体衬底002表面；第一金属层500，设置于所述N型第二半导体衬底002顶部，所述第一金属层500接触所述源体区202与所述源区303；第二介质013，设置于所述第二半导体衬底002顶部，邻近或邻接所述第一金属层500，所述第二介质013涵盖部分或全部的所述多个第一槽单元700的槽口；P型半导体区003，设置在所述N型半导体衬底001的底部；以及，第二金属层502，设置接触所述P型半导体区003。
本申请通过载流子势垒区设计与高于半导体衬底的浓度条件，可在保持半导体器件功能的前提下， 限定空穴的导通路径或通道，从而能获得较低的导通压降。其次，元胞结构的主结构外侧还能选择性的设置如前所述的第一电场屏蔽结构或第二电场屏蔽结构，可作为电场屏蔽区域，借此提升半导体器件的耐压性。此外，前述第一电场屏蔽结构构成的PMOS除能产生电场屏蔽效益外，还能在器件关断的时候作为空穴电流通道，避免寄生晶闸管开启，亦提升器件的鲁棒性(Robust)。再者，元胞主结构还能配套三维方向掺杂的P型半导体区域形成接触表面半导体器件阴极的电场屏敝结构，同样能达到电场屏蔽的效果，提升耐压性。而且，槽单元的数量与较为宽泛的浅槽并列设计，即使少数槽的刻蚀窗口发生套偏，较能调节半导体区域浓度，避免产生较差的导通路径或是产生预想之外的空穴通道。甚至，槽的规格、深度等需求一致化，较能简化制造工艺的复杂性，较低器件制作难度。
如先前所述，第一导电类型与第二导电类型为相异，例如：第一导电类型为P型，第二导电类型为N型；或者，第一导电类型为N型，第二导电类型为P型，即以上描述中的N型和P型可以互换，对应的电子和空穴也可以互换，互换之后仍然适用本发明的原理。
“在本申请的一实施例中”及“在各种实施例中”等用语被重复地使用。此用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。
工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (20)

  1. 一种半导体器件的元胞结构，其中，所述元胞结构包括：
    第一导电类型的半导体衬底；
    多个第一槽单元，设置于所述半导体衬底顶部，所述多个第一槽单元分隔设置，导电材料设置于所述多个第一槽单元内，通过第一介质与所述半导体衬底相隔离；
    第一导电类型的载流子势垒区，设置邻接于所述多个第一槽单元的底部或接近底部的侧缘，通过所述第一介质与所述导电材料相隔离，所述载流子势垒区的浓度高于所述半导体衬底的浓度；
    第二导电类型的第一源体区，设置所述多个第一槽单元的间隔中，所述第一源体区设置有一个以上的源区，所述第一源体区及所述源区均位在所述半导体衬底表面；
    第一金属层，设置于所述半导体衬底顶部，所述第一金属层接触所述第一源体区与所述源区；
    第二介质，设置于所述半导体衬底顶部，邻近或邻接所述第一金属层，所述第二介质涵盖部分或全部的所述多个第一槽单元的槽口；
    第一半导体区，设置在所述半导体衬底的底部；以及
    第二金属层，设置接触所述第一半导体区。
  2. 如权利要求1所述半导体器件的元胞结构，其中，所述载流子势垒区的数量为一个，所述多个第一槽单元共同接触所述载流子势垒区。
  3. 如权利要求1所述半导体器件的元胞结构，其中，所述载流子势垒区的数量为多个，所述多个第一槽单元每一者均对应接触一个所述载流子势垒区。
  4. 如权利要求1所述半导体器件的元胞结构，其中，所述多个第一槽单元的槽口宽度为相同或相异；所述多个第一槽单元的深度为相同或相异。
  5. 如权利要求1所述半导体器件的元胞结构，其中，所述第一源体区侧边接触相邻的第一槽单元的侧边，所述源区接触所述第一介质。
  6. 如权利要求5所述半导体器件的元胞结构，其中，所述第二介质邻接所述第一金属层，涵盖所述多个第一槽单元的全部槽口范围，并接触部分或全部的所述源区。
  7. 如权利要求1所述半导体器件的元胞结构，其中，所述源区的导电类型等同于所述半导体衬底的导电类型。
  8. 如权利要求1所述半导体器件的元胞结构，其中，所述源区为重掺杂区或轻掺杂区。
  9. 如权利要求1所述半导体器件的元胞结构，其中，所述第一导电类型为N型，所述第二导电类型 为P型；或者，所述第一导电类型为P型，所述第二导电类型为N型。
  10. 如权利要求1所述半导体器件的元胞结构，其中，所述第一半导体区为第一导电类型或第二导电类型。
  11. 如权利要求1所述半导体器件的元胞结构，其中，所述第一半导体区的一侧设置有与其导电类型相同或相异的第二半导体区。
  12. 如权利要求1所述半导体器件的元胞结构，其中，所述第一半导体区的同层侧边设置有与其导电类型相异的第三半导体区。
  13. 如权利要求1所述半导体器件的元胞结构，其中，还包括第一电场屏蔽结构，其包括：
    所述半导体衬底；
    第二导电类型的第一电场屏蔽区，设置所述半导体衬底之中且深度相同或相近于所述载流子势垒区。
  14. 如权利要求13所述半导体器件的元胞结构，其中，所述第一电场屏蔽结构还包括：
    多个第二槽单元，设置于所述半导体衬底顶部并位于所述多个第一槽单元的外侧，所述多个第二槽单元内设置有所述导电材料，通过第三介质与所述半导体衬底相隔离；
    所述第一电场屏蔽区设置邻接于所述多个第二槽单元的底部或接近底部的侧缘，通过所述第三介质与所述导电材料相隔离；以及
    所述第二源体区，设置所述多个第二槽单元的间隔中，所述第二源体区位于所述半导体衬底表面。
  15. 如权利要求14所述半导体器件的元胞结构，其中，所述第二源体区为第一导电类型或第二导电类型。
  16. 如权利要求14所述半导体器件的元胞结构，其中，所述第一电场屏蔽结构还包括：
    第三金属层，设置于所述半导体衬底顶部，所述第三金属层接触所述第二源体区；以及
    第四介质，设置于所述半导体衬底顶部，邻接所述第三金属层，所述第四介质涵盖部分或全部的所述多个第二槽单元的槽口。
  17. 如权利要求16所述半导体器件的元胞结构，其中，所述第二源体区部分或全部表面与所述第三金属层接触。
  18. 如权利要求13所述半导体器件的元胞结构，其中，相邻的所述电场屏蔽区与所述载流子势垒区为相互接触或不接触。
  19. 如权利要求1所述半导体器件的元胞结构，其中，还包括第二电场屏蔽结构，其包括：
    所述半导体衬底；
    第二导电类型的第二电场屏蔽区，设置所述半导体衬底之中；
    第四金属层，设置于所述半导体衬底的顶部；以及
    第二导电类型的半导体区域，以垂直方向形成于所述半导体衬底中，且接触所述第二电场屏蔽区与所述第四金属层。
  20. 一种半导体器件，包括元胞区与终端区，其中，所述元胞区包括一个以上的元胞，所述元胞的结构包括：
    N型半导体衬底；
    多个第一槽单元，设置于所述N型半导体衬底顶部，所述多个第一槽单元分隔设置，导电材料设置于所述多个第一槽单元内，通过第一介质与所述N型半导体衬底相隔离；
    N型载流子势垒区，设置邻接于所述多个第一槽单元的底部或接近底部的侧缘，通过所述第一介质与所述导电材料相隔离，所述N型载流子势垒区的浓度高于所述N型半导体衬底的浓度；
    P型第一源体区，设置所述多个第一槽单元的间隔中，所述第一源体区设置有一个以上的N型源区，所述P型第一源体区及所述N型源区均位在所述半导体衬底表面；
    第一金属层，设置于所述N型半导体衬底顶部，所述第一金属层接触所述P型第一源体区与所述N型源区；
    第二介质，设置于所述N型半导体衬底顶部，邻近或邻接所述第一金属层，所述第二介质涵盖部分或全部的所述多个第一槽单元的槽口；
    P型半导体区，设置在所述N型半导体衬底的底部；以及
    第二金属层，设置接触所述P型半导体区。
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