JPS5984474A - 電力用縦型電界効果トランジスタ - Google Patents

電力用縦型電界効果トランジスタ

Info

Publication number
JPS5984474A
JPS5984474A JP57194283A JP19428382A JPS5984474A JP S5984474 A JPS5984474 A JP S5984474A JP 57194283 A JP57194283 A JP 57194283A JP 19428382 A JP19428382 A JP 19428382A JP S5984474 A JPS5984474 A JP S5984474A
Authority
JP
Japan
Prior art keywords
layer
source
substrate
vertical type
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57194283A
Other languages
English (en)
Inventor
Yukiyasu Usunaga
薄永　行泰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57194283A priority Critical patent/JPS5984474A/ja
Publication of JPS5984474A publication Critical patent/JPS5984474A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は二重拡散により半導体基板上のエピタキシャル
領域にゲート領域とソース領域を自己整合的に形成し、
ドレイン側のオーミックコンタクトを良好とし、低オン
抵抗を有する電力用縦型電界効果トランジスタ（ＭＯＢ
　　ＩＴ）に関する。
従来、電力用縦型Ｍ０８　　ＦＩＢＴ　　は高濃度基物
上にエピタキシャル領域を形成したウエーノ）を用い。
エピタキシャル領域に二重拡散によりゲート及びソース
部を作ハ前記ソース拡散時に裏面基板に基鈑濃度よυ高
濃度の不純物を拡散する。この拡散層深さは極めて浅い
ため、裏面＠、他極形成工程中ホーニング等で削除され
る場合がある。
通常の数オーム程度のオン抵抗素子では基板濃度が１０
ｃｒｒＬ　オーダーでオーミックの抵抗成分の影響は少
い。しかしｓ　　１　ｇ　Ｏミ！Ｊオーム以下の低オン
抵抗素子の場合、オーミック抵抗成分の寄与は極めて大
きな障害となる。
本発明の目的は上述の欠点を取除き、低オーミツク抵抗
を有する電力用縦型ＭＯ８１Ｔを提供することにある。
即ち、−導電型を有する牛轡体基板の一万の面に、半導
体基板と同一の導・成型低濃度エピタキシャル層を施し
、このエピタキシャル層に二重拡散により、ゲート領域
及びソース領域を自己整合的に形成される電界効果トラ
ンジスタに於て、上述のエピタキシャル層上に対向する
半導体基板面にソース層と同一の４１ｊｔ型でよシ高濃
度不純物層をソース拡散接合より深く備えた面を接合よ
シ浅い領域まで粗面化した上にドレイン電極を形成する
ものである。
この様に、半導体基板に高濃度の深い不純物層を設ける
ことにより、ホーニング等の表面研磨により除去されに
くいため、良好なオーミックコンタクトが得られる。
次に、■１面を参照し本発明を説明する。第１図（ａ）
は従来提業されているヘチャネル電力用縦型ＭＯ８ＦＩ
ＳＴの拡散工程完了後の断面図を示し、第１図（ｂｌは
裏面電極形成後の断面図を示す。
第１図（ａ）に於て、ｌは０．０１〜０．０２０儒の半
導体基板で、２は０．５〜２．００何のエピタキシャル
層である。
このウェーハのエピタキシャル層部に酸化膜を設け、フ
ォトレジスト法で所定の形状に酸化膜を部分除去し％第
１回目のＰ形不純物を注入し３を形成する。次に酸化膜
４とゲート層５を形成し。
第２回目のＰ形不純物により３′を設け、所定の時間拡
散後、同一の酸化膜４とゲート層５でマスクし、Ｎ形不
純物を拡散しソース領域６を設けると同時に、裏面にへ
形不純物を拡散し、ソース領域６の接合深さとほぼ同程
度のドレインＮ７を作り。
最後にソース電極８を設ける。
このソース領域６或いはドレイン領域７の接合深さは１
〜２μｍである。
第１図（ｂｌに於て、拡散終了後のウェーハの裏面をア
ルミナ或いはカーボラ／ダムの粒子によジ、ホーニング
し粗面化する。この時、裏面は均一な仕上げレベルで１
μｍ程度は除去される場合が多い。
最悪の場合、第３図のＶＤ　−Ｉｎ特性の破線で示す波
形となる。即ち、　ＶＦＩの立上）は０．１−０．５Ｖ
増加し、鴇、川の抵抗成分は５〜５０ｍΩの増加を示す
事が判明した。
この事はオン抵抗数Ωの素子に対し、５％以下の影響で
あるため１問題となる場合は少いが、数１０ｍΩ〜数１
００ｍΩの低オン抵抗素子では大問題となる。
更に、裏面の小形不純物層の拡散深さが浅いため、ホー
ニング研磨深さと逆転する恐れがあ！１１゜オン抵抗の
バラツキ幅も広くなる可能性がある。
これらの問題を改善するために本発明の一実施例を以下
に述べる。第２図（ａ）及び第２図（ｂ）けそれぞれ本
発明による拡散終了並び・に裏面電極形成後の断面図で
ある。第２図（ａｔに於て、半導体基体１の裏面に商磯
度不純物増］４を深くル取する方法は大きく分けて２通
りある。
（１）　　エピタキシャル形成前に半導体基板裏面側に
高濃度不純物領域を施す。
（２）拡散プロセスの前段で半導体基板の裏面側に高濃
度不純物領域を施す。
但し、半導体基板よυ高濃度とする条件であれば、拡散
終了後２μより深い高濃度不純物領域が形成される。こ
こでは、１２はゲート層で入力容素、帰還容量低減のた
めチャネル活成部以外は除去し、酸化膜】１の中に設け
、その上にソース電極１３を重ねて、フィールドプレー
ト効果を持せである。
第２図Ｔｂｌは半導体基板の裏面を粗面１５とし。
電極１６を形成したものである。
この様に確笑に高濃度領域１４を設けることにより、第
３図の実線で示すＶＦ２．Ｒ，及びｌ（４の特性が得ら
れる。
【図面の簡単な説明】
１２はゲート電極、１３はソース’ｔ＆、１４は半導体
基板１のソースと対向する面に設けられた高濃度不純物
領域、１６はドレイン！、極、第３図はＭＯＳ　　ＦＥ
Ｔの電流−電圧物性および隠流−抵抗特性で、　Ｖｐｌ
は従来の立上り電圧物性５Ｉ（Ｊｒ川は従来の抵抗値、
　ＶＦＲは本発明実施例による立上す電正特性、Ｊ：（
２，Ｒ４はこの本発明実施例の抵抗値である。 特開昭５９−８４４７４　（３） 茅　１回　（０−）　　　　　　　峯１図（ｂ）第２日
（α）　　　　　　第２図（ｂ）第３図

Claims (1)

    【特許請求の範囲】
  1. 一導電型午導体基板の一生面上に一導電型低濃度エビタ
    キシャル層を設け、前記エピタキシャル層に二重拡散に
    よυゲート領域とソース領域とを自己整合的に形成して
    成る・電界効果トランジスタに於て、前記−主面にソー
    ス層と同一の導電型及び高濃度を有し、ソース拡散接合
    より深い接合を設け、該接合より浅い領域まで表面を粗
    面化した上にドレイン区極を形成することを待機とする
    電力用縦型電界効果トランジスタ。
JP57194283A 1982-11-05 1982-11-05 電力用縦型電界効果トランジスタ Pending JPS5984474A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57194283A JPS5984474A (ja) 1982-11-05 1982-11-05 電力用縦型電界効果トランジスタ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57194283A JPS5984474A (ja) 1982-11-05 1982-11-05 電力用縦型電界効果トランジスタ

Publications (1)

Publication Number Publication Date
JPS5984474A true JPS5984474A (ja) 1984-05-16

Family

ID=16322021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57194283A Pending JPS5984474A (ja) 1982-11-05 1982-11-05 電力用縦型電界効果トランジスタ

Country Status (1)

Country Link
JP (1) JPS5984474A (ja)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0308612A2 (en) * 1987-09-24 1989-03-29 Mitsubishi Denki Kabushiki Kaisha Field effect transistor and manufacturing method thereof
US5532179A (en) * 1992-07-24 1996-07-02 Siliconix Incorporated Method of making a field effect trench transistor having lightly doped epitaxial region on the surface portion thereof
US5558313A (en) * 1992-07-24 1996-09-24 Siliconix Inorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon
US5578851A (en) * 1994-08-15 1996-11-26 Siliconix Incorporated Trenched DMOS transistor having thick field oxide in termination region
US5597765A (en) * 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
US5913130A (en) * 1996-06-12 1999-06-15 Harris Corporation Method for fabricating a power device
US5923979A (en) * 1997-09-03 1999-07-13 Siliconix Incorporated Planar DMOS transistor fabricated by a three mask process
US7851852B2 (en) 2004-09-16 2010-12-14 Semiconductor Components Industries, L.L.C. Method of forming a low capacitance semiconductor device and structure therefor
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0308612A2 (en) * 1987-09-24 1989-03-29 Mitsubishi Denki Kabushiki Kaisha Field effect transistor and manufacturing method thereof
US5910669A (en) * 1992-07-24 1999-06-08 Siliconix Incorporated Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof
US5532179A (en) * 1992-07-24 1996-07-02 Siliconix Incorporated Method of making a field effect trench transistor having lightly doped epitaxial region on the surface portion thereof
US5558313A (en) * 1992-07-24 1996-09-24 Siliconix Inorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon
US5981344A (en) * 1992-07-24 1999-11-09 Siliconix Incorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon
US5578851A (en) * 1994-08-15 1996-11-26 Siliconix Incorporated Trenched DMOS transistor having thick field oxide in termination region
US5639676A (en) * 1994-08-15 1997-06-17 Siliconix Incorporated Trenched DMOS transistor fabrication having thick termination region oxide
US5614751A (en) * 1995-01-10 1997-03-25 Siliconix Incorporated Edge termination structure for power MOSFET
US5597765A (en) * 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
US5913130A (en) * 1996-06-12 1999-06-15 Harris Corporation Method for fabricating a power device
US6078077A (en) * 1996-06-12 2000-06-20 Intersil Corporation Power device
US6236083B1 (en) 1996-06-12 2001-05-22 Intersil Corporation Power device
US5923979A (en) * 1997-09-03 1999-07-13 Siliconix Incorporated Planar DMOS transistor fabricated by a three mask process
US7851852B2 (en) 2004-09-16 2010-12-14 Semiconductor Components Industries, L.L.C. Method of forming a low capacitance semiconductor device and structure therefor
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9935193B2 (en) 2012-02-09 2018-04-03 Siliconix Technology C. V. MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US10229988B2 (en) 2012-05-30 2019-03-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US10283587B2 (en) 2014-06-23 2019-05-07 Vishay-Siliconix Modulated super junction power MOSFET devices
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
US10340377B2 (en) 2014-08-19 2019-07-02 Vishay-Siliconix Edge termination for super-junction MOSFETs

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