TWI534913B - 可堆疊模製微電子封裝 - Google Patents

可堆疊模製微電子封裝 Download PDF

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Publication number
TWI534913B
TWI534913B TW100125521A TW100125521A TWI534913B TW I534913 B TWI534913 B TW I534913B TW 100125521 A TW100125521 A TW 100125521A TW 100125521 A TW100125521 A TW 100125521A TW I534913 B TWI534913 B TW I534913B
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Taiwan
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conductive
microelectronic
substrate
microelectronic package
height
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TW100125521A
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English (en)
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TW201209939A (en
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比加希姆 哈巴
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泰斯拉公司
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Publication of TW201209939A publication Critical patent/TW201209939A/zh
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Description

可堆疊模製微電子封裝
本發明係關於微電子封裝且係關於製造或測試微電子封裝之方法。
本申請案主張2010年7月19日申請之美國專利申請案第12/838,974號的申請日期之權利，該案之揭示內容特此以引用的方式併入本文中。
諸如半導體晶片之微電子器件通常需要至其他電子組件之許多輸入及輸出連接。半導體晶片或其他相當器件之輸入及輸出接點一般以實質上覆蓋器件之一表面的柵格狀圖案安置(通常被稱作「區域陣列」)，或安置於可平行於且鄰近於器件之前表面之每一邊緣延伸的狹長列中，或安置於前表面之中心中。通常，諸如晶片之器件必須實體黏著於諸如印刷電路板的基板上，且器件之接點必須電連接至電路板之導電特徵部。
半導體晶片通常提供於封裝中，該等封裝促進在晶片之製造期間及在將晶片黏著於諸如電路板或其他電路面板之外部基板上期間進行的對晶片之處置。舉例而言，許多半導體晶片提供於適合於表面黏著之封裝中。已針對各種應用提議此一般類型之眾多封裝。最通常地，此等封裝包括通常被稱作「晶片載體」之介電元件，其中端子以電鍍或蝕刻之金屬結構的形式形成於介電質上。此等端子通常藉由諸如沿著晶片載體自身延伸之薄跡線的特徵部及藉由在晶片之接點與端子或跡線之間延伸的細引線或導線而連接至晶片自身之接點。在表面黏著操作中，將封裝置放至電路板上，以使得封裝上之每一端子與電路板上之對應接觸焊墊對準。將焊料或其他結合材料提供於端子與接觸焊墊之間。可藉由加熱總成以便使焊料熔融或「回焊」或以其他方式活化結合材料而將封裝永久性地結合於適當位置。
許多封裝包括附接至封裝之端子的呈焊球形式之焊料塊，焊料塊之直徑通常為約0.1 mm及約0.8 mm(5密耳及30密耳)。具有自底表面突出之焊球陣列的封裝通常被稱作球狀柵格陣列或「BGA」封裝。被稱作平台柵格陣列或「LGA」封裝之其他封裝係藉由薄層或由焊料所形成之平台而緊固至基板。此類型之封裝可能相當緊密。通常被稱作「晶片尺度封裝」之某些封裝佔據等於或僅稍大於併入於封裝中的器件之面積的電路板面積。此情形為有利的在於：此情形減小總成之總的大小且准許在基板上之各種器件之間使用短的互連，此又限制器件之間的信號傳播時間且由此促進以高速進行的總成之操作。
包括封裝之總成可遭受由器件及基板之差異熱膨脹及收縮所強加的應力。在操作期間以及在製造期間，半導體晶片傾向於膨脹及收縮達一量，該量不同於電路板之膨脹及收縮的量。在封裝之端子(諸如)藉由使用焊料而相對於晶片或其他器件固定的情況下，此等效應傾向於引起端子相對於電路板上之接觸焊墊移動。此情形可強加將端子連接至電路板上之接觸焊墊的在焊料中之應力。如以下各美國專利之某些較佳實施例中所揭示，半導體晶片封裝可具有可相對於晶片或併入於封裝中之其他器件移動的端子：美國專利5,679,977；5,148,266；5,148,265；5,455,390；及5,518,964，該等專利之揭示內容以引用的方式併入本文中。此移動可補償可觀程度之差異膨脹及收縮。
經封裝之器件之測試提出另一難克服的問題。在一些製造程序中，有必要在經封裝之器件的端子與測試夾具(test fixture)之間進行暫時連接，且經由此等連接操作器件以確保器件為完全功能性的。通常，必須在未將封裝之端子結合至測試夾具的情況下進行此等暫時連接。重要的是，確保所有端子可靠地連接至測試夾具之導電元件。然而，難以藉由將封裝相抵於簡單測試夾具(諸如，具有平面接觸焊墊之普通電路板)按壓而進行連接。若封裝之端子並非共平面的，或若測試夾具之導電元件並非共平面的，則該等端子中之一些端子將並不接觸測試夾具上之其各別接觸焊墊。舉例而言，在BGA封裝中，附接至端子之焊球之直徑的差及晶片載體之非平面性可引起該等焊球中之一些焊球處於不同高度處。
此等問題可經由使用具有經配置以補償非平面性之特徵部的特別建構之測試夾具來減輕。然而，此等特徵部添加了測試夾具之成本，且在一些狀況下，將某種不可靠性引入至測試夾具自身中。此情形特別不合需要，此係因為測試夾具及器件與測試夾具之嚙合應比經封裝之器件自身更可靠以便提供有意義的測試。此外，用於高頻操作之器件通常藉由施加高頻信號來測試。此要求對測試夾具中之信號路徑之電特性強加約束，此情形進一步使測試夾具的構造複雜化。
另外，當測試具有與端子連接之焊球的經封裝之器件時，焊料傾向於累積於測試夾具之嚙合焊球的彼等部分上。焊料殘餘物之此累積可縮短測試夾具之壽命且削弱測試夾具之可靠性。
已提出多種解決方案來處置上述問題。上述專利中所揭示之某些封裝具有可相對於微電子器件移動之端子。此移動可補償測試期間的端子之某種程度之非平面性。
皆簽發至Nishiguchi等人之美國專利5,196,726與5,214,308揭示了一種BGA型方法，其中晶片之面上的凸塊引線(bump lead)收納於基板上之杯狀插口中且藉由低熔點材料而結合於杯狀插口中。簽發至Beaman等人之美國專利4,975,079揭示了一種用於晶片之測試插口，在該測試插口中，測試基板上之圓頂形接點安置於圓錐形導引器內。迫使晶片相抵於基板，以使得焊球進入圓錐形導引器且嚙合基板上之圓頂形插腳。施加足夠的力以使得圓頂形插腳實際上使晶片之焊球變形。
BGA插口之另一實例可見於1998年9月8日發佈之共同讓渡的美國專利5,802,699中，該專利之揭示內容特此以引用的方式併入本文中。'699專利揭示了一種具有複數個孔之薄片狀連接器。每一孔具備在一孔之上向內延伸之至少一彈性層狀接點。BGA器件之凸塊引線可前進至該等孔中，以使得凸塊引線與該等接點嚙合。可測試總成，且若發現可接受，則可將凸塊引線永久性地結合至該等接點。
於2001年3月20日發佈之共同讓渡的美國專利6,202,297揭示了一種用於具有凸塊引線之微電子器件的連接器及用於製造及使用該連接器之方法，該專利的揭示內容特此以引用的方式併入本文中。在'297專利之一實施例中，介電基板具有自前表面向上延伸之複數個支柱。該等支柱可以支柱群組陣列來配置，其中每一支柱群組在其間界定一間隙。大體上層狀接點自每一支柱之頂部延伸。為了測試器件，將器件之凸塊引線各自插入於各別間隙內，藉此嚙合該等接點，隨著繼續插入凸塊引線，該等接點摩擦凸塊引線。通常，隨著將凸塊引線插入至間隙中，該等接點之遠端部分向下朝向基板且向外遠離間隙之中心偏轉。
共同讓渡之美國專利6,177,636揭示了一種用於在微電子器件與支撐基板之間提供互連的方法及裝置，該專利之揭示內容特此以引用的方式併入本文中。在'636專利之一較佳實施例中，一種製造用於微電子器件之互連組件之方法包括提供具有第一表面及第二表面之可撓性晶片載體，及將導電薄片耦接至該晶片載體之第一表面。接著選擇性地蝕刻該導電薄片以產生複數個實質上硬質支柱。可將韌性層提供於支撐結構之第二表面上且使諸如半導體晶片之微電子器件與該韌性層嚙合，以使得韌性層處於微電子器件與晶片載體之間，且留下該等支柱自晶片載體之曝露表面突出。將該等支柱電連接至微電子器件。該等支柱形成突出封裝端子，該等突出封裝端子可嚙合於插口中或以焊料結合至基板(如，電路面板)之特徵部。因為該等支柱可相對於微電子器件移動，所以此封裝實質上可適應在器件處於使用中時器件與支撐基板之間的熱膨脹係數失配。此外，該等支柱之尖端可為共平面的或幾乎共平面的。
儘管此項技術中存在所有上文所描述之進展，但仍將需要在製造或測試微電子封裝方面之進一步改良。
一種微電子封裝具有：一微電子元件，其上覆或黏著至一基板之一第一表面；及實質上硬質導電支柱，其突出超過該第一表面或突出超過該基板之一遠離該第一表面的第二表面。曝露於該基板之與該等導電支柱突出超過之該表面相反的一表面處的導電元件與該微電子元件電互連。一囊封物上覆該微電子元件之至少一部分及該等導電支柱突出超過的該基板之該表面，該囊封物具有一凹座或複數個開口，每一開口准許進行至至少一導電支柱之至少一電連接。至少一些導電支柱彼此電絕緣且經調適以同時攜載不同電位。在特定實施例中，該囊封物中之該等開口至少部分地曝露接合至支柱之導電塊，完全地曝露支柱之頂表面且部分地曝露支柱之邊緣表面，或可僅部分地曝露支柱之頂表面。
在一實施例中，該等導電支柱突出至高於該第一表面或該第二表面中之至少一者的一第一高度，該囊封物接觸該等導電支柱且具有在高於該等導電支柱突出超過的該基板之該相同表面的一第二高度處的一主表面，該第二高度大於該第一高度，且該囊封物中之該等開口為該主表面中之開口。
在一特定實施例中，該等導電支柱可突出超過該第一表面且該等導電元件可曝露於該第二表面處。
在一實施例中，該第一表面可具有一第一區及一自該第一區延伸之第二區。該微電子元件可上覆該第一區，且該等支柱可與該第二區對準。
在一特定實施例中，該等導電支柱可突出超過該第二表面且該等導電元件可曝露於該第一表面處。
該囊封物之該主表面可為一實質上平面表面。該囊封物可進一步具有在高於該第一表面之一第三高度處的一上覆該微電子元件之第二表面，該第三高度不同於該第二高度，例如，該第三高度大於該第二高度。
在一實施例中，該囊封物之該主表面可為一實質上平面表面，其上覆在一距其之至少實質上均勻之第二高度處的該第一表面之該第一區及該第二區且上覆該微電子元件。
在一變化中，至少一導電支柱可包括一遠離該微電子元件之尖端區，及一安置於該尖端區下方且更接近於該基板之第二區。該第二區及該尖端區可具有各別凹面圓周表面。該至少一支柱可本質上由金屬組成且具有一水平尺寸，該水平尺寸為該尖端區中之垂直位置的一第一函數且該水平尺寸為該第二區中之垂直位置的一第二函數。
在一實施例中，該等導電元件包括導電支柱或導電結合材料塊中之至少一者，且該囊封物之一部分上覆該第二表面。此部分可具有在一高於該第二表面之高度處的一主表面，及該主表面中之一凹座或一或多個開口中的至少一者。該凹座或該一或多個開口可至少部分地曝露用於電連接至其之該等導電元件中之至少一者。該等導電元件中之至少一些導電元件可彼此電絕緣且經調適以同時攜載不同電位。
在一或多個實施例中，該等導電支柱中之至少兩者的表面或至少兩個導電塊之表面至少部分地曝露於該等開口中的一單一開口內。
根據一實施例提供一種製成一微電子封裝之方法。此方法可包括提供一微電子總成，該微電子總成包括一基板、一黏著至該基板之微電子元件，及具有遠離該基板之頂表面的實質上硬質導電支柱。該等導電支柱中之第一導電支柱及第二導電支柱可藉由該基板之導電特徵部而電連接至該微電子元件，以用於在該第一導電支柱上攜載一第一信號電位且用於同時在該第二導電支柱上攜載一第二電位，該第二電位不同於該第一信號電位。可接著形成一囊封物層，該囊封物層上覆該微電子元件之至少一部分且覆蓋該等導電支柱之該等頂表面。可接著在該囊封物層中形成一凹座或一或多個開口中之至少一者。每一凹座或開口可與該等導電支柱中之至少一者對準且每一凹座或開口准許進行與該等導電支柱中之至少一者的一電連接。
在一實施例中，該囊封物層可接觸該等導電支柱且每一凹座或開口可至少部分地曝露該等導電支柱中之至少一者。
在一實施例中，至少一個別開口可至少部分地曝露該等導電支柱中之兩者或兩者以上。
該微電子總成可進一步包括與該等導電支柱中之各別者接合的導電塊。形成於該囊封物層中之每一凹座或開口可至少部分地曝露該等導電塊中之至少一者。在一特定實施例中，至少一個別開口可至少部分地曝露該等導電塊中之兩者或兩者以上。
該囊封物層可形成以具有一實質上平面表面，且該凹座或開口可自該實質上平面表面延伸或形成於該實質上平面表面中。
在一實施例中，該等導電支柱可具有遠離該等頂表面延伸之邊緣表面，且至少一導電支柱之該邊緣表面可至少部分地曝露於該等開口中的至少一者內。
在一特定實施例中，可製成至少第一微電子封裝及第二微電子封裝，且接著可將該第二微電子封裝堆疊於該第一微電子封裝之頂上，且該第一微電子封裝與該第二微電子封裝係使用該第一微電子封裝及該第二微電子封裝中之至少一者的該等導電支柱而電互連在一起。
在另一實例中，形成該囊封物層之該步驟可包括在該基板之一表面上方形成該囊封物層之第一實質上平面表面及第二實質上平面表面。該第一表面可上覆與該微電子元件對準的該基板之至少一部分且該第二表面可上覆超越該微電子元件之一邊緣的該基板之另一部分。該第一表面及該第二表面可具有不同於該基板之該表面的高度。
參看圖1A，根據本發明之實施例，微電子封裝包括基板100，基板100具有鄰近於微電子元件110之面114的第一表面或頂表面102及與第一表面或頂表面102相反的第二表面或底表面104。微電子元件110可為第一半導體晶片，其具有面向朝向圖1A中之圖式之頂部的向上方向的正面113，及面向相反的向後方向之背面114。背面114大體上平行於正面113。平行於正面113之方向在本文中被稱作「水平」或「橫向」方向；而垂直於正面之方向在本文中被稱作向上或向下方向且在本文中亦被稱作「垂直」方向。本文中所提及之方向係在所提及之結構的參考框架中。因此，此等方向可處於垂直參考框架或重力參考框架之任何定向下。一特徵部安置於比另一特徵部大的「高於表面」之高度處的陳述意謂：在遠離表面之相同正交方向上，一特徵部處於比另一特徵部大之距離處。相反地，一特徵部安置於比另一特徵部小的「高於表面」之高度處的陳述意謂：在遠離表面之相同正交方向上，一特徵部處於比另一特徵部小之距離處。
微電子元件110包括安置於鄰近於正面113之相對薄層中的主動電路元件。主動電路元件可包括諸如電晶體、二極體及其他元件之器件，及併有該等器件之電路。通常，主動電路元件具有大約幾微米或幾微米以下之尺寸。
基板100包括曝露於基板100之頂表面102處的第一導電支柱106，及曝露於基板100之第二表面104處的導電元件108。如本發明中所使用，「曝露於」介電元件之表面處的導電元件可與此表面齊平；相對於此表面凹入；或自此表面突出，只要可藉由在垂直於該表面之方向上朝向該表面移動一理論點而接取該導電元件以用於接觸即可。
在圖1A中所展示之實例中，導電元件108為導電焊墊。基板100可為可撓性的，且在一實施例中，基板100可由諸如聚醯亞胺之介電材料製成。通常具有導電性之基板亦可具有導電跡線(未圖示)，該等導電跡線在頂表面102、底表面104之上及/或在頂表面與底表面之間延伸。諸如半導體晶片之微電子元件110附接至基板100之第一表面102。如圖1A至圖1B中所見，微電子元件之接點117可使用諸如導線結合之導電元件112而與一或多個導電焊墊105電互連。又，導電焊墊105可與導電支柱106連接。該等導電支柱中之至少一些導電支柱彼此電絕緣且經調適以攜載不同電位，例如，不同信號或不同電壓(例如，電力、接地，或其組合)。黏接劑115可用於將微電子元件110之與正面(亦即，基板100之接觸承載面)相反的背面114附接至基板100。
當自基板之頂表面102上方檢視時，每一導電支柱之底座107可具有與結合層接觸之區域，該區域可大於支柱之頂表面126。底座107可具有(例如)圓形、橢圓形、長橢圓形，或其他矩形或多邊形形狀。頂表面126可界定支柱之尖端或頂點。安置於基板之頂表面102上方的頂表面或尖端可具有小於底座之區域。通常，當自頂表面102上方檢視時，尖端具有與底座相同之形狀。支柱之形狀相當任意，且可能不僅為平截頭圓錐形(亦即，為圓錐之一部分之截圓錐，其頂點沿著平行於底面或大體上平行於底面之面切斷，如諸圖式中所展示)。或者，導電支柱可具有圓柱形、圓錐形或任何其他類似形狀，諸如，具有圓頂部或平線區形狀之圓錐。此外，除具有圓形橫截面之三維(3D)形狀(其被稱為「迴轉體」，諸如截圓錐)之外或並非該三維(3D)形狀，支柱130可具有任意形狀，諸如具有多邊形水平橫截面之任何三維形狀。通常，可藉由改變光阻圖案、蝕刻條件或用以形成支柱之原始層或金屬箔之厚度來調整形狀。儘管支柱106之尺寸亦為任意的且不限於任何特定範圍，但常常，支柱106可形成以自基板100之曝露表面突出達50微米至300微米，且若支柱具有圓形橫截面，則可將直徑設定在幾十微米及大於幾十微米的範圍中。在一特定實施例中，支柱之直徑可在0.1 mm與10 mm之間的範圍內。在一特定實施例中，支柱106之材料可為銅或銅合金。銅合金可包括銅與任何其他一或多種金屬之合金。製造支柱及具有支柱之基板的結構及細節可如美國專利公開案2007-0148822中所描述。
通常，可藉由用遮罩14(圖1C)各向同性地蝕刻金屬層(例如，層壓至基板之箔)而形成支柱，遮罩14安置於金屬箔上或金屬箔上方，以使得蝕刻在金屬箔之厚度10之方向上自與遮罩14接觸的金屬箔表面向下(亦即，朝向下方的基板之頂表面102)繼續進行。蝕刻可繼續進行，直至基板100之頂表面102完全地曝露於支柱之間以使得每一支柱的頂表面126(圖1A)具有距基板之頂表面102的相同高度且頂表面126為共平面的為止。遮罩14之寬度12通常大於在與遮罩接觸之表面處的導電支柱106之寬度。
尖端之寬度135(圖2)在基板延伸所在的橫向方向111、113上可相同或不同。當在該兩個方向上寬度相同時，寬度可表示尖端之直徑。同樣地，底座之寬度137在金屬箔之橫向方向111、113上可相同或不同，且當寬度137相同時，寬度137可表示底座之直徑。在一實施例中，尖端可具有第一直徑，且底座可具有第二直徑，其中第一直徑與第二直徑之間的差可大於在支柱之尖端與底座之間延伸的支柱高度的25%。
圖1C說明在藉由完全地穿過金屬箔蝕刻以曝露下伏基板100而形成導電支柱106之後的基板。在一特定實例中，導電支柱可具有距幾十微米之高度及距幾十微米之橫向尺寸(例如，直徑)。在一特定實例中，高度及直徑可各自小於100微米。支柱之直徑小於導電焊墊之橫向尺寸。每一支柱之高度可小於或大於支柱之直徑。
圖1D說明一替代實施例，其中支柱40形成有具有寬度47之底座，當如參看圖1C所論述而形成支柱時，相對於支柱之高度46而言，寬度47可比底座之寬度137(圖1B)窄。因此，可獲得具有比如上文所論述而形成之支柱大的高度對寬度縱橫比之支柱40。在一特定實施例中，可藉由使用遮蔽層48蝕刻分層結構(圖1E)之多個部分而形成支柱40，其中該分層結構包括第一金屬箔50、第二金屬箔52及安置於(例如，包夾於)第一金屬箔與第二金屬箔之間的蝕刻障壁層54。所得支柱40可具有上部支柱部分42及下部支柱部分44，且可具有安置於上部支柱部分與下部支柱部分之間的蝕刻障壁層45。在一實例中，金屬箔本質上由銅組成，且蝕刻障壁45本質上由不受侵蝕銅之蝕刻劑侵蝕的金屬(諸如，鎳)組成。或者，蝕刻障壁45可本質上由可藉由用以圖案化金屬箔之蝕刻劑蝕刻的金屬或金屬合金組成(除了蝕刻障壁45比金屬箔蝕刻得更緩慢以外)。以此方式，當根據遮蔽層48蝕刻第一金屬箔以界定上部支柱部分42時，蝕刻障壁保護第二金屬箔52免受侵蝕。接著，移除蝕刻障壁45之曝露超越上部支柱部分42之邊緣43的多個部分，此後使用上部支柱部分作為遮罩蝕刻第二金屬箔52。
所得支柱40可包括具有第一邊緣之第一蝕刻部分，其中該第一邊緣具有第一曲率半徑R1。支柱40亦具有在第一蝕刻部分與基板之頂表面之間的至少一第二蝕刻部分，其中該第二蝕刻部分具有第二邊緣，該第二邊緣具有不同於第一曲率半徑之第二曲率半徑R2。可藉以描述支柱40之另一方式在於：每一導電支柱包括遠離基板之尖端區，及安置於該尖端區下方更接近於基板之第二區，該第二區及該尖端區具有各別凹面圓周表面，且每一固體金屬支柱具有水平尺寸，該水平尺寸為尖端區中之垂直位置的第一函數且該水平尺寸為第二區中之垂直位置的第二函數。
在一實施例中，當蝕刻第二金屬箔以形成下部支柱部分時，上部支柱部分42可部分地或完全地被保護以免受進一步侵蝕。舉例而言，為了保護上部支柱部分，可在蝕刻第二金屬箔之前，對上部支柱部分之(多個)邊緣43塗覆抗蝕刻材料。形成類似於支柱40(圖1D中所展示)之經蝕刻之金屬支柱的進一步描述及方法描述於在2007年3月13日申請之共同擁有的美國申請案11/717,587(Tessera 3.0-358 CIP CIP)中，該申請案之揭示內容以引用的方式併入本文中。
在一實例中，開始結構不需要包括包夾於第一金屬箔與第二金屬箔之間的蝕刻障壁層。實情為，可藉由不完全地蝕刻(例如，「半蝕刻」)金屬箔以使得金屬箔之突出部分32(圖1F)被界定以及在突出部分之間的凹座33(其中金屬箔已曝露至蝕刻劑)被界定來形成上部支柱部分。在曝光及顯影作為遮蔽層56之光阻之後，可蝕刻箔58，如圖1F中所展示。一旦達到蝕刻之某一深度，便中斷蝕刻製程。舉例而言，可在預定時間之後終止蝕刻製程。蝕刻製程留下遠離基板100向上突出的第一支柱部分32，其中凹座33界定於該等第一部分之間。隨著蝕刻劑侵蝕箔58，蝕刻劑移除在遮蔽層56之邊緣之下的材料，從而允許遮蔽層自第一支柱部分32之頂部(指示為懸垂物30)橫向地突出。第一遮蔽層56保持處於特定位置(如所展示)。
一旦箔58已被蝕刻至所要深度，便將第二光阻層34(圖1G)沈積至箔58之曝露表面上。在此例子中，可將第二光阻34沈積至箔58內之凹座33上(亦即，在箔先前已被蝕刻之位置)。因此，第二光阻34亦覆蓋第一支柱部分32。在一實例中，可使用電泳沈積製程來在箔58之曝露表面上選擇性地形成第二光阻層。在此狀況下，可將第二光阻34沈積至箔上而不覆蓋第一光阻遮蔽層56。
在下一步驟，將具有第一光阻56及第二光阻34之基板曝露至輻射且接著使第二光阻顯影。如圖1H中所展示，第一光阻56可在箔58之多個部分之上橫向地突出(藉由懸垂物30指示)。此懸垂物30防止第二光阻34被曝露至輻射且由此防止第二光阻34被顯影及移除，從而引起第二光阻34之多個部分黏附至第一支柱部分32。因此，第一光阻56充當第二光阻34之遮罩。藉由洗滌使第二光阻34顯影以便移除輻射曝露之第二光阻34。此情形在第一支柱部分32上留下第二光阻34之未曝露部分。
一旦第二光阻34之多個部分已被曝露及顯影，便執行第二蝕刻製程，從而移除箔58之額外部分，藉此在第一支柱部分32下方形成第二支柱部分36，如圖1I中所展示。在此步驟期間，仍黏附至第一支柱部分32之第二光阻34保護第一支柱部分32免於被再次蝕刻。此後，可移除第一光阻遮罩56及第二光阻遮罩34，從而留下自基板100之主表面突出的支柱60。
可按需要將此等步驟重複達許多次以產生形成第三支柱部分、第四支柱部分或第n支柱部分之較佳縱橫比及間距。當到達基板100時，可停止該製程，此層可充當蝕刻終止層或抗蝕刻層。作為最後的步驟，可分別完整地剝離第一光阻58及第二光阻34。
以此方式，可形成具有類似於支柱40(圖1D)之形狀之形狀的支柱60(圖1I)，但不需要在上部支柱部分與下部支柱部分之間提供內部蝕刻障壁45(如圖1D中所見)。使用此方法，可製造具有多種形狀之支柱，其中上部支柱部分與下部支柱部分可具有類似直徑，或上部支柱部分之直徑可大於或小於下部支柱部分的直徑。在一特定實施例中，藉由使用上文所描述的技術自支柱之尖端至支柱之底座接連地形成支柱的多個部分，支柱之直徑可自尖端至底座逐漸變小或可自尖端至底座逐漸變大。
藉由上文所描述之製程(圖1F至圖1I)所形成的支柱60可如圖2中所展示。每一支柱60可具有處於或鄰近於尖端區之第一部分32，及下伏於第一部分且更接近於基板表面的第二部分36。第一部分32之圓周表面22及第二部分36之圓周表面24為凹面表面，且各自具有一斜率或dX/dZ，該斜率或dX/dZ至多隨著Z方向(高於基板表面之高度之方向)上的位置漸漸地改變。關於本文中所描述的支柱之圓周表面中之每一者(例如，表面22或表面24)，「凹面」意謂在圓周表面之邊界之間的每個高度處(例如，在圓周表面22之上部邊界19與彼圓周表面22之下部邊界21之間的每個高度29處)，圓周表面封閉之直徑25小於相同高度29處由藉由在該等邊界之間延伸的一系列直線所界定的理論圓錐形表面所封閉的直徑。舉例而言，在邊界19、21之間的圓周表面22上之每個點處於自理論圓錐形表面26向內處，理論圓錐形表面26係藉由延伸穿過邊界19、21之一系列直線界定。
替代於藉由蝕刻形成支柱(如上文所描述之製程中)，亦有可能藉由電鍍製程形成支柱，在電鍍製程中，在基板之頂表面上沈積諸如光阻層之犧牲層，此後藉由光微影在該犧牲層中形成開口。該等開口界定可電鍍金屬以形成支柱所在的位置。通常，藉由此方法所形成之支柱自底座至尖端具有均勻的橫截面，且可為(例如)圓柱形形狀。
參看圖3，一旦形成支柱，便可將基板100置放於模之頂板120與底板116之間。頂板120定位於底板116之上以用於將基板100俘獲於其間。特定言之，可將模之頂板120置放為與基板之第一表面102接觸，且可將模之底板116置放為與基板100之第二表面104接觸。模頂板120可包括入口122，入口122使得能夠將可流動材料引入至藉由模底板116與模頂板120所界定之空腔124中。
可將模之頂板120相抵於基板之頂表面102按壓，以界定具有一體積之內部空腔124。可將頂板120之內表面128與導電支柱106之頂表面126並置並間隔開。底板116可在模製製程期間提供相抵於基板100之反作用力。接著，可經由入口122將可固化可流動材料(諸如，可固化囊封物)引入至模之空腔124中。可固化囊封物可為透明的、不透明的或具有介於透明與不透明之間的尺度的光學性質。舉例而言，當微電子元件110包括發射或接收可見光波長波譜之主動器件時，囊封物可為透明的。可固化材料較佳經固化以形成固化囊封物層，該固化囊封物層較佳對封裝提供穩定性且保護微電子元件110、導電導線結合112及導電支柱106。
參看圖4，導電支柱106之頂表面126延伸至距基板100之頂表面102的第一高度H1。在模製之後，囊封物130可具有在高度H2處之主表面134，主表面134足以覆蓋半導體晶片110、導線結合112及導電支柱106。在圖4中所展示之特定實施例中，主表面134可處於距微電子元件黏著至的表面102之第一區以及導電支柱126突出超過的表面102之第二區的均勻高度處。高於基板100之頂表面102的導電支柱106高度H1小於囊封物主表面之高度H2，以使得導電支柱之頂表面126內埋於主表面134下方。
圖5說明微電子封裝180之製造之後續步驟，其中開口136形成於囊封物主表面134中，開口136至少部分地曝露導電支柱106。在一實施例中，可在囊封物已固化之後形成開口136。或者，在一變化中，可在自模移除封裝之後(彼時，囊封物可能僅部分固化)形成開口136。在此變化中，可在於囊封物中形成開口136之後發生囊封物之完全固化。如圖5中特別展示，開口136可形成以便至少部分地曝露頂表面126，而且至少部分地曝露個別導電支柱的邊緣表面138。為了達成此目的，可使用雷射來切除在導電支柱106之頂表面上方的囊封物材料以便形成開口136。機械鑽孔或蝕刻為在囊封物中形成開口之其他可能方式。
該等開口可形成以便完全地或部分地曝露該等導電支柱中之一或多者。在一特定實例中，該等開口中之至少一者可僅部分地曝露單一導電支柱。以此方式，開口可在囊封物層中提供管道，該管道使導電支柱與電路面板之對應導電元件或導電支柱可連接至之其他元件(例如，另一微電子封裝)之間的電連接絕緣。
在一特定狀況下，一開口可曝露一個以上導電支柱。在一個此實例中，一完整支柱列或此列之一部分可曝露於或部分地曝露於囊封物之一開口中。在另一實例中，複數個支柱列或複數個支柱列之多個部分可曝露於或部分地曝露於囊封物之主表面中的一開口中。在一特定實例中，一起曝露於或部分地曝露於單一開口中或各別開口中的複數個導電支柱可連接至處於相同電位之一或多個導電元件，(諸如)以用於進行接地或電力連接。然而，在一實施例中，單一開口可至少部分地曝露攜載不同信號之複數個支柱，以使得(例如)可藉由至少部分地一起曝露於囊封物中之單一開口內的至少兩個支柱同時攜載電力、接地或信號中之至少兩者的組合。圖5進一步說明導電塊，例如，與基板之導電焊墊108接合的焊球208。焊球208可與導電支柱對準以用於接合至導電支柱，如下文將進一步描述。除非另外註明，否則焊球與基板之導電元件(例如，焊墊等)之接合隱含於下文所展示的實施例中。
在一特定實施例(圖5A)中，其中至少兩個支柱106至少部分地曝露於單一開口236內，可使用鋸來形成在一或多個水平方向上跨越基板表面102延伸之開口236。在此狀況下，導電支柱之頂表面126'可曝露於該開口內。在特定實施例中，導電支柱之頂表面126'可安置於開口內的囊封物層之表面238上方、表面238下方，或可與表面238齊平。在圖5A中所展示之特定實施例中，開口236並不水平地延伸至囊封物層之一周邊邊緣，亦即，至囊封物層之周邊邊緣131(如圖5中所展示)。在如圖5B中所見的一變化中，可使用鋸或其他構件來在囊封物層中形成凹座336，凹座336確實延伸至囊封物層之周邊邊緣131且至少部分地曝露導電支柱106中的一者或複數者。在特定實施例中，導電支柱106之頂表面126'可安置於囊封物層之凹入表面338上方、凹入表面338下方，或可與凹入表面338齊平。
圖6展示圖5中所展示的實施例之變化。在此實施例中，以使得導電支柱106之頂表面126僅部分地曝露於每一開口140內的方式形成開口140。如圖6中所見，支柱之頂表面126之部分142處於開口140與邊緣表面138之間。在形成該等開口之後，導電支柱之頂表面之此等部分142保持內埋於固化囊封物層130內。此外，在圖6中所說明之實施例中，導電支柱之邊緣表面138內埋於囊封物內。
圖7說明又一變化，其中導電塊144(例如，諸如錫之結合金屬、焊料或其他結合材料)接觸導電支柱之頂表面126及邊緣表面138。形成於固化囊封物材料130中之開口146至少部分地曝露導電塊144，且亦可曝露支柱106之多個部分。
圖8說明根據圖5中所展示之微電子封裝之變化的微電子封裝200。在此狀況下，囊封物130形成以具有複數個區，該複數個區具有在距基板100之頂表面102之不同高度處的主表面。如圖8中所見，囊封物130包括中央區147，中央區147具有在高度150處之主表面148，主表面148足以覆蓋半導體晶片110及導線結合112。如圖8中特別展示，封裝可包括複數個微電子元件110，例如，經堆疊且與導電元件(例如，基板100之導電焊墊)電連接之半導體晶片。或者，類似於圖5中所展示之實施例，微電子封裝可包括單一微電子元件110。
囊封物130亦包括周邊區151，周邊區151自中央區147朝向基板100之周邊邊緣156延伸。周邊區151中的囊封物之主表面152具有高度154，高度154小於中央區中的囊封物之高度150。通常，在類似於圖3中所展示之方法的方法中，藉由用以形成囊封物之模之頂板120A的形狀來判定中央區147及周邊區151中的囊封物之主表面的高度。參看圖9，為了形成具有不同高度的囊封物材料之中央區及周邊區，模之頂板120A之內表面128A處於的在微電子元件110及導線結合112上方之位置處距基板頂表面102的高度大於頂板120A之內表面128B處於的在導電支柱106上方距基板頂表面102的高度。
或者，在一變化中，可形成在中央區147與周邊區151兩者中具有在均勻高度150處之主表面的囊封物層，且接著可使用鋸或其他構件來將周邊區中的囊封物層之高度減小至較低高度154。
圖10說明圖8中所展示的微電子封裝之變化，其中導電支柱106之頂表面僅部分地曝露於囊封物材料中之開口140內，類似於上文關於圖6所描述的實施例。
圖11說明圖8中所展示的微電子封裝之變化，其中接合至導電支柱106的導電塊144表面至少部分地曝露於囊封物材料中之開口146內，類似於上文關於圖7所描述的實施例。
圖12展示堆疊於其他微電子封裝之頂部上的圖8之微電子封裝。特定言之，第一微電子封裝200A堆疊於第二微電子封裝200B之頂上，第二微電子封裝200B又堆疊於第三微電子封裝200C之頂上。第三微電子封裝又堆疊於第四微電子封裝200D之頂上。該四個微電子封裝較佳彼此電互連。第一微電子封裝200A之導電塊208A(例如，焊球)與第二微電子封裝200B之導電支柱106B接觸。在組裝期間，可使導電塊208A之溫度升高以便至少部分地變換成熔融狀態，以使得可將導電支柱106B至少部分地插入於導電塊208A中且藉此將導電支柱106B與導電塊208A接合至彼此。接著可降低導電塊208A之溫度，以使得導電塊重新凝固以用於經由導電支柱106B及導電塊208A而永久性地連接基板200A與基板200B。以類似型式進行第二微電子封裝200B與第三微電子封裝200C之間的電連接，亦以類似方式進行第三微電子封裝200C與第四微電子封裝200D之間的電互連。通常，關於總成中之所有封裝，同時進行用以形成總成中之電連接的微電子封裝之接合。然而，可僅關於該等封裝之一子集進行微電子封裝之接合，且接著應用進一步接合製程以將額外封裝或封裝之一或多個子集接合至其。儘管圖12展示包括堆疊於彼此之頂上之四個微電子封裝的總成，但本發明預期可製造兩個或兩個以上微電子封裝之任何大小的總成。舉例而言，在一實施例中，五個或五個以上微電子封裝之堆疊可為可能的。堆疊中之最高封裝或最低封裝可電連接至外部元件(諸如，電路板或測試板)，亦即，經由焊球、其他導電塊或支柱等。視情況，如圖12中所見，可製成總成中之最高微電子封裝200A，而導電元件(諸如，導電支柱、導電塊等)並未曝露於此封裝200A之頂表面152A處。在將個別微電子封裝一起組裝於堆疊中之前，可個別地測試每一封裝。
圖13展示根據圖8中所展示之實施例之變化的微電子封裝。在此狀況下，導電塊(例如，焊球218)曝露於封裝之頂表面102處。囊封物層130上覆一微電子元件或複數個微電子元件110A、110B之一面。
額外囊封物層230上覆基板100之底表面104，具有曝露導電支柱108之頂表面226的開口240，導電支柱108遠離基板100之底表面104突出。類似於上文所描述之實施例(圖5)的囊封物層130中之開口136，開口240可曝露導電支柱之頂表面226且部分地曝露導電支柱的邊緣表面238。視情況，可將導電塊(尤其例如，焊料塊、錫、導電膏)與導電支柱108之表面接合。可以類似於上文關於圖12所描述之方式的方式將圖13中所說明的微電子封裝300與一或多個其他微電子封裝堆疊及接合。
在圖13中所說明的實施例之變化中，可藉由導電支柱來替換導電塊218，諸如上文所描述。在另一變化中，導電支柱108之頂表面226可僅部分地曝露於開口240內，類似於上文關於圖6所展示及描述的導電支柱106及開口140之配置。在又一變化中，可在將總成置放至模中之前，將包括第二導電支柱108之頂表面226及邊緣表面238的表面與導電塊接合，類似於上文關於圖7所展示及描述之配置。在此狀況下，開口240至少部分地曝露與第二導電支柱接合之導電塊，類似於圖8中所展示之配置(在該配置中，導電塊144部分地曝露於開口146內)。可將此等變化中之每一者與上文關於上述諸圖中之任一者所展示及描述的特徵部組合。儘管本發明不受任何特定操作理論限制，但咸信，導電塊之平坦化將實現關於複數個微電子封裝的大量生產，每一封裝具有一標準高度。圖5、圖5A、圖5B、圖6、圖7、圖8、圖10、圖11及圖13中之任一者中所展示的結構可堆疊於其他微電子封裝之頂上以形成堆疊總成，類似於圖12中所展示的堆疊總成。
在上文所描述的實施例之另一變化中，可將微電子元件110之接觸承載面113(圖1A)置放為鄰近於基板100之頂表面102，且可以覆晶方式將接點117與曝露於基板之頂表面102處的基板接點以對準方式並置，微電子元件之接點117與曝露於基板之頂表面處的接點以導電方式結合。可將此配置與上文中所描述的實施例及其變化中之任一者組合。此外，在上文(圖5、圖5A、圖5B、圖6、圖7、圖8、圖10、圖11及圖12)所展示及描述之實施例中，替代於導電塊108遠離基板底表面突出，微電子封裝可改為具有諸如上文所描述之導電支柱，或可與處於適當位置中之導電塊(例如，導電結合材料塊，諸如錫、焊料、導電膏等)組合的支柱。上文所描述之實施例可應用於的微電子封裝之其他細節包括2005年12月23日申請之美國申請案11/318,404(Tessera 3.0-484)，該案之揭示內容以引用的方式併入本文中。
較佳實施例之上述描述意欲說明而非限制本發明。製造微電子封裝之特定方法及其中的結構可如Belgacem Haba之於2010年7月19日申請的題為「具有區域陣列單元連接器之可堆疊模製微電子封裝(STACKABLE MOLDED MICROELECTRONIC PACKAGES WITH AREA ARRAY UNIT CONNECTORS)」之共同擁有的美國申請案第12/839,038號中進一步描述，該案之揭示內容以引用的方式併入本文中。
儘管已參考特定實施例描述本文中之本發明，但應理解，此等實施例僅說明本發明之原理及應用。因此，應理解，可對說明性實施例進行眾多修改，且可在不脫離如藉由附加申請專利範圍所界定的本發明之精神及範疇的情況下設計出其他配置。
10．．．金屬箔之厚度
12．．．遮罩之寬度
14．．．遮罩
19．．．圓周表面之上部邊界
21．．．圓周表面之下部邊界
22．．．第一部分之圓周表面
24．．．第二部分之圓周表面
25．．．圓周表面封閉之直徑
26．．．理論圓錐形表面
29．．．高度
30．．．懸垂物
32．．．金屬箔之突出部分/第一支柱部分
33．．．凹座
34．．．第二光阻層/第二光阻遮罩
36．．．第二支柱部分
40．．．支柱
42．．．上部支柱部分
43．．．邊緣
44．．．下部支柱部分
45．．．內部蝕刻障壁/蝕刻障壁層
46．．．支柱之高度
47．．．寬度
48．．．遮蔽層
50．．．第一金屬箔
52．．．第二金屬箔
54．．．蝕刻障壁層
56．．．遮蔽層/第一光阻遮罩
58．．．箔
60．．．支柱
100．．．基板
102．．．第一表面或頂表面
104．．．第二表面或底表面
105．．．導電焊墊
106．．．導電支柱
106B．．．導電支柱
107．．．底座
108．．．導電元件/導電焊墊/導電支柱
110．．．微電子元件/半導體晶片
110A．．．微電子元件
110B．．．微電子元件
111．．．橫向方向
112．．．導電元件/導電導線結合
113．．．正面/橫向方向
114．．．面/背面
115．．．黏接劑
116．．．底板
117．．．接點
120．．．頂板
120A．．．頂板
122．．．入口
124．．．空腔
126．．．導電支柱之頂表面
126'．．．導電支柱之頂表面
128．．．頂板之內表面
128A．．．頂板之內表面
128B．．．頂板之內表面
130．．．囊封物/囊封物層
131．．．囊封物層之周邊邊緣
134．．．主表面
135．．．尖端之寬度
136．．．開口
137．．．底座之寬度
138．．．導電支柱之邊緣表面
140．．．開口
142．．．支柱之頂表面之部分
144．．．導電塊
146．．．開口
147．．．中央區
148．．．主表面
150．．．高度
151．．．周邊區
152．．．囊封物之主表面
152A．．．封裝之頂表面
154．．．高度
156．．．基板之周邊邊緣
180．．．微電子封裝
200．．．微電子封裝
200A．．．第一微電子封裝/基板
200B．．．第二微電子封裝/基板
200C．．．第三微電子封裝
200D‧‧‧第四微電子封裝
208‧‧‧焊球
208A‧‧‧導電塊
218‧‧‧焊球/導電塊
226‧‧‧導電支柱之頂表面
230‧‧‧囊封物層
236‧‧‧開口
238‧‧‧囊封物層之表面/導電支柱之邊緣表面
240‧‧‧開口
300‧‧‧微電子封裝
336‧‧‧凹座
338‧‧‧囊封物層之凹入表面
R1‧‧‧第一曲率半徑
R2‧‧‧第二曲率半徑
圖1A為說明穿過圖1B之線1A-1A之微電子總成的截面圖；
圖1B為說明圖1A中所展示之微電子總成的俯視平面圖；
圖1C為說明根據本發明之實施例所形成之導電支柱的部分截面圖；
圖1D為說明根據圖1C中所展示之支柱之變化的支柱之部分截面圖；
圖1E為說明形成如圖1D中所展示之支柱之方法的部分截面圖；
圖1F、圖1G、圖1H及圖1I為說明與支柱之形成有關的製造方法中之階段的部分截面圖；
圖2為進一步說明如圖1I中所展示之支柱的部分斷裂截面圖；
圖3為說明根據本發明之實施例的製造微電子封裝之方法中之模製階段的截面圖；
圖4為說明在圖3中所展示之階段之後的製造方法之階段的截面圖；
圖5為說明根據本發明之實施例之微電子封裝的截面圖；
圖5A為說明根據圖5中所展示的本發明之實施例之變化的微電子封裝之截面圖；
圖5B為說明根據圖5中所展示的本發明之實施例之另一變化的微電子封裝之截面圖；
圖6為說明根據圖5中所說明之實施例之變化的微電子封裝之截面圖；
圖7為說明根據圖5中所說明之實施例之變化的微電子封裝之截面圖；
圖8為說明根據圖5中所說明之實施例之變化的微電子封裝之截面圖；
圖9為說明根據圖3中所展示之實施例之變化的製造微電子封裝之方法中之模製階段的截面圖；
圖10為說明根據圖6中所說明之實施例之變化的微電子封裝之截面圖；
圖11為說明根據圖7中所說明之實施例之變化的微電子封裝之截面圖；
圖12為說明根據本發明之實施例的經堆疊之微電子總成的截面圖；及
圖13為說明根據圖8中所說明之實施例之變化的微電子封裝之截面圖。
102．．．第一表面或頂表面
110．．．微電子元件/半導體晶片
112．．．導電元件/導電導線結合
130．．．囊封物/囊封物層
147．．．中央區
148．．．主表面
150．．．高度
151．．．周邊區
152．．．囊封物之主表面
154．．．高度
156．．．基板之周邊邊緣
200．．．微電子封裝

Claims (19)

  1. 一種微電子封裝，其包含：一基板，其具有一第一表面及一遠離該第一表面之第二表面；一微電子元件，其上覆該第一表面；一導電支柱，其突出超過該第一表面或該第二表面中之至少一者，該導電支柱具有一頂表面及一或多個邊緣表面，該頂表面遠離該基板，該一或多個邊緣表面從該基板延伸到該導電支柱的頂表面；一導電結合金屬，其接觸該導電支柱的頂表面及邊緣表面；導電元件，其曝露於該基板之第二表面處，該等導電元件與該微電子元件電互連；及一囊封物，其上覆該微電子元件之至少一部分及該導電支柱突出超過的該基板之該表面，該囊封物具有一開口，該開口部分地曝露該導電接合金屬。
  2. 如請求項1之微電子封裝，其中該導電結合金屬包括焊料。
  3. 如請求項1之微電子封裝，其中該導電支柱具有平截頭圓錐的形狀。
  4. 如請求項1之微電子封裝，其中該第一表面或該第二表面中之至少一者具有一第一區域和從該第一區域延伸的一第二區域，該微電子元件上覆該第一區域，且該導電支柱與該第二區域對其並且突出至高於該第二表面的一 第一高度，該囊封物接觸該導電支柱且在該第二區域上的一第二高度處具有一主表面，該第二高度大於該第一高度，其中該囊封物中之該開口為該主表面中之開口。
  5. 如請求項4之微電子封裝，其中該囊封物之該主表面為一實質上平面表面，該囊封物進一步具有在高於該第一表面之一第三高度處的一上覆該微電子元件之第二表面，該第三高度不同於該第二高度。
  6. 如請求項5之微電子封裝，其中該第三高度大於該第二高度。
  7. 如請求項1之微電子封裝，其中該囊封物之該主表面為一實質上平面表面，其上覆在一距其之至少實質上均勻之第二高度處的該第一表面之該第一區及該第二區且上覆該微電子元件。
  8. 如請求項1之微電子封裝，其中該第一表面或該第二表面的至少一者具有一第一區域和和從該第一區域延伸的一第二區域，該微電子元件上覆該第一區域，且該導電支柱與該第二區域對準並在該第二區域上方突出至一第一高度，且其中該導電支柱包括一遠離該微電子元件之尖端區，及一安置於該尖端區下方且更接近於該基板之第二區，該第二區及該尖端區具有各別凹面圓周表面，且該導電支柱本質上由金屬組成且具有一水平尺寸，該水平尺寸為該尖端區中之垂直位置的一第一函數且該水平尺寸為該第二區中之垂直位置的一第二函數。
  9. 如請求項1之微電子封裝，其中該等導電元件包括導電 支柱或導電結合材料塊中之至少一者，且該囊封物之一部分上覆該第二表面且進一步具有複數個第二開口，每一第二開口部分地曝露該等導電元件中之至少一者，其中該等導電元件中之至少一些導電元件彼此電絕緣且經調適以同時攜載不同電位。
  10. 如請求項1之微電子封裝，其中該導電結合金屬包括焊料。
  11. 如請求項1之微電子封裝，其中該導電結合金屬上覆該導電支柱。
  12. 一種微電子封裝，其包含：一基板，其具有一第一表面及一遠離該第一表面之第二表面；一微電子元件，其上覆該第一表面；一焊料塊，其突出超過該第一表面或該第二表面中之至少一者，該導電塊具有遠離該基板之一頂表面；導電元件，其曝露於該基板的該第二表面處，該等導電元件與該微電子元件電互連；及一囊封物，其上覆該微電子元件之至少一部分及該導電塊突出超過的該基板之該表面，該囊封物具有一漸細的開口，該漸細的開口部分地曝露該焊料塊的該頂表面。
  13. 如請求項12之微電子封裝，其中該導電塊的該頂表面實質上為平坦的。
  14. 一種製成一微電子封裝之方法，其包含：提供一微電子總成，該微電子總成包括一基板、一安裝至該基板之微電子元件，及具有遠離該基板之頂表面和遠離該頂表面朝著該基板延伸的邊緣表面的金屬支柱，且該等金屬支柱具有平截頭圓錐的形狀，其中該等金屬支柱中之第一金屬支柱及第二金屬支柱藉由該基板的導電特徵而與該微電子元件電連接，以用於在該第一金屬支柱上攜載一第一信號電位且用於同時在該第二金屬支柱上攜載一第二電位，該第二電位不同於該第一信號電位；接著形成一囊封物層，該囊封物層上覆該基板之至少一部分和上覆該微電子元件之至少一部分，且覆蓋該等金屬支柱之該等頂表面和該等邊緣表面；及接著在該囊封物層中形成多個開口，每一個開口與該等導電支柱中之至少一者對準，該每一個開口准許與該等導電支柱中之至少一者進行一電連接。
  15. 如請求項14之方法，其中該囊封物層接觸該等金屬支柱，且形成該等多個開口包括形成一開口，其係部分地暴露該等金屬支柱的至少一者。
  16. 如請求項14之方法，其中該微電子總成進一步包括導電塊，其係與該等金屬支柱的個別金屬支柱接合，並且形成於該囊封物層中的該等開口的每一開口至少部分地暴露該等導電塊的至少一者。
  17. 如請求項14之方法，其中至少第一微電子封裝和第二微 電子封裝係被製成，該方法進一步包括堆疊該第二微電子封裝於該第一微電子封裝之上，該第一微電子封裝和該第二微電子封裝係利用該第一微電子封裝和該第二微電子封裝的至少一者中的金屬支柱而電性互連在一起。
  18. 如請求項14之方法，其中形成該囊封物層的步驟包括在該基板的表面上方形成該囊封物層的實質平坦的第一表面和第二表面，該第一表面上覆該基板與該微電子元件對齊的至少一部分，且該第二表面上覆該基板超過該微電子元件的一邊緣的另一部分，該第一表面和該第二表面具有與該基板的表面不同的高度。
  19. 如請求項14之方法，其中該等導電塊為焊料塊，其接觸該等金屬支柱的該等頂表面和該等邊緣表面。
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US9123664B2 (en) 2015-09-01
WO2012012323A2 (en) 2012-01-26
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JP2018026584A (ja) 2018-02-15
US20120013000A1 (en) 2012-01-19
JP6431967B2 (ja) 2018-11-28
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US20150364406A1 (en) 2015-12-17
TW201209939A (en) 2012-03-01
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US8482111B2 (en) 2013-07-09
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US20140008790A1 (en) 2014-01-09
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US9570382B2 (en) 2017-02-14
US20150084188A1 (en) 2015-03-26
WO2012012323A3 (en) 2012-07-05

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