JP6743149B2 - 導電性バリアのダイレクトハイブリッドボンディング - Google Patents

導電性バリアのダイレクトハイブリッドボンディング Download PDF

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JP6743149B2
JP6743149B2 JP2018529502A JP2018529502A JP6743149B2 JP 6743149 B2 JP6743149 B2 JP 6743149B2 JP 2018529502 A JP2018529502 A JP 2018529502A JP 2018529502 A JP2018529502 A JP 2018529502A JP 6743149 B2 JP6743149 B2 JP 6743149B2
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conductive barrier
barrier material
layer
conductive
metal contact
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JP2018528622A5 (enExample
JP2018528622A (ja
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ポール エム エンクイスト
ポール エム エンクイスト
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インヴェンサス ボンディング テクノロジーズ インコーポレイテッド
インヴェンサス ボンディング テクノロジーズ インコーポレイテッド
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    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
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    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
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    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01933—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01935—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938—Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
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    • H10W72/01951—Changing the shapes of bond pads
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    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
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    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
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    • H10W80/743—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having disposition changed during the connecting
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Wire Bonding (AREA)
JP2018529502A 2015-08-25 2016-08-25 導電性バリアのダイレクトハイブリッドボンディング Active JP6743149B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/835,379 US9953941B2 (en) 2015-08-25 2015-08-25 Conductive barrier direct hybrid bonding
US14/835,379 2015-08-25
PCT/US2016/048609 WO2017035321A1 (en) 2015-08-25 2016-08-25 Conductive barrier direct hybrid bonding

Publications (3)

Publication Number Publication Date
JP2018528622A JP2018528622A (ja) 2018-09-27
JP2018528622A5 JP2018528622A5 (enExample) 2019-10-03
JP6743149B2 true JP6743149B2 (ja) 2020-08-19

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US (6) US9953941B2 (enExample)
EP (1) EP3341956A4 (enExample)
JP (1) JP6743149B2 (enExample)
KR (2) KR102408487B1 (enExample)
CN (2) CN114944376A (enExample)
TW (1) TWI702659B (enExample)
WO (1) WO2017035321A1 (enExample)

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US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
EP2597670B1 (de) 2010-03-31 2016-03-30 EV Group E. Thallner GmbH Verfahren zum permanenten Verbinden zweier Metalloberflächen
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
FR3011679B1 (fr) * 2013-10-03 2017-01-27 Commissariat Energie Atomique Procede ameliore d'assemblage par collage direct entre deux elements, chaque element comprenant des portions de metal et de materiaux dielectriques
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9455182B2 (en) 2014-08-22 2016-09-27 International Business Machines Corporation Interconnect structure with capping layer and barrier layer
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
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