WO2011108436A1 - 半導体装置及び半導体装置用接合材 - Google Patents

半導体装置及び半導体装置用接合材 Download PDF

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Publication number
WO2011108436A1
WO2011108436A1 PCT/JP2011/054133 JP2011054133W WO2011108436A1 WO 2011108436 A1 WO2011108436 A1 WO 2011108436A1 JP 2011054133 W JP2011054133 W JP 2011054133W WO 2011108436 A1 WO2011108436 A1 WO 2011108436A1
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Prior art keywords
semiconductor device
layer
bonding material
semiconductor
substrate
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PCT/JP2011/054133
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English (en)
French (fr)
Inventor
克昭 菅沼
声俊 金
Original Assignee
国立大学法人大阪大学
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Application filed by 国立大学法人大阪大学 filed Critical 国立大学法人大阪大学
Priority to JP2012503096A priority Critical patent/JP5773344B2/ja
Priority to KR1020127025457A priority patent/KR101559617B1/ko
Priority to US13/581,941 priority patent/US9217192B2/en
Priority to EP11750546.1A priority patent/EP2544225A4/en
Publication of WO2011108436A1 publication Critical patent/WO2011108436A1/ja

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    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C18/00—Alloys based on zinc
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/52—Mounting semiconductor bodies in containers
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
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    • B23K35/282—Zn as the principal constituent
    • C—CHEMISTRY; METALLURGY
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Definitions

  • the present invention relates to a semiconductor device in which a semiconductor member is stacked on a substrate, and a semiconductor device bonding material for bonding the semiconductor member and the substrate.
  • Patent Document 1 discloses a semiconductor device in which a semiconductor element is die-attached to a die pad.
  • the semiconductor device of Patent Document 1 uses lead having a low melting point as a main component of the bonding material.
  • a power module used in a hybrid vehicle generates heat in the device itself due to a large current and is close to the engine, and thus is in a severe temperature environment. Therefore, it is used as a bonding agent for die attach of a next generation power semiconductor (SiC semiconductor chip) that is assumed to be used at a high temperature of 200 ° C. or higher, and cannot be used as a bonding material.
  • SiC semiconductor chip next generation power semiconductor
  • the present invention provides compound semiconductor devices such as GaN semiconductors and SiC semiconductors that have been developed as next-generation power semiconductors, and semiconductor device bonding materials with excellent heat resistance stability as bonding materials for die attach of semiconductor devices. Objective.
  • a characteristic configuration of a semiconductor device according to the present invention is a semiconductor device in which a semiconductor member is stacked on a substrate, and the semiconductor member and the substrate are for a semiconductor device whose main component is zinc. Bonded via a bonding material.
  • a bonding material for a semiconductor device containing lead as a main component has been used for bonding a semiconductor member and a substrate.
  • these bonding materials for semiconductor devices have a low melting point, and are stable as heat-resistant as bonding materials for die attach of GaN semiconductors and SiC semiconductors that are being developed as next-generation power semiconductors that are expected to be used at high temperatures of 200 ° C or higher. Unusable due to lack of sex.
  • a bonding material for a semiconductor device whose main component is zinc having a melting point of 420 ° C. is used, a next-generation power semiconductor excellent in heat fatigue that can withstand a temperature cycle up to 300 ° C. A device can be obtained.
  • the coating layer that prevents diffusion of the bonding material for the semiconductor device is provided on at least one of the substrate surface and the semiconductor member surface. Accordingly, the reaction between the substrate and the bonding material for semiconductor device and / or the reaction between the semiconductor member and the bonding material for semiconductor device is hindered, and the formation of a reaction layer having a low strength can be prevented. As a result, the bonding strength between the substrate and the bonding material for semiconductor device and / or the bonding strength between the semiconductor member and the bonding material for semiconductor device can be maintained, and a semiconductor device with excellent reliability can be obtained.
  • the coat layer is formed by laminating a barrier layer made of nitride, carbide or carbonitride and a protective layer made of noble metal.
  • a barrier layer made of nitride, carbide or carbonitride
  • a protective layer made of noble metal.
  • the nitride, carbide or carbonitride constituting the barrier layer has a lower free energy than the free energy of the substance constituting the insulating layer provided on the substrate. Is selected. Therefore, the activation of the barrier layer is suppressed, and the substance constituting the substrate or the semiconductor member does not move to the semiconductor device bonding material side. For this reason, the reaction between the substrate and the bonding material for a semiconductor device and the reaction between the semiconductor member and the bonding material for a semiconductor device can be prevented, and the formation of a reaction layer having a low strength can be prevented. As a result, a highly reliable semiconductor device can be obtained.
  • the material constituting the barrier layer is TiN
  • the material constituting the protective layer is Au, Ag, Cu, Ni, or Pd, and is included in the substrate.
  • the material constituting the insulating layer is Si 3 N 4 , Al 2 O 3 , or AlN.
  • TiN as a material constituting the barrier layer has a free energy smaller than that of Si 3 N 4 as a material constituting the insulating layer included in the substrate.
  • the bonding force between Ti and N is larger than the bonding force between Ti and Zn and the bonding force between N and Zn.
  • the reaction between the substrate and the bonding material for a semiconductor device can be prevented, and the formation of a reaction layer having a low strength can be prevented.
  • a highly reliable semiconductor device can be obtained as described above.
  • Au, Ag, Cu, Ni, or Pd as a material constituting the protective layer improves the wettability of the bonding material for a semiconductor device with respect to the coat layer, so that an Au layer, Ag on the bonding surface with the bonding material for the semiconductor device.
  • the layer, the Cu layer, the Ni layer, or the Pd layer is provided, generation of voids at the joint surface can be suppressed, and a good joint surface can be obtained.
  • the purity of the zinc is 90 wt% or more.
  • Zinc is a highly conductive metal with excellent flexibility. Therefore, by containing 90 wt% or more of zinc in the bonding material for a semiconductor device, it is possible to prevent the semiconductor device from being fragile and broken by an impact such as bending or bending.
  • the purity of zinc is 99.9999 wt% or more.
  • the barrier layer has a thickness in the range of 100 nm to 2000 nm, and the protective layer has a thickness in the range of 20 nm to 500 nm. Within this thickness range, the barrier layer can sufficiently prevent diffusion of the bonding material for semiconductor devices, and the protective layer can reliably prevent oxidation and contamination of the bonding material for semiconductor devices. it can.
  • the bonding material for a semiconductor device contains an impurity element.
  • the impurity element preferably includes at least one element selected from the group consisting of Ca, Mn, Ti, Cr, Ni, V, and Nb.
  • a characteristic configuration of the bonding material for a semiconductor device according to the present invention is a bonding material for a semiconductor device that bonds the semiconductor member and the substrate in a semiconductor device in which a semiconductor member is stacked on a substrate. It is mainly composed of zinc.
  • the bonding material for a semiconductor device according to the present invention is a bonding material for a semiconductor device whose main component is zinc having a melting point of 420 ° C., if this material is used, it has excellent thermal fatigue that can withstand a temperature cycle up to 300 ° C. Next-generation power semiconductor devices can be obtained.
  • FIG. 1 It is a schematic diagram of the test piece for a tensile test.
  • (A) And (b) is a graph which shows the result of a tension test.
  • (A) And (b) is a graph which shows the result of a tension test.
  • (A)-(e) is a figure which shows the image of the surface of the zinc to which pure zinc and the impurity element were added.
  • (A) And (b) is a figure which shows the image of the surface of zinc to which the impurity element was added, and pure zinc. It is a graph which shows the change of the weight increase amount with respect to the oxidation time of a sample.
  • (A) And (b) is a graph which shows the result of a tension test.
  • (A) And (b) is a graph which shows the result of a tension test.
  • FIG. 1 is a schematic diagram showing a semiconductor device 100 according to an embodiment of the present invention.
  • the semiconductor device 100 has a configuration in which a semiconductor member 120 is stacked on a substrate 110.
  • substrate 110 and the semiconductor member 120 are joined via the bonding
  • the semiconductor device bonding material 130 is used as a die attach material (semiconductor die bonding material) in a semiconductor manufacturing process. It is an adhesive that is provided in the form of a thin film layer, a paste, or a film, and joins a semiconductor member (for example, a die chip) and a substrate. Since the melting point of the material mainly composed of zinc is about 420 ° C., it can function as a die attach material (die bonding material for semiconductor) without melting even at a high temperature of about 300 ° C.
  • the substrate 110 includes an insulating layer 111 and Cu layers (first Cu layer 112 and second Cu layer 113) bonded to both surfaces of the insulating layer 111.
  • a first coat layer 140 that prevents diffusion of the semiconductor device bonding material 130 is provided on the surface of the substrate 110.
  • the first coat layer 140 is configured by laminating a first barrier layer 141 made of nitride, carbide or carbonitride and a first protective layer 142 made of a noble metal.
  • a second coat layer 150 is provided on the surface of the semiconductor member 120 to prevent the semiconductor device bonding material 130 from diffusing.
  • the second coat layer 150 is formed by laminating a second barrier layer 151 made of nitride, carbide or carbonitride and a second protective layer 152 made of a noble metal.
  • the material constituting the semiconductor member 120 is, for example, SiC, and the semiconductor device 100 functions as a SiC semiconductor device. Further, the material constituting the semiconductor member 120 may be GaN, and the semiconductor device 100 functions as a GaN semiconductor device. Further, the material constituting the insulating layer 111 is a Si 3 N 4 for example, so long as it functions as an insulator, but is not limited to Si 3 N 4. For example, the insulating layer 111 can be Al 2 O 3 or AlN. Alternatively, the insulating layer 111 may be other ceramics.
  • the thickness of the first protective layer 142 and the second protective layer 152 is preferably about 20 nm to 500 nm.
  • the first protective layer 142 and the second protective layer 152 are made of a noble metal, and for example, Au, Ag, Cu, Ni, or Pd can be adopted.
  • Au, Ag, Cu, Ni, or Pd ensures the wettability of the bonding material for semiconductor device 130 and prevents contamination of the bonding material for semiconductor device.
  • an Au layer, an Ag layer, a Cu layer, a Ni layer, or a Pd layer is provided on the bonding surface with the semiconductor device bonding material 130, generation of voids at the bonding surface can be suppressed, and a good bonding surface can be obtained. it can.
  • the thicknesses of the first barrier layer 141 and the second barrier layer 151 are preferably about 100 nm to 2000 nm. With this thickness, the barrier layer can sufficiently prevent diffusion of the semiconductor device bonding material 130.
  • the nitride, carbide, or carbonitride constituting the first barrier layer 141 and the second barrier layer 151 is selected to have a free energy smaller than the free energy of the material constituting the insulating layer 111. Therefore, activation of each barrier layer 141 and 151 is suppressed, and the substance which comprises the board
  • FIG. 2 is a graph showing changes in free energy of various nitrides.
  • the vertical axis shows the free energy change (kcal / mol) of the reaction (Me + N2 ⁇ Me-nitride), and the horizontal axis shows the temperature (° C.).
  • NbN, TiN, Ta 2 N, and ZrN have a smaller change in free energy of reaction than Si 3 N 4 .
  • the material constituting the insulating layer is Si 3 N 4
  • the material constituting the first barrier layer 141 and the second barrier layer 151 can be selected from TiN, for example.
  • TiN has a free energy that is smaller than the free energy of Si 3 N 4 .
  • NbN, TiN, Ta 2 N, and ZrN can be used as materials constituting the first barrier layer 141 and the second barrier layer 151.
  • the substance which comprises the 1st barrier layer 141 and the 2nd barrier layer 151 is a carbide
  • carbonized_material TiC, TaC, ZrC, NbC etc. can be used, for example.
  • the semiconductor The material constituting the first barrier layer 141 and the second barrier layer 151 may be changed to TiC or NbC by reacting SiC constituting the member 120 with Ti or Nb. This reaction may occur in a solid state, but when a metal barrier (for example, Ti) is dissolved in a liquid, a reaction with SiC is more likely to occur.
  • the material constituting the first barrier layer 141 and the second barrier layer 151 may be a carbonitride such as TiCN.
  • the first barrier layer 141 and the second barrier layer 151 may be made of different materials.
  • the first coat layer 140 is provided on the surface of the substrate 110 as long as the substrate 110 and the semiconductor member 120 are bonded via the semiconductor device bonding material 130 containing zinc as a main component. It is not limited to that.
  • the second coat layer 150 is not limited to be provided on the surface of the semiconductor member 120.
  • the first coat layer 140 may not be provided on the surface of the substrate 110, and the second coat layer 150 may not be provided on the surface of the semiconductor member 120.
  • each of the first protective layer 142 and the second protective layer 152 is a noble metal as long as the noble metal layer is provided on the bonding surface of the semiconductor device bonding material 130. It is not limited to a single layer. At least one of the first protective layer 142 and the second protective layer 152 may have at least one metal layer in addition to the single noble metal layer. Further, each of the first protective layer 142 and the second protective layer 152 may include a plurality of noble metal layers, such as a noble metal layer including an Ni layer and an Au layer. Further, the semiconductor device bonding material 130 may be added with a small amount of impurities if zinc is a main component. The purity of zinc as a main component in the bonding material 130 for a semiconductor device is 90 wt% or more, but is preferably high purity (99.99 wt% or more).
  • the bonding material for a semiconductor device whose main component is zinc having a melting point of 420 ° C. since it has excellent thermal fatigue that can withstand a temperature cycle up to 300 ° C. A next-generation power semiconductor device can be obtained.
  • a coat layer that prevents diffusion of the bonding material for the semiconductor device is provided on the substrate surface. Therefore, the reaction between the substrate and the bonding material for a semiconductor device is hindered, and formation of a reaction layer having a low strength can be prevented. As a result, the bonding strength between the substrate and the bonding material for a semiconductor device is maintained, and a semiconductor device having excellent reliability can be obtained.
  • the material constituting the barrier layer is TiN
  • the material constituting the protective layer is Au, Ag, Cu, Ni, or Pd
  • the material constituting the insulating layer included in the substrate is Si 3 N 4 , Al 2.
  • it constitutes a preferred semiconductor device of the present invention.
  • TiN as a material constituting the barrier layer has a free energy smaller than that of Si 3 N 4 as a material constituting the insulating layer included in the substrate.
  • the bonding force between Ti and N is larger than the bonding force between Ti and Zn and the bonding force between N and Zn.
  • the reaction between the substrate and the bonding material for a semiconductor device can be prevented, and the formation of a reaction layer having a low strength can be prevented.
  • a highly reliable semiconductor device can be obtained as described above.
  • Au, Ag, Cu, Ni, or Pd as a material constituting the protective layer improves the wettability of the bonding material for a semiconductor device with respect to the coat layer, so that an Au layer, Ag on the bonding surface with the bonding material for the semiconductor device.
  • the layer, the Cu layer, the Ni layer, or the Pd layer is provided, generation of voids at the joint surface can be suppressed, and a good joint surface can be obtained.
  • the impurity element is, for example, at least one selected from the group consisting of Ca (calcium), Mn (manganese), Ti (titanium), Cr (chromium), Ni (nickel), V (vanadium), and Nb (niobium). It is preferable that an element is included.
  • Ca is an alkaline earth metal
  • Mn, Ti, Cr, Ni, V, and Nb are transition metals. In particular, Ni, V and Nb are also called refractory metals.
  • thermal shock test sample 1 a thermal shock test sample 2, and a thermal shock test comparative sample were prepared.
  • the thermal shock test sample 1 pure zinc (purity 99.99 wt%, length 4 mm, width 4 mm, thickness 0.2 mm) was used as the bonding material 130 for the semiconductor device.
  • the insulating layer 111 an Si 3 N 4 layer (15 mm long, 15 mm wide, 0.5 mm thick) was used.
  • An Au layer (13 mm long, 13 mm wide, 200 nm thick) is provided as a first protective layer 142 on one side (second Cu layer 113 (13 mm long, 13 mm wide, 0.5 mm thick)) of the substrate 100, and a first barrier layer.
  • a TiN layer (length 13 mm, width 13 mm, thickness 800 nm) was used as 141.
  • the Au layer is laminated on the semiconductor device bonding material 130 side, and the TiN layer is laminated on the second Cu layer 113 side.
  • An Au layer (3 mm length, 3 mm width, 200 nm thickness) as the second protective layer 152 on one side (3 mm length, 3 mm width, 1 mm thickness) side of the semiconductor member 120, and a TiN layer (3 mm length) as the second barrier layer 151 , Width 3 mm, thickness 800 nm).
  • the Au layer is laminated on the semiconductor device bonding material 130 side, and the TiN layer is laminated on the semiconductor member 120 side.
  • the thermal shock test sample 2 includes layers other than the first coat layer 140 among the layers of the thermal shock test sample 1.
  • the thermal shock test comparative sample has the same configuration as the thermal shock test sample 1 except that Pb-5Sn (melting point is 315 ° C.) is used as the bonding material for the semiconductor device.
  • the surface of the first Cu layer was polished and the first coat layer was deposited to prepare a thermal shock test sample 1 and a thermal shock test comparative sample.
  • the semiconductor device bonding material was melted in an infrared furnace (Ar atmosphere, 450 ° C. ⁇ 60 s (melting point: 420 ° C. or higher, 100 s)). .
  • thermal shock test For each of the thermal shock test sample 1, the thermal shock test sample 2 and the thermal shock test comparative sample, a temperature cycle (0 to 500 times) between ⁇ 50 ° C. and 300 ° C. was performed in the air. Each time, 30 minutes was maintained.
  • FIG. 3 is a view showing a photograph of a cross section of the thermal shock test sample 1 after the thermal shock test.
  • the thermal shock test sample 1 after the thermal shock test includes a SiC layer (semiconductor member 120), a TiN layer (second barrier layer 151), a Zn layer (semiconductor device bonding material 130), and a Cu layer (second Cu layer 113). including.
  • a SiC layer semiconductor member 120
  • TiN layer second barrier layer 151
  • Zn layer semiconductor device bonding material 130
  • Cu layer second Cu layer 113
  • the thermal shock test sample 1 after the thermal shock test is observed for appearance and low magnification, large bonding defects (cracks, interface peeling, etc.) are not confirmed, and the semiconductor member 120, the bonding material 130 for the semiconductor device, and the substrate 110 are not observed.
  • the semiconductor device bonding material 130 was bonded well. Only the TiN layer (second barrier layer 151) was formed at the interface at the bonding surface between the semiconductor member 120 and the bonding material for semiconductor device 130 and at the interface at the bonding surface between the substrate 110 and the bonding material for semiconductor device.
  • FIG. 4 is a view showing a photograph of a cross section of the thermal shock test sample 2 after the thermal shock test.
  • the thermal shock test sample 2 after the thermal shock test includes an SiC layer (semiconductor member 120), a TiN layer (second barrier layer 151), a Zn layer (semiconductor device bonding material 130), a CuZn 5 layer, and a Cu 5 Zn 8. And a Cu layer (second Cu layer 113). At the interface between the Zn layer (semiconductor device bonding material 130) and the Cu layer (second Cu layer 113), the Zn layer (semiconductor device bonding material 130) and the Cu layer (second Cu layer 113) react to form CuZn 5. Layer, Cu 5 Zn 8 layer was formed.
  • FIG. 5 is a view showing a photograph of a cross section of the thermal shock test comparative sample after the thermal shock test.
  • the comparative sample for the thermal shock test after the thermal shock test includes a SiC layer, a TiN layer, a Pb-5Sn layer (a bonding material for a semiconductor device), and a Cu layer. Cracks are generated inside the Pb-5Sn layer (semiconductor device bonding material).
  • FIG. 6 is a diagram for explaining the configuration of a shear test sample and the shear test results.
  • FIG. 6A is a schematic diagram showing a configuration of a sample for shear test.
  • a shear test sample 1 For the shear test, a shear test sample 1, a shear test sample 2 and a shear test comparative sample were prepared.
  • Each of the shear test sample 1 and the shear test comparative sample has a first Cu layer 213 (length 7 mm, width 11 mm, thickness 0.8 mm), first coating layer 240 (Au layer 242 thickness 200 nm, from the bottom) TiN layer 241 thickness 800 nm), semiconductor device bonding material layer 230 (length 4 mm, width 4 mm, thickness 0.2 mm), second coat layer 250 (Au layer 252 thickness 200 nm, TiN layer 251 thickness) 800 nm) and a second Cu layer 220 (length 4 mm, width 4 mm, thickness 0.8 mm).
  • the shear test sample 2 includes layers other than the first coat layer 240 among the layers of the shear test sample 1.
  • the semiconductor device bonding material of the shear test sample 1 and the shear test sample 2 is pure zinc (purity 99.99 wt%), and the semiconductor device bonding material of the shear test comparative sample is Pb-5Sn.
  • a temperature cycle (0 to 500 times) between ⁇ 50 ° C. and 300 ° C. is performed in the atmosphere for each of the shear test sample 1, the shear test sample 2, and the shear test comparative sample. Each time, 30 minutes was maintained. At each of the 0th, 250th and 500th temperature cycles, an impact was applied by the head.
  • the test height (head position) is 0.1 mm from the upper surface of the first coat layer 240, and the test speed (head speed) is 50 ⁇ m / s.
  • a portion to which a shearing force is applied is indicated by an arrow in FIG. 6A (a portion of the bonding material layer 230 for a semiconductor device).
  • FIG. 6B is a graph showing the shear test results for the shear test sample 1, the shear test sample 2, and the shear test comparative sample.
  • the vertical axis represents shear strength (MPa), and the horizontal axis represents the number of temperature cycles (times).
  • the shear test sample 1 showed a shear strength of about 36 to 39 MPa, which was about 3.5 times the shear strength of the shear test comparative sample.
  • the bonding material for a semiconductor device mainly composed of zinc having a melting point of 420 ° C. since it can withstand a temperature cycle up to 300 ° C. It is possible to obtain a next-generation power semiconductor device having excellent heat fatigue.
  • Samples 1 to 5 were prepared in order to investigate changes in characteristics due to the addition of impurity elements.
  • Sample 1 commercially available zinc to which no impurity element was added was prepared. The purity of this zinc was 99.99 wt%. Such zinc is represented as 4N.
  • zinc to which no impurity element is added in the sample 1 may be referred to as pure zinc.
  • Samples 2 to 5 four additives prepared by adding the impurity elements Ca, Mn, Ti, and Cr to 0.1 mass percent (0.1 wt%) to the above-described zinc were prepared. Samples 2 to 5 are respectively added with Ca, Mn, Ti and Cr.
  • samples 1 to 5 were processed into test pieces for tensile testing.
  • FIG. 7 the schematic diagram of a test piece is shown. Specifically, samples 1 to 5 were respectively casted and rolled until the thickness of each sample was changed from 10 to 13 mm to 1.3 mm, and then electric discharge machining was performed. In this way, test pieces 1 to 5 were formed from samples 1 to 5, respectively.
  • each of the test pieces 1 to 5 had a thickness of 1.2 mm, and a heat treatment was performed at 180 ° C. for 3 hours to remove the residual stress. Thereafter, each of the test pieces 1 to 5 was polished with an alumina abrasive. In the polishing, the particle size of the alumina abrasive was gradually reduced, and finally an abrasive having a particle size of 0.3 ⁇ m was used.
  • Ten test pieces 1 to 5 were prepared as described above, and a tensile test was performed. The elongation rate was 7 ⁇ 10 ⁇ 4 mm / sec. In the tensile test, the result of the test piece fractured at a portion other than the gauge distance was ignored, and the average of six pieces excluding the maximum value and the minimum value among the measurement results of the remaining test pieces was calculated. .
  • FIG. 8 shows the results of the tensile test.
  • FIG. 8A shows the nominal stress with respect to the nominal strain
  • FIG. 8B shows the maximum tensile strength (UTS) of the test pieces 1 to 5.
  • UTS maximum tensile strength
  • FIG. 8A and 8B the results of the test pieces 1 to 5 are shown as Zn, 0.1Ca, 0.1Mn, 0.1Cr, and 0.1Ti, respectively.
  • the addition of Ca, Mn, Cr and Ti increased the elastic range and increased the Young's modulus. In particular, the Young's modulus increased significantly with the addition of Ti.
  • FIG. 9 (a) shows the results of the elongation of each of the test pieces 1 to 5.
  • the elongation of the test piece 1 was relatively low at 5.0%, whereas the elongation of the test pieces 2 to 4 to which the impurity element was added was 20% or more. Thus, it has been found that the elongation increases with the addition of the impurity element.
  • FIG. 9 (b) shows the result of 0.2% proof strength.
  • the proof stress of Samples 2, 3, and 5 to which Ca, Mn, and Ti were added was higher than that of Sample 1, but the proof stress of Sample 4 to which Cr was added was almost the same as that of Sample 1.
  • FIG. 10 shows an enlarged image of each sample 1-5.
  • FIGS. 10A to 10E are images of samples 1 to 5, respectively.
  • the crystal grains of zinc in Sample 1 were relatively large, the grain diameter of the zinc crystals was reduced by the addition of the impurity element.
  • the crystal grain size of zinc was considerably reduced.
  • FIGS. 11 (a) and 11 (b) show enlarged images of fracture surfaces in the initial structures of Sample 5 and Sample 1 to which Ti is added, respectively.
  • Sample 5 is considered to be an intermetallic compound.
  • EDS Energy dispersive X-ray analysis
  • FIG. 12 shows the result of weight gain with respect to the oxidation time of samples 1 to 5. While the increase in the weight of Sample 1 with respect to the oxidation time was relatively large, the increase in the weight of Samples 2 to 5 with respect to the oxidation time was relatively small due to the addition of the impurity element. In particular, the increase in weight was considerably reduced by the addition of Cr. As described above, the addition of the impurity element (particularly, addition of Cr) could suppress the oxidation of the sample mainly composed of zinc.
  • test piece 6 was polished with an alumina abrasive.
  • the particle size of the alumina abrasive was gradually reduced, and finally an abrasive having a particle size of 0.3 ⁇ m was used.
  • Three test pieces 6 were prepared as described above, and a tensile test was performed. The elongation rate was 7 ⁇ 10 ⁇ 4 mm / sec.
  • FIG. 13 shows the results of the tensile test.
  • FIG. 13A shows the nominal stress with respect to the nominal strain
  • FIG. 13B shows the maximum tensile strength (UTS) of the test pieces 1 and 6.
  • UTS maximum tensile strength
  • Fig.13 (a) and FIG.13 (b) the result of the test pieces 1 and 6 is each shown as 4NZn and 6NZn.
  • Fig. 14 (a) shows the results of the elongation of each of the test pieces 1 and 6 (Elongation).
  • the elongation percentage of the test piece 1 was relatively low at 5.0%, whereas the elongation percentage of the test piece 6 was 8% or more.
  • the elongation rate improved with the increase in purity of zinc.
  • FIG. 14B shows the result of 0.2% proof strength.
  • the yield strength decreased with increasing purity of zinc.
  • the semiconductor device and the bonding material for a semiconductor device according to the present invention can be used for a compound semiconductor device such as a GaN semiconductor device or a SiC semiconductor device that has been developed as a next-generation power semiconductor.

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Abstract

　本発明による基板１１０に半導体部材１２０を積層した半導体装置１００は、半導体部材１２０と基板１１０とは亜鉛を主成分とする半導体装置用接合材１３０を介して接合されている。また、基板１１０の表面および半導体部材１２０の表面の少なくとも一方に半導体装置用接合材１３０の拡散を防ぐコート層が設けられている。また、コート層１４０は、窒化物、炭化物または炭窒化物からなるバリア層１４１と、貴金属からなる保護層１４２とを積層して構成される。更に、バリア層１４１を構成する窒化物、炭化物または炭窒化物は、基板１１０に設けられた絶縁層１１１を構成する物質が有する自由エネルギーよりも小さい自由エネルギーを有するように選択される。

Description

半導体装置及び半導体装置用接合材
　本発明は、基板に半導体部材を積層した半導体装置、及び半導体部材と基板とを接合する半導体装置用接合材に関する。
　一般に、半導体実装工程において、ダイ（半導体素子）と基板とが接合材によって接合される。例えば、特許文献１では、半導体素子がダイパッドにダイアタッチされている半導体装置が開示される。
特開平６－１６３７３７号公報
　しかし、特許文献１の半導体装置には、接合材の主成分として、融点が低い鉛が用いられている。例えば、ハイブリッド自動車に使用されているパワーモジュールは、大電流によりデバイス自体に発熱が起こるとともに、エンジンに近接しているため、厳しい温度環境におかれる。従って、２００℃以上の高温での使用を想定している次世代パワー半導体（ＳｉＣ半導体チップ）のダイアタッチ用接合剤としては耐熱安定性にかけ、接合材としては使えない。
　本発明は、次世代パワー半導体として開発されているＧａＮ半導体やＳｉＣ半導体などの化合物半導体装置、及び半導体装置のダイアタッチ用接合材として耐熱安定性に優れた半導体装置用接合材を提供することを目的とする。
　上記課題を解決するために、本発明に係る半導体装置の特徴的構成は、基板に半導体部材を積層した半導体装置であって、前記半導体部材と前記基板とは亜鉛を主成分とする半導体装置用接合材を介して接合されている。
　背景技術の項目で説明したように、従来の半導体装置では、半導体部材と基板との接合のためには鉛を主成分とする半導体装置用接合材が用いられてきた。しかし、これら半導体装置用接合材では融点が低く、２００℃以上の高温での使用を想定している次世代パワー半導体として開発されているＧａＮ半導体やＳｉＣ半導体のダイアタッチ用接合材としては耐熱安定性に欠けるため使用に耐えられない。一方、本発明の半導体装置であれば、融点が４２０℃である亜鉛を主成分とする半導体装置用接合材を用いるため、３００℃までの温度サイクルに耐え得る耐熱疲労に優れた次世代パワー半導体装置を得ることができる。
　本発明の半導体装置の好適な態様によれば、半導体装置用接合材の拡散を防ぐコート層が基板表面および半導体部材表面の少なくとも一方に設けられている。従って、基板と半導体装置用接合材との反応および／または半導体部材と半導体装置用接合材との反応が妨げられ、強度が弱い反応層の形成を防ぐことができる。その結果、基板と半導体装置用接合材との接合強度および／または半導体部材と半導体装置用接合材との接合強度が保たれ、信頼性に優れた半導体装置を得ることができる。
　本発明の半導体装置の好適な態様によれば、前記コート層は、窒化物、炭化物または炭窒化物からなるバリア層と、貴金属からなる保護層とを積層して構成される。バリア層を設けることにより半導体装置用接合材が基板に拡散することを防ぐことができる。また、貴金属（特にＡｕ）は、コート層に対する半導体装置用接合材の濡れ性を向上させる。その結果、半導体装置用接合材と基板との良好な接合が可能になる。
　本発明の半導体装置の好適な態様によれば、前記バリア層を構成する窒化物、炭化物または炭窒化物は、前記基板に設けられた絶縁層を構成する物質が有する自由エネルギーよりも小さい自由エネルギーを有するように選択される。従って、バリア層の活性化が抑制され、基板又は半導体部材を構成する物質が半導体装置用接合材側に移動しない。このため、基板と半導体装置用接合材との反応及び半導体部材と半導体装置用接合材との反応を防ぎ得、強度が弱い反応層の形成を防ぐことができる。結果として、信頼性の高い半導体装置を得ることができる。
　本発明の半導体装置の好適な態様によれば、前記バリア層を構成する物質はＴｉＮであり、前記保護層を構成する物質はＡｕ、Ａｇ、Ｃｕ、Ｎｉ又はＰｄであり、前記基板に含まれる絶縁層を構成する物質はＳｉ３Ｎ４、Ａｌ２Ｏ３、又はＡｌＮである。例えば、バリア層を構成する物質としてのＴｉＮは、基板に含まれる絶縁層を構成する物質としてのＳｉ３Ｎ４が有する自由エネルギーよりも小さい自由エネルギーを有する。またＴｉとＮとの結合力が、ＴｉとＺｎとの結合力及びＮとＺｎとの結合力よりも大きい。従って、基板と半導体装置用接合材との反応を防ぎ得、強度が弱い反応層の形成を防ぐことができる。その結果、上記と同様に、信頼性の高い半導体装置を得ることができる。また保護層を構成する物質としてのＡｕ、Ａｇ、Ｃｕ、Ｎｉ又はＰｄは、コート層に対する半導体装置用接合材の濡れ性を向上させるため、半導体装置用接合材との接合面にＡｕ層、Ａｇ層、Ｃｕ層、Ｎｉ層又はＰｄ層を設けると、接合面でのボイドの生成を抑えることができ、良好な接合面を得ることができる。
　本発明の半導体装置の好適な態様によれば、前記亜鉛の純度は、９０ｗｔ％以上である。亜鉛は柔軟性に優れた導電性の良好な金属である。従って、半導体装置用接合材に亜鉛を９０ｗｔ％以上含有させることで、半導体装置の曲げや折れなどの衝撃によって脆く破壊されることを避けることができる。なお、亜鉛の純度は、９９．９９９９ｗｔ％以上であることが好ましい。高純度の亜鉛を用いることにより、半導体装置用接合材の伸び率を向上させることができる。
　本発明の半導体装置の好適な態様によれば、前記バリア層の厚さは１００ｎｍから２０００ｎｍの範囲内であり、前記保護層の厚さは２０ｎｍから５００ｎｍの範囲内である。この程度の厚さ範囲であれば、バリア層によって半導体装置用接合材の拡散を防ぐことが十分に可能となり、且つ、保護層によって半導体装置用接合材の酸化及び汚染を確実に防止することができる。
　本発明の半導体装置の好適な態様によれば、前記半導体装置用接合材は、不純物元素を含む。不純物元素を含むことにより、半導体装置用接合材の特性を改善することができる。なお、不純物元素は、Ｃａ、Ｍｎ、Ｔｉ、Ｃｒ、Ｎｉ、ＶおよびＮｂからなる群から選択された少なくとも１つの元素を含むことが好ましい。このような不純物元素の添加により、半導体装置用接合材の延性を向上させるとともに酸化を抑制することができる。
　上記課題を解決するために、本発明に係る半導体装置用接合材の特徴的構成は、基板に半導体部材を積層した半導体装置において、前記半導体部材と前記基板とを接合する半導体装置用接合材であって、亜鉛を主成分とする。
　本発明に係る半導体装置用接合材によれば、上記説明した本発明の半導体装置と同様の作用効果を得ることができる。本発明に係る半導体装置用接合材は融点が４２０℃である亜鉛を主成分とする半導体装置用接合材であるため、これを使用すれば、３００℃までの温度サイクルに耐え得る耐熱疲労に優れた次世代パワー半導体装置を得ることができる。
本発明の実施形態に係る半導体装置を示す模式図である。 各種窒化物の自由エネルギー変化を示すグラフである。 熱衝撃試験後の熱衝撃試験用試料１の断面の写真を示す図である。 熱衝撃試験後の熱衝撃試験用試料２の断面の写真を示す図である。 熱衝撃試験後の熱衝撃試験用比較試料の断面の写真を示す図である。 せん断試験用試料の構成及びせん断試験結果を説明する図であり、（ａ）はせん断試験用試料の構成を示す模式図であり、（ｂ）はせん断試験結果を示すグラフである。 引張試験用の試験片の模式図である。 （ａ）および（ｂ）は引張試験の結果を示すグラフである。 （ａ）および（ｂ）は引張試験の結果を示すグラフである。 （ａ）～（ｅ）は純亜鉛および不純物元素の添加された亜鉛の表面の像を示す図である。 （ａ）および（ｂ）は不純物元素の添加された亜鉛および純亜鉛の表面の像を示す図である。 試料の酸化時間に対する重量増加量の変化を示すグラフである。 （ａ）および（ｂ）は引張試験の結果を示すグラフである。 （ａ）および（ｂ）は引張試験の結果を示すグラフである。
　図１、図２を参照して、本発明の半導体装置及び半導体装置用接合材に関する実施形態を説明し、図３～図１４を参照して、本発明の実施例を説明する。なお、本発明は、以下の実施形態に限定されない。
　図１は、本発明の実施形態に係る半導体装置１００を示す模式図である。半導体装置１００は、基板１１０に半導体部材１２０を積層した構成を有する。基板１１０と半導体部材１２０とは、亜鉛を主成分とする半導体装置用接合材１３０を介して接合されている。半導体装置用接合材１３０は、ダイアタッチ材（半導体用ダイボンド材）として半導体製造過程で用いられる。薄膜層状、ペースト状、フィルム状等の形状で提供され、半導体部材（例えばダイチップ）と基板とを接合する接着剤である。亜鉛を主成分とする材料の融点は、約４２０℃であるため、３００℃程度の高温であっても融解することなく、ダイアタッチ材（半導体用ダイボンド材）としての機能を発揮しえる。
　基板１１０は、絶縁層１１１と、絶縁層１１１の両面に接合されたＣｕ層（第１Ｃｕ層１１２と第２Ｃｕ層１１３）とを含む。基板１１０の表面に半導体装置用接合材１３０の拡散を防ぐ第１コート層１４０が設けられている。第１コート層１４０は、窒化物、炭化物または炭窒化物からなる第１バリア層１４１と、貴金属からなる第１保護層１４２とを積層して構成される。
　半導体部材１２０の表面に半導体装置用接合材１３０の拡散を防ぐ第２コート層１５０が設けられている。第２コート層１５０は、窒化物、炭化物または炭窒化物からなる第２バリア層１５１と、貴金属からなる第２保護層１５２とを積層して構成される。
　半導体部材１２０を構成する物質は例えばＳｉＣであり、半導体装置１００はＳｉＣ半導体装置として機能する。また、半導体部材１２０を構成する物質はＧａＮであり得、半導体装置１００はＧａＮ半導体装置として機能する。また、絶縁層１１１を構成する物質は例えばＳｉ３Ｎ４であるが、絶縁体として機能する限りは、Ｓｉ３Ｎ４に限定されない。例えば、絶縁層１１１はＡｌ２Ｏ３、又はＡｌＮであり得る。あるいは、絶縁層１１１は他のセラミックスであってもよい。
　第１保護層１４２及び第２保護層１５２の厚さは２０ｎｍから５００ｎｍの程度であることが好ましい。第１保護層１４２及び第２保護層１５２は貴金属で構成され、例えばＡｕ、Ａｇ、Ｃｕ、Ｎｉ又はＰｄを採用することができる。Ａｕ、Ａｇ、Ｃｕ、Ｎｉ又はＰｄは半導体装置用接合材１３０の濡れ性を確保し、半導体装置用接合材の汚染を防止する。半導体装置用接合材１３０との接合面にＡｕ層、Ａｇ層、Ｃｕ層、Ｎｉ層又はＰｄ層を設けると、接合面でのボイドの生成を抑えることができ、良好な接合面を得ることができる。
　第１バリア層１４１及び第２バリア層１５１の厚さは１００ｎｍから２０００ｎｍの程度であることが好ましい。この程度の厚さであれば、バリア層によって半導体装置用接合材１３０の拡散を防ぐことが十分に可能となる。第１バリア層１４１及び第２バリア層１５１を構成する窒化物、炭化物または炭窒化物は、絶縁層１１１を構成する物質が有する自由エネルギーよりも小さい自由エネルギーを有するように選択される。従って、各バリア層１４１、１５１の活性化が抑制され、基板１１０又は半導体部材１２０を構成する物質が半導体装置用接合材１３０側に移動しない。このため、基板と半導体装置用接合材との反応及び半導体部材と半導体装置用接合材との反応を防ぎ得、強度が弱い反応層の形成を防ぐことができる。結果として、信頼性の高い半導体装置を得ることができる。
　図２は、各種窒化物の自由エネルギー変化を示すグラフである。縦軸は反応（Ｍｅ＋Ｎ２→Ｍｅ－ｎｉｔｒｉｄｅ）の自由エネルギー変化（ｋｃａｌ／ｍｏｌ）を示し、横軸は温度（℃）を示す。図２を参照すれば、ＮｂＮ、ＴｉＮ、Ｔａ２Ｎ及びＺｒＮは、Ｓｉ３Ｎ４よりも反応の自由エネルギー変化が小さい。例えば、絶縁層を構成する物質がＳｉ３Ｎ４であれば、第１バリア層１４１及び第２バリア層１５１を構成する物質は例えばＴｉＮを選択可能である。ＴｉＮは、Ｓｉ３Ｎ４が有する自由エネルギーよりも小さい自由エネルギーを有する。この他、第１バリア層１４１及び第２バリア層１５１を構成する物質としては、ＮｂＮ、ＴｉＮ、Ｔａ２Ｎ及びＺｒＮを用い得る。なお、第１バリア層１４１及び第２バリア層１５１を構成する物質が炭化物の場合は、例えば、ＴｉＣ、ＴａＣ、ＺｒＣ、ＮｂＣなどを用い得る。また、ＴｉＣまたはＮｂＣから構成された第１バリア層１４１及び第２バリア層１５１を形成する場合、予めＴｉまたはＮｂから構成された第１バリア層１４１及び第２バリア層１５１を形成した後、半導体部材１２０を構成するＳｉＣとＴｉまたはＮｂとが反応することによって、第１バリア層１４１及び第２バリア層１５１を構成する物質をＴｉＣまたはＮｂＣに変化させてもよい。この反応は固相状態で生じてもよいが、メタルバリア（例えば、Ｔｉ）が液体中に溶けると、ＳｉＣとの反応がさらに生じやすくなる。あるいは、第１バリア層１４１及び第２バリア層１５１を構成する物質はＴｉＣＮなどの炭窒化物であってもよい。なお、第１バリア層１４１及び第２バリア層１５１は互いに異なる物質から構成されてもよい。
　以上、図１及び図２を参照して、本発明の半導体装置１００及び半導体装置用接合材１３０に関する実施形態を説明した。なお、半導体装置１００において、基板１１０と半導体部材１２０とが亜鉛を主成分とする半導体装置用接合材１３０を介して接合されている限りは、基板１１０の表面に第１コート層１４０が設けられることに限定されない。また同様に、半導体部材１２０の表面に第２コート層１５０が設けられることに限定されない。基板１１０の表面に第１コート層１４０が設けられないことがあり得、半導体部材１２０の表面に第２コート層１５０が設けられないことがあり得る。
　更に、第１コート層１４０と第２コート層１５０において、半導体装置用接合材１３０との接合面に貴金属層が設けられる限りは、第１保護層１４２と第２保護層１５２の各々は、貴金属層の単層に限定されない。第１保護層１４２と第２保護層１５２の少なくとも一方が、貴金属層の単層に加えて少なくとも一層の金属層を有し得る。更に、第１保護層１４２と第２保護層１５２の各々は、例えばＮｉ層とＡｕ層とを含んだ貴金属層のように、複数の貴金属層を含み得る。更に、半導体装置用接合材１３０は、亜鉛が主成分であれば、微量の不純物を添加し得る。半導体装置用接合材１３０における主成分としての亜鉛の純度は、９０ｗｔ％以上であるが、高純度（９９．９９ｗｔ％以上）であることが好ましい。
　本発明の半導体装置及び半導体装置用接合材によれば、融点が４２０℃である亜鉛を主成分とする半導体装置用接合材を用いるため、３００℃までの温度サイクルに耐え得る耐熱疲労に優れた次世代パワー半導体装置を得ることができる。また、半導体装置用接合材の拡散を防ぐコート層が基板表面に設けられている。従って、基板と半導体装置用接合材との反応が妨げられ、強度が弱い反応層の形成を防ぐことができる。その結果、基板と半導体装置用接合材との接合強度が保たれ、信頼性に優れた半導体装置を得ることができる。
　特に、バリア層を構成する物質がＴｉＮであり、保護層を構成する物質がＡｕ、Ａｇ、Ｃｕ、Ｎｉ又はＰｄであり、基板に含まれる絶縁層を構成する物質がＳｉ３Ｎ４、Ａｌ２Ｏ３、又はＡｌＮである場合は、本発明の好適な半導体装置を構成する。例えば、バリア層を構成する物質としてのＴｉＮは、基板に含まれる絶縁層を構成する物質としてのＳｉ３Ｎ４が有する自由エネルギーよりも小さい自由エネルギーを有する。またＴｉとＮとの結合力が、ＴｉとＺｎとの結合力及びＮとＺｎとの結合力よりも大きい。従って、基板と半導体装置用接合材との反応を防ぎ得、強度が弱い反応層の形成を防ぐことができる。その結果、上記と同様に、信頼性の高い半導体装置を得ることができる。また保護層を構成する物質としてのＡｕ、Ａｇ、Ｃｕ、Ｎｉ又はＰｄは、コート層に対する半導体装置用接合材の濡れ性を向上させるため、半導体装置用接合材との接合面にＡｕ層、Ａｇ層、Ｃｕ層、Ｎｉ層又はＰｄ層を設けると、接合面でのボイドの生成を抑えることができ、良好な接合面を得ることができる。
　上述したように、半導体装置用接合材１３０において、主成分の亜鉛に微量の不純物元素が添加されてもよい。不純物元素は、例えば、Ｃａ（カルシウム）、Ｍｎ（マンガン）、Ｔｉ（チタン）、Ｃｒ（クロム）、Ｎｉ（ニッケル）、Ｖ（バナジウム）およびＮｂ（ニオブ）からなる群から選択された少なくとも１つの元素を含むことが好ましい。なお、Ｃａはアルカリ土類金属であり、Ｍｎ、Ｔｉ、Ｃｒ、Ｎｉ、ＶおよびＮｂは遷移金属である。特に、Ｎｉ、ＶおよびＮｂは高融点金属とも呼ばれる。このような不純物元素の添加により、半導体装置用接合材１３０の延性を向上させるとともに半導体装置用接合材１３０の酸化を低減させることができる。不純物元素として亜鉛よりも酸化しやすい元素を用いることにより、半導体装置用接合材１３０の表面に亜鉛の保護膜となる酸化膜が形成されると考えられる。また、半導体装置用接合材１３０において純度の高い亜鉛を用いることによって延性を向上させることができる。
　なお、露出された銅が２００℃以上の温度の環境下にさらされると、酸化が著しく進行し、銅とＳｉＣおよび銅とセラミックスのそれぞれの界面に酸化物が生成し、強度が低下してしまうことがある。これに対して、第１バリア層１４１を構成する物質としてＴｉＮを用いて絶縁層１１１の表面のＣｕ層１１３を覆うと、３００℃の高温下にさらされても銅の酸化はほとんど進行しない。このように、第１バリア層１４１を構成する物質としてＴｉＮを用いることにより、ＳｉＣ／ＴｉＮ／銅／セラミックス界面における強度の低下を抑制することができる。
　以下、本発明の実施例を図３から図１４を参照して説明する。
［熱衝撃試験用試料］
　熱衝撃試験のために、熱衝撃試験用試料１、熱衝撃試験用試料２及び熱衝撃試験用比較試料を用意した。
　熱衝撃試験用試料１において、半導体装置用接合材１３０として純亜鉛（純度９９．９９ｗｔ％、縦４ｍｍ、横４ｍｍ、厚さ０．２ｍｍ）を用いた。絶縁層１１１として、Ｓｉ３Ｎ４層（縦１５ｍｍ、横１５ｍｍ、厚さ０．５ｍｍ）を用いた。基板１００の片面（第２Ｃｕ層１１３（縦１３ｍｍ、横１３ｍｍ、厚さ０．５ｍｍ））側に第１保護層１４２としてＡｕ層（縦１３ｍｍ、横１３ｍｍ、厚さ２００ｎｍ）を、第１バリア層１４１としてＴｉＮ層（縦１３ｍｍ、横１３ｍｍ、厚さ８００ｎｍ）を用いた。Ａｕ層は半導体装置用接合材１３０側に積層され、ＴｉＮ層は第２Ｃｕ層１１３側に積層されている。半導体部材１２０の片面（縦３ｍｍ、横３ｍｍ、厚さ１ｍｍ）側に第２保護層１５２としてＡｕ層（縦３ｍｍ、横３ｍｍ、厚さ２００ｎｍ）を、第２バリア層１５１としてＴｉＮ層（縦３ｍｍ、横３ｍｍ、厚さ８００ｎｍ）を用いた。Ａｕ層は半導体装置用接合材１３０側に積層され、ＴｉＮ層は半導体部材１２０側に積層されている。
　熱衝撃試験用試料２は、熱衝撃試験用試料１の各層のうち、第１コート層１４０以外の層を含む。熱衝撃試験用比較試料は、半導体装置用接合材としてＰｂ－５Ｓｎ（融点は３１５℃）を用いる点以外は、熱衝撃試験用試料１と同様の構成である。
　第１Ｃｕ層の表面を研磨し、第１コート層を蒸着することにより、熱衝撃試験用試料１及び熱衝撃試験用比較試料を作製した。熱衝撃試験用試料１、熱衝撃試験用試料２及び熱衝撃試験用比較試料において、赤外線炉（Ａｒ雰囲気、４５０℃×６０ｓ（融点４２０℃以上、１００ｓ））で半導体装置用接合材を溶融した。
［熱衝撃試験］
　熱衝撃試験用試料１、熱衝撃試験用試料２及び熱衝撃試験用比較試料の各々に対し、大気中、－５０℃と３００℃との間の温度サイクル（０～５００回）を実施した。各回において、３０ｍｉｎ保持した。
　図３は、熱衝撃試験後の熱衝撃試験用試料１の断面の写真を示す図である。熱衝撃試験後の熱衝撃試験用試料１は、ＳｉＣ層（半導体部材１２０）、ＴｉＮ層（第２バリア層１５１）、Ｚｎ層（半導体装置用接合材１３０）及びＣｕ層（第２Ｃｕ層１１３）を含む。半導体部材１２０と半導体装置用接合材１３０との接合面及び基板１１０と半導体装置用接合材１３０との接合面の各々は完全に濡れ、ボイドを見つけることができなかった。Ｚｎ層（半導体装置用接合材１３０）内部では、ＡｕＺｎ化合物が確認されたが、微量であり定量が困難であった（（１８－２２ａｔ％）Ａｕ－（７８－８２ａｔ％）Ｚｎ）。熱衝撃試験後の熱衝撃試験用試料１を外観観察及び低倍率観察しても、大きな接合欠陥（亀裂、界面剥離等）は確認されず、半導体部材１２０と半導体装置用接合材１３０及び基板１１０と半導体装置用接合材１３０は良好に接合していた。半導体部材１２０と半導体装置用接合材１３０との接合面における界面及び基板１１０と半導体装置用接合材１３０との接合面における界面では、ＴｉＮ層（第２バリア層１５１）のみ形成されていた。
　図４は、熱衝撃試験後の熱衝撃試験用試料２の断面の写真を示す図である。熱衝撃試験後の熱衝撃試験用試料２は、ＳｉＣ層（半導体部材１２０）、ＴｉＮ層（第２バリア層１５１）、Ｚｎ層（半導体装置用接合材１３０）、ＣｕＺｎ５層、Ｃｕ５Ｚｎ８層及びＣｕ層（第２Ｃｕ層１１３）を含む。Ｚｎ層（半導体装置用接合材１３０）とＣｕ層（第２Ｃｕ層１１３）との界面では、Ｚｎ層（半導体装置用接合材１３０）とＣｕ層（第２Ｃｕ層１１３）とが反応し、ＣｕＺｎ５層、Ｃｕ５Ｚｎ８層が形成された。Ｃｕ５Ｚｎ８層部分から亀裂が発生しているが、Ｚｎ層（半導体装置用接合材１３０）内部には伝播していない。熱衝撃試験後の熱衝撃試験用試料２を外観観察及び低倍率観察しても、大きな接合欠陥（亀裂等）は確認されず、半導体部材１２０と半導体装置用接合材１３０及び基板１１０と半導体装置用接合材１３０は良好に接合していた。半導体部材１２０とＺｎ層（半導体装置用接合材１３０）との接合面における界面では、ＴｉＮ層（第２バリア層１５１）のみ形成されていた。
　図５は、熱衝撃試験後の熱衝撃試験用比較試料の断面の写真を示す図である。熱衝撃試験後の熱衝撃試験用比較試料は、ＳｉＣ層、ＴｉＮ層、Ｐｂ－５Ｓｎ層（半導体装置用接合材）及びＣｕ層を含む。Ｐｂ－５Ｓｎ層（半導体装置用接合材）内部に亀裂が発生している。
［せん断試験用試料］
　図６は、せん断試験用試料の構成及びせん断試験結果を説明する図である。図６（ａ）は、せん断試験用試料の構成を示す模式図である。せん断試験のために、せん断試験用試料１、せん断試験用試料２及びせん断試験用比較試料を用意した。せん断試験用試料１、及びせん断試験用比較試料の各々は、下から第１Ｃｕ層２１３（縦７ｍｍ、横１１ｍｍ、厚さ０．８ｍｍ）、第１コート層２４０（Ａｕ層２４２の厚さ２００ｎｍ、ＴｉＮ層２４１の厚さ８００ｎｍ）、半導体装置用接合材層２３０（縦４ｍｍ、横４ｍｍ、厚さ０．２ｍｍ）、第２コート層２５０（Ａｕ層２５２の厚さ２００ｎｍ、ＴｉＮ層２５１の厚さ８００ｎｍ）、第２Ｃｕ層２２０（縦４ｍｍ、横４ｍｍ、厚さ０．８ｍｍ）を含む。せん断試験用試料２は、せん断試験用試料１の各層のうち、第１コート層２４０以外の層を含む。せん断試験用試料１及びせん断試験用試料２の半導体装置用接合材は、純亜鉛（純度９９．９９ｗｔ％）であり、せん断試験用比較試料の半導体装置用接合材は、Ｐｂ－５Ｓｎである。
　せん断試験用試料１、せん断試験用試料２及びせん断試験用比較試料の各々に対して、大気中、－５０℃と３００℃との間の温度サイクル（０～５００回）を実施している。各回において、３０ｍｉｎ保持した。温度サイクルが０回目、２５０回目及び５００回目の各々において、ヘッドによる衝撃を与えた。試験高さ（ヘッドの位置）は、第１コート層２４０の上面から０．１ｍｍの部分、試験速度（ヘッドスピード）は５０μｍ／ｓである。せん断力を付与する部分を図６（ａ）において矢印で示す（半導体装置用接合材層２３０の部分）。
［せん断試験結果］
　図６（ｂ）は、せん断試験用試料１、せん断試験用試料２及びせん断試験用比較試料に対するせん断試験結果を示すグラフである。縦軸はせん断強度（ＭＰａ）を示し、横軸は温度サイクル数（回）を示す。
　せん断試験用試料１では、サイクル数が５００回目であっても、極めて微細な亀裂が生じる以外は微細組織に変化がなく、初期強度が維持される信頼性の高いダイアタッチ接合を得ることができた。せん断試験用試料２では、金属間化合物層（Ｃｕ５Ｚｎ８層）で亀裂が生じるが、接合部分（半導体装置用接合材内部）には亀裂は伝播しないため、初期強度が維持される信頼性の高いダイアタッチ接合を得ることができた。
　せん断試験用試料１は約３６～３９ＭＰａのせん断強度を示し、せん断試験用比較試料のせん断強度の約３．５倍であった。
　このように、本発明の半導体装置１００及び半導体装置用接合材１３０によれば、融点が４２０℃である亜鉛を主成分とする半導体装置用接合材を用いるため、３００℃までの温度サイクルに耐え得る耐熱疲労に優れた次世代パワー半導体装置を得ることができる。
［不純物元素の添加による特性の変化］
　不純物元素の添加による特性の変化を調べるために試料１～５を用意した。試料１として、不純物元素を添加しない市販の亜鉛を用意した。この亜鉛の純度は９９．９９ｗｔ％であった。このような亜鉛は４Ｎと表される。ここでは、試料１における不純物元素の添加を行わない亜鉛を純亜鉛と呼ぶことがある。
　試料２～５として、上述の亜鉛に不純物元素Ｃａ、Ｍｎ、Ｔｉ、Ｃｒがそれぞれ０．１質量パーセント（０．１ｗｔ％）となるように添加した４つの添加物を用意した。試料２～５には、それぞれ、Ｃａ、Ｍｎ、ＴｉおよびＣｒが添加されている。
　具体的には、不純物を添加した亜鉛をアーク炉においてＡｒ雰囲気において融解し、その後、ひっくり返した。溶解およびひっくり返しを交互に３回行い、不純物元素を含む亜鉛合金を試料２～５として作製した。
　次に、試料１～５を引張試験用の試験片に加工した。図７に、試験片の模式図を示す。具体的には、試料１～５をそれぞれ鋳造し、それぞれの厚さが１０～１３ｍｍから１．３ｍｍになるまで圧延し、その後、放電加工を行った。このようにして、試料１～５から試験片１～５をそれぞれ形成した。
　次に、試験片１～５のそれぞれの厚さが１．２ｍｍになるように研磨を行い、１８０℃で３時間の熱処理を行い、残留応力を除去した。その後、アルミナ研磨剤で試験片１～５のそれぞれの研磨を行った。研磨では、アルミナ研磨剤の粒径を徐々に小さくしていき、最終的に粒径０．３μｍの研磨剤を用いた。
　以上のようにして試験片１～５をそれぞれ１０個用意し、引張試験を行った。伸長速度は７×１０－４ｍｍ／秒であった。なお、引張試験において標点距離以外の部分において破断した試験片の結果を無視し、また、残りの試験片の測定結果のうちの最大値および最小値を除外した６個ずつの平均を算出した。
　図８に、引張試験の結果を示す。図８（ａ）は、公称ひずみ（Ｎｏｍｉｎａｌ　Ｓｔｒａｉｎ）に対する公称応力（Ｎｏｍｉｎａｌ　Ｓｔｒｅｓｓ）を示し、図８（ｂ）に、試験片１～５の最大引張強さ（Ｕｌｔｉｍａｔｅ　Ｔｅｎｓｉｌｅ　Ｓｔｒｅｓｓ：ＵＴＳ）を示す。図８（ａ）および図８（ｂ）では、試験片１～５の結果をそれぞれ、Ｚｎ、０．１Ｃａ、０．１Ｍｎ、０．１Ｃｒ、０．１Ｔｉと示している。Ｃａ、Ｍｎ、ＣｒおよびＴｉの添加により、弾性域が拡大したとともにヤング率が増大した。特に、Ｔｉの添加により、ヤング率は著しく増大した。
　図９（ａ）に、試験片１～５のそれぞれの伸び率（Ｅｌｏｎｇａｔｉｏｎ）の結果を示す。試験片１の伸び率は５．０％と比較的低かったのに対して、不純物元素の添加された試験片２～４の伸び率は２０％以上を示した。このように、不純物元素の添加により、伸び率が増大することが分かった。
　図９（ｂ）に、０．２％耐力（ｐｒｏｏｆ　ｓｔｒｅｎｇｔｈ）の結果を示す。Ｃａ、Ｍｎ、Ｔｉの添加された試料２、３、５の耐力は試料１と比べて高かったが、Ｃｒの添加された試料４の耐力は試料１とほぼ同程度であった。試料４のように、試料２、３、５と比べて耐力の低い材料で半導体装置用接合材を形成することにより、半導体装置が衝撃を受けた場合の半導体部材へのダメージを吸収することができる。
　図１０に、各試料１～５の拡大像を示す。図１０（ａ）～図１０（ｅ）は、それぞれ、試料１～５の像である。試料１における亜鉛の結晶粒は比較的大きかったが、不純物元素の添加により、亜鉛の結晶の粒径が小さくなった。特に、ＣｒおよびＴｉの添加された試料４、５では亜鉛の結晶の粒径がかなり小さくなった。
　図１１（ａ）および図１１（ｂ）にＴｉの添加された試料５および試料１のそれぞれの初期組織における破断面の拡大像を示す。試料５には金属間化合物と考えられるところがある。試料５に対してエネルギー分散型Ｘ線分析（Ｅｎｅｒｇｙ　Ｄｉｓｐｅｒｓｉｖｅ　Ｘ－ｒａｙ　Ｓｐｅｃｔｒｏｓｃｏｐｙ：ＥＤＳ）を行ったところ、ＺｎおよびＴｉの質量％（ｗｔ％）は９９．４３、０．５７であり、原子数％（ａｔ％）は９９．２３、０．７７であった。
　また、試料１～５の酸化速度を熱重量分析（Ｔｈｅｒｍｏｇｒａｖｉｍｅｔｒｙ　Ａｎａｌｙｓｉｓ：ＴＧＡ）で測定した。ここでは、大気中４００℃で酸化を行った。図１２に、試料１～５の酸化時間に対する重量増加量（ｗｅｉｇｈｔ　ｇａｉｎ）の結果を示す。酸化時間に対する試料１の重量増加量は比較的大きかったのに対して、不純物元素の添加により、酸化時間に対する試料２～５の重量増加量は比較的小さくなった。特に、Ｃｒの添加により、重量増加量はかなり小さくなった。このように、不純物元素の添加（特に、Ｃｒの添加）により、亜鉛を主成分とする試料の酸化を抑制することができた。
　以上から、不純物元素の添加により、亜鉛の結晶が微細化し、これにともない、強度および伸び率が向上したと考えられる。
［亜鉛の純度による特性の変化］
　純度の異なる亜鉛を用いてその特性の比較を行った。ここでは、純度９９．９９ｗｔ％（４Ｎ）の亜鉛と、純度９９．９９９９ｗｔ％の亜鉛とを比較した。なお、純度９９．９９ｗｔ％の亜鉛（４Ｎ）の特性は図８および図９を参照して上述した結果と同様である。ここでは、試料６として純度９９．９９９９ｗｔ％の亜鉛を用意した。このような亜鉛は６Ｎと表される。試料６を厚さが１０～１３ｍｍから１．３ｍｍになるまで圧延した後、図７に示した形状となるように放電加工を行った。このようにして、試料６から試験片６を形成した。
　次に、試験片６のそれぞれの厚さが１．２ｍｍになるように研磨を行い、１８０℃で３時間の熱処理を行い、残留応力を除去した。その後、アルミナ研磨剤で試験片６の研磨を行った。研磨では、アルミナ研磨剤の粒径を徐々に小さくしていき、最終的に粒径０．３μｍの研磨剤を用いた。以上のようにして試験片６を３個用意し、引張試験を行った。伸長速度は７×１０－４ｍｍ／秒であった。
　図１３に、引張試験の結果を示す。図１３（ａ）は、公称ひずみ（Ｎｏｍｉｎａｌ　Ｓｔｒａｉｎ）に対する公称応力（Ｎｏｍｉｎａｌ　Ｓｔｒｅｓｓ）を示し、図１３（ｂ）に、試験片１、６の最大引張強さ（Ｕｌｔｉｍａｔｅ　Ｔｅｎｓｉｌｅ　Ｓｔｒｅｓｓ：ＵＴＳ）を示す。図１３（ａ）および図１３（ｂ）では、試験片１、６の結果をそれぞれ、４ＮＺｎ、６ＮＺｎと示している。亜鉛の高純度化に伴って弾性域が拡大した。
　図１４（ａ）に、試験片１、６のそれぞれの伸び率（Ｅｌｏｎｇａｔｉｏｎ）の結果を示す。試験片１の伸び率は５．０％と比較的低かったのに対して、試験片６の伸び率は８％以上であった。このように、亜鉛の高純度化に伴って伸び率が向上した。
　図１４（ｂ）に、０．２％耐力（ｐｒｏｏｆ　ｓｔｒｅｎｇｔｈ）の結果を示す。亜鉛の高純度化に伴って耐力が低減した。このように耐力の比較的低い材料で半導体装置用接合材を形成することにより、半導体装置が衝撃を受けた場合の半導体部材へのダメージを好適に吸収することができる。
　本発明による半導体装置及び半導体装置用接合材は、次世代パワー半導体として開発されているＧａＮ半導体装置やＳｉＣ半導体装置などの化合物半導体装置に利用可能である。
１００　　半導体装置
１１０　　基板
１１１　　絶縁層
１１２　　第１Ｃｕ層
１１３　　第２Ｃｕ層
１２０　　半導体部材
１３０　　半導体装置用接合材
１４０　　第１コート層
１４１　　第１保護層
１４２　　第１バリア層
１５０　　第２コート層
１５１　　第２保護層
１５２　　第２バリア層

Claims (15)

  1. 　基板に半導体部材を積層した半導体装置であって、
    　前記半導体部材と前記基板とは亜鉛を主成分とする半導体装置用接合材を介して接合されている、半導体装置。
  2. 　前記基板の表面および前記半導体部材の表面の少なくとも一方に前記半導体装置用接合材の拡散を防ぐコート層が設けられている、請求項１に記載の半導体装置。
  3. 　前記コート層は、窒化物、炭化物または炭窒化物からなるバリア層と、貴金属からなる保護層とを積層して構成される、請求項２に記載の半導体装置。
  4. 　前記バリア層を構成する窒化物、炭化物または炭窒化物は、前記基板に設けられた絶縁層を構成する物質が有する自由エネルギーよりも小さい自由エネルギーを有するように選択される、請求項３に記載の半導体装置。
  5. 　前記バリア層を構成する物質はＴｉＮであり、前記保護層を構成する物質はＡｕ、Ａｇ、Ｃｕ、Ｎｉ又はＰｄであり、前記基板に含まれる絶縁層を構成する物質はＳｉ３Ｎ４、Ａｌ２Ｏ３、又はＡｌＮである、請求項３又は請求項４に記載の半導体装置。
  6. 　前記半導体装置用接合材における亜鉛の純度は、９０ｗｔ％以上である、請求項１から請求項５の何れか一項に記載の半導体装置。
  7. 　前記半導体装置用接合材における亜鉛の純度は、９９．９９９９ｗｔ％以上である、請求項６に記載の半導体装置。
  8. 　前記バリア層の厚さは１００ｎｍから２０００ｎｍの範囲内にあり、前記保護層の厚さは２０ｎｍから５００ｎｍの範囲内にある、請求項４から請求項７の何れか一項に記載の半導体装置。
  9. 　前記半導体装置用接合材は、不純物元素を含む、請求項１から請求項８の何れか一項に記載の半導体装置。
  10. 　前記不純物元素は、Ｃａ、Ｍｎ、Ｔｉ、Ｃｒ、Ｎｉ、ＶおよびＮｂからなる群から選択された少なくとも１つの元素を含む、請求項９に記載の半導体装置。
  11. 　基板に半導体部材を積層した半導体装置において、前記半導体部材と前記基板とを接合する半導体装置用接合材であって、
    　亜鉛を主成分とする、半導体装置用接合材。
  12. 　前記亜鉛の純度は、９０ｗｔ％以上である、請求項１１に記載の半導体装置用接合材。
  13. 　前記亜鉛の純度は、９９．９９９９ｗｔ％以上である、請求項１２に記載の半導体装置用接合材。
  14. 　前記半導体装置用接合材は不純物元素を含む、請求項１１から請求項１３の何れか一項に記載の半導体装置用接合材。
  15. 　前記不純物元素は、Ｃａ、Ｍｎ、Ｔｉ、Ｃｒ、Ｎｉ、ＶおよびＮｂからなる群から選択された少なくとも１つの元素を含む、請求項１４に記載の半導体装置用接合材。
PCT/JP2011/054133 2010-03-01 2011-02-24 半導体装置及び半導体装置用接合材 WO2011108436A1 (ja)

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US13/581,941 US9217192B2 (en) 2010-03-01 2011-02-24 Semiconductor device and bonding material for semiconductor device
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