JPS61119049A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS61119049A
JPS61119049A JP24100584A JP24100584A JPS61119049A JP S61119049 A JPS61119049 A JP S61119049A JP 24100584 A JP24100584 A JP 24100584A JP 24100584 A JP24100584 A JP 24100584A JP S61119049 A JPS61119049 A JP S61119049A
Authority
JP
Japan
Prior art keywords
layer
backside
gold
tin
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24100584A
Other languages
English (en)
Inventor
Hisashi Sawaki
佐脇　久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24100584A priority Critical patent/JPS61119049A/ja
Publication of JPS61119049A publication Critical patent/JPS61119049A/ja
Pending legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、特にシリコン半導体素子層をリードフレーム
の素子搭載部に接着搭載する方法に関するものである。
（従来の技術） 従来、シリコン半導体素子裏面と該素子を搭載するリー
ドフレームの素子搭載部との図の接触”抵抗を小さく、
かつ、そのバラツキ金少くしてオーミックコンタクトを
得る方法として、半導体素子裏面と素子搭載部との間に
純金（９９，９９チ以上）の薄片をおいて４００Ｃ’前
後に加熱する。金−シリコン（以下、Ａ　ｕ　−８１と
略記する）共晶法が知られている。Ａｕ−８ｉ共晶法は
、接触抵抗が小さく、かつ、そのバラツキの少ない良好
なオーミック働コンタクトが得られるとして、広く使用
されているが、本法の欠点は、高価であることである。
さらに、Ａｕ−８ｉ共晶法は、半導体素子とリードフレ
ームとを硬く接着させるため、同素子とリードフレーム
との熱膨張係数の違いにより素子にクラックを発磁部せ
る欠点がある。
他の方法として、あらかじめ半導体索子Ｊ＆面に金等の
金属薄膜を形成しておいた半導体素子を、リードフレー
ムの素子搭載部に導電性樹脂を用いて接着する、導電ａ
樹脂法かある。導電性樹脂法は、非常に安価に製造でき
るか、半導体素子良面の加工方法及び半導体素子基板の
抵抗率によって接触抵抗が大きく変化する。又、接触抵
抗自体も比較的高い。
（発明が解決しようとする問題点） 以上の如く、Ａｕ−８ｉ共晶法は、接触抵抗は小さくバ
ラツキも少ないが高価であり、一方、導電性樹脂法は、
安価であるが接触抵抗のバラツキが大きい、欠点がある
。
（問題点を解決するための手段） 本発明の目的は、安価で、接触抵抗が小さく、かつ、そ
のバラツキも少ない、製造方法を提供するもので、本発
明は基本的には、導電性樹脂による方法を用いて安価に
製造し、さらにシリコン半導体基板の裏面加工方法に特
別の方法全採用することで、接触抵抗１Ａｕ−８ｉ共晶
法と同等に丁ゐことを％似とする。
（実施例） 以下、本発明を実施例に基づいて説明する。
１．３〜３．０Ω−画のシリコン半導体Ｐ型基板を用い
て、埋込拡散、エピタキシャル成長、拡散、酸化技術に
て製造されるパイ・ポーラ型半導体集積回路について述
べる。拡散勢の前工程は公知の方法によって製造される
。半導体基板ウェハの裏面研磨後の裏面加工として、順
に金（Ａｕ＝２００　ｏＡ）　を金（Ａｕ＝２００ＯＡ
）を形成する。ＩＮ目のＡｕｄ、電子ガンによって蒸着
した。２１ｉ目以降の金属は、スパッター装置を用いて
連続的に形成した。なおＴｉＮは、反応性スパッターを
用いた。しかる後、裏面加工済７　ｓ−八ｔ　％　４５
０　Ｃテ、３０分１’ｉ’ｌ　Ｎ　を雰囲気でシンター
処理した。この時、第一層目のＡｕは、基板シリコンと
反応して金・シリサイド（Ａｕ８ｉ）層を形成する。し
かし、第４層のＡｕは、Ｔｉ及びＴｉＮか拡散のバリア
となり、半導体基板裏面に残る。その後、約７０９にの
銀粉を含む導電性樹脂を用いてリードフレームに搭載す
る。
表−１に本発明および従来技術によって製造した半導体
集積回路装置の歩留りを示す。
表−１製品の歩留りと製造価格 なお、表−１で、従来法−１とあるのは、前記半導体素
子は単に、研磨のみを行ない、厚さ２０μのＡｕ薄膜を
用いて製造したものであり、従来法−２とあるのは、研
磨後、クエハ展面に、Ａ　ｕ薄膜を２００ＯＡ形成した
後、導電性樹脂を用いて接着させたものである。
他の実施例として、４〜５．５Ω−画のシリコン半導体
Ｎ型基板を用いて製造するＭＯａ型半導体集槓回路装置
について述べる。拡散等の前工程は、公知の方法により
て製造されるが、裏面加工としては、前記のＡｕ−Ｔ　
ｉ　−Ｔ　１Ｎ−Ａｕ構造のＡｕの代りに、０．２％の
ｓｂｌ含むＡｕを使用した。金属膜厚、熱処理条件等は
、前実施例と同様である、。
本実施例における結果を表−２に示す。な１６、従来法
−１′は前記Ａｕ薄膜の代りに、０．２−のｓｂを含む
Ａｕ薄膜を使用した。従来法−２′は、従来法−２と、
まったく同様のプロセスで製造した。
表−２＃品の歩留りと製造価格 なお、本仕様で、熱処理条件に４５０ｔｌ：’、３０分
とした力；本条件は％　Ａｕｉ＋１の生成する３７０Ｃ
から、ＴｉＮか拡散バリアとして有効な、４８０ｔＺ’
程民の範−１で、問題はない。又、各金杷の厚さについ
ては、紅済性の而から考えて炉くすることは可能である
。任し、ＴｉＮについては、第１１Ｎ３のＡｕの拡散バ
リアとの目的があるため、５００Ｘ装置は必要であり、
これ以上薄くすることは出来ない。さらに、本実施例で
は、比較的高抵抗率基板について例示したが低い抵抗率
のシリコン基板を用いても、効果があることは云うまで
もない。
さらにまた、ＴｉＮＶｉＡｕ又はｓｂを含むＡｕに対し
てバリア層を形成するものであるから、これに限定され
ない。
（発明の効果） 以上のとおり、本発明によれば、安価で接触抵抗のバラ
ツキが少ない方法が提供される。

Claims (1)

    【特許請求の範囲】
  1. 　シリコン半導体素子の裏面に、少なくともＡｕを主成
    分とする第１の金属層、Ａｕの拡散に対するバリアとし
    て作用する第２の金属層、およびＡｕを主成分とする第
    ３の金属層をこの順に形成し、熱処理を施した後に導電
    性樹脂を用いて素子搭載基板に接着することを特徴とす
    る半導体装置の製造方法。
JP24100584A 1984-11-15 1984-11-15 半導体装置の製造方法 Pending JPS61119049A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24100584A JPS61119049A (ja) 1984-11-15 1984-11-15 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24100584A JPS61119049A (ja) 1984-11-15 1984-11-15 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS61119049A true JPS61119049A (ja) 1986-06-06

Family

ID=17067911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24100584A Pending JPS61119049A (ja) 1984-11-15 1984-11-15 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS61119049A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0253691A2 (en) * 1986-06-17 1988-01-20 Fairchild Semiconductor Corporation Silicon die bonding process
EP0756325A3 (de) * 1995-07-27 1998-12-30 Philips Patentverwaltung GmbH Halbleitervorrichtung mit einem Träger
WO2011108436A1 (ja) * 2010-03-01 2011-09-09 国立大学法人大阪大学 半導体装置及び半導体装置用接合材

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0253691A2 (en) * 1986-06-17 1988-01-20 Fairchild Semiconductor Corporation Silicon die bonding process
EP0756325A3 (de) * 1995-07-27 1998-12-30 Philips Patentverwaltung GmbH Halbleitervorrichtung mit einem Träger
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JP5773344B2 (ja) * 2010-03-01 2015-09-02 国立大学法人大阪大学 半導体装置及び半導体装置用接合材
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