JP2983486B2 - ろう材料層を有する半導体基体 - Google Patents

ろう材料層を有する半導体基体

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Publication number
JP2983486B2
JP2983486B2 JP9047059A JP4705997A JP2983486B2 JP 2983486 B2 JP2983486 B2 JP 2983486B2 JP 9047059 A JP9047059 A JP 9047059A JP 4705997 A JP4705997 A JP 4705997A JP 2983486 B2 JP2983486 B2 JP 2983486B2
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JP
Japan
Prior art keywords
layer
semiconductor substrate
brazing
support plate
material layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9047059A
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English (en)
Other versions
JPH1012507A (ja
Inventor
シユネーガンス マンフレート
ヒユープナー ホルガー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH1012507A publication Critical patent/JPH1012507A/ja
Application granted granted Critical
Publication of JP2983486B2 publication Critical patent/JP2983486B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Die Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、金属製支持板と、
ろう付け前にシリコンから出発して支持板に向かう方向
にアルミニウム合金層および拡散障壁層を含んでいる一
連の金属層を介してろう付けすることのできるシリコン
から成る半導体基体に関する。
【０００２】
【従来の技術】このような半導体基体は多数市販されて
いる半導体デバイス、特に電力用半導体デバイスに組み
込まれている。一連の金属層は一般に、シリコン半導体
基体に接しているアルミニウム層を含んでいる。アルミ
ニウム層はシリコンに良好に付着し、またｐドープされ
たシリコンと十分なオーム接触を形成する。アルミニウ
ム層には従来技術により、普通はチタンまたはクロムか
ら成っておりまた拡散障壁層に接しているニッケル層と
アルミニウム層との間の付着仲介剤および背面障壁とし
ての役割をする拡散障壁層が設けられている。ニッケル
層には従来技術により直接に、またはそれに続く付着改
善の役割をする薄いチタン層に、普通は銀、金またはパ
ラジウムから成っておりまたニッケル層に対する酸化保
護の役割をする貴金属層が被覆される。
【０００３】本来のろう付け工程の際に、こうして金属
化された半導体基体背面と金属製支持板との間には一般
に、普通亜鉛および融剤から成るろう板片が置かれる。
ろう付け工程の際に次いで、支持板と半導体基体の銀層
との間に挟まれているろう層が溶融し、その際に次いで
銀層が溶解し、また後続のニッケル層がろう材料により
溶解し、またろう結合が形成される。
【０００４】しかしこの一般に知られているろう付け方
法は大きな欠点を有する。一方ではニッケルおよびシリ
コン半導体基体の熱膨張係数が異なることにより、特に
薄い半導体基体（厚み≦２５０μｍ）において強いウェ
ハの曲げ（曲げ＞１０００μｍ）に通ずる機械的応力が
惹起される。
【０００５】それによりウェハの“ハンドリング”が困
難になり、カセットの位置決め誤差が増大し、またウェ
ハの加工の際の破損の危険が増大する。
【０００６】この問題はこれまで、ろう付けがなお十分
な付着性を示すようにニッケル層の厚みを最小にするこ
とによって対処されてきた。しかしニッケル層の厚みの
減少（≒１μｍ）にもかかわらず、製造中にはさらに上
記の問題に通ずる７００ないし２０００μｍのウェハの
曲げが生ずる。
【０００７】
【発明が解決しようとする課題】従って本発明の課題
は、シリコン半導体基体を、保持体材料への付着性を犠
牲にすることなしにウェハの曲げが顕著に減ぜられるよ
うに金属化することにある。
【０００８】
【課題を解決するための手段】この課題は、冒頭に記載
した種類のシリコン半導体基体の拡散障壁層にろう材料
層が被覆されることにより解決される。
【０００９】ろう材料層として錫または鉛またはガリウ
ム層が設けられると有利である。
【００１０】このような半導体基体は次いで金属の支持
板に被覆され、約２５０℃以上の高い温度への加熱によ
り直接に、すなわち別のろう材料および融剤を用いずに
支持板とろう付けされる。
【００１１】それにより、３００μｍ以下の基板曲げし
か生じないほぼ無応力のろう層が形成される。さらに、
ろう付けされた半導体基体の支持板上への付着性が非常
に高い。すなわち３０ＭＰａよりも大きい範囲内にあ
る。従って温度の交番負荷による損傷が生じない。なぜ
ならば金属相がごく薄くしか生じていないからである。
全体としてこうしてウェハの“ハンドリング”中の問題
および損傷の危険が回避される。
【００１２】さらに、本発明により金属化された半導体
基体および本発明による方法により顕著なコストの低減
が達成される。なぜならば、材料コストが特に酸化保護
層の省略により低減され、またスループットが高められ
るからである。さらに本発明による方法は特に環境にや
さしい。なぜならば融剤が使用されないので、ＦＣＫＷ
溶剤による洗浄工程が省略されるからである。
【００１３】
【実施例】図面にはろう付け前の金属の層列が示されて
いる。本発明により半導体基体１には、シリコンに良好
に付着しまた特にｐドープされたシリコンと共に十分な
オーム接触を形成するアルミニウム層３が被覆されてい
る。アルミニウム層３には、約５０ｎｍの厚みを有する
クロムまたはチタンから成る拡散障壁層４が設けられて
いる。この層はアルミニウム層３に直接スパッタされも
しくは直接蒸着される。拡散障壁層４には付着仲介剤、
たとえば銅が被覆され（図示されていない）、またはろ
う材料が直接に被覆される。ろう層は錫、ガリウムもし
くは鉛から成っており、また１０００ないし３０００ｎ
ｍの厚み、錫を使用する際にはたとえば約２７００ｎｍ
の厚みを有する。こうして金属化されたシリコン半導体
基体１は次いで一般に銅から成る金属の支持板２に押し
付けられ、また約３００℃において保護ガス雰囲気のも
とにまたは真空条件のもとに支持板２と結合され、その
際に拡散障壁層４、ろう材料層５および支持板２の間に
冶金学的結合が生じ、この結合は約４５０℃まで安定で
ある。
【００１４】本発明による方法を使用すれば、高い品質
の製品が製造される。なぜならば、前記の層列が特に良
好な機械的および電気的に安定な接触を生ずるからであ
る。特に本発明による方法は技術的な観点でも経済的お
よびエコロジー的な観点でも従来技術にくらべて非常に
有利である。
【００１５】技術的には本発明による方法により、シリ
コン半導体基板の厚みを一層減少する可能性が開かれ、
このことは電力用半導体テバイスにおける導通特性の改
善に通ずる。経済的には、材料コストを低減することが
でき、また製造中のスループットが高められるという利
点が得られる。最後に本発明による方法のエコロジー的
な利点は、融剤なしでろう付けされるので、ＦＣＫＷを
含有する溶剤による洗浄工程が回避されることにある。
【図面の簡単な説明】
【図１】本発明によるろう付け前の層列を示す断面図。
【符号の説明】
１ 半導体基体 ２ 支持板 ３ アルミニウム層 ４ 拡散障壁層 ５ ろう材料層
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭57−102032（ＪＰ，Ａ) 特開 昭62−194650（ＪＰ，Ａ) 特開 昭63−4629（ＪＰ，Ａ) 特開 平３−262137（ＪＰ，Ａ) 特開 平５−175252（ＪＰ，Ａ) 特開 平８−213713（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/02 H01L 21/52

Claims (5)

    (57)【特許請求の範囲】
  1. 【請求項１】 金属製支持板（２）と、ろう付け前にシ
    リコンから出発して支持板に向かう方向にアルミニウム
    合金層（３）および拡散障壁層（４）を含んでいる一連
    の金属層を介してろう付けされるシリコンから成る半導
    体基体（１）において、拡散障壁層（４）にろう材料層
    （５）が被覆されることを特徴とするろう材料層を有す
    る半導体基体。
  2. 【請求項２】 ろう材料層（５）として錫または鉛また
    はガリウム層が設けられていることを特徴とする請求項
    １記載の半導体基体。
  3. 【請求項３】 拡散障壁層（４）の厚みが約５０ｎｍで
    あることを特徴とする請求項１または２記載の半導体基
    体。
  4. 【請求項４】 ろう材料層（５）の厚みが１０００ない
    し３０００ｎｍであることを特徴とする請求項１または
    ２記載の半導体基体。
  5. 【請求項５】 金属製支持板（２）に請求項１ないし５
    の１つによる半導体基体をろう付けするための方法にお
    いて、半導体基体（１）が支持板（２）に被覆され、ま
    た約２５０℃以上の高い温度への加熱により直接に支持
    板（２）とろう付けされることを特徴とする半導体基体
    のろう付け方法。
JP9047059A 1996-02-19 1997-02-14 ろう材料層を有する半導体基体 Expired - Fee Related JP2983486B2 (ja)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8461645B2 (en) 2011-03-16 2013-06-11 Infineon Technologies Austria Ag Power semiconductor device
US9082878B2 (en) 2010-09-09 2015-07-14 Infineon Technologies Ag Method of fabricating a power semiconductor chip package

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19639438A1 (de) 1996-09-25 1998-04-02 Siemens Ag Halbleiterkörper mit Lotmaterialschicht
US6118351A (en) * 1997-06-10 2000-09-12 Lucent Technologies Inc. Micromagnetic device for power processing applications and method of manufacture therefor
US6440750B1 (en) 1997-06-10 2002-08-27 Agere Systems Guardian Corporation Method of making integrated circuit having a micromagnetic device
DE19735760A1 (de) * 1997-08-18 1999-02-25 Zeiss Carl Fa Lötverfahren für optische Materialien an Metallfassungen und gefaßte Baugruppen
DE19740904B4 (de) * 1997-09-17 2004-10-28 Infineon Technologies Ag Verfahren zum Beseitigen von Sauerstoff-Restverunreinigungen aus tiegelgezogenen Siliziumwafern
US6255714B1 (en) 1999-06-22 2001-07-03 Agere Systems Guardian Corporation Integrated circuit having a micromagnetic device including a ferromagnetic core and method of manufacture therefor
KR100594565B1 (ko) * 1999-08-04 2006-06-28 삼성전자주식회사 액정표시장치
DE19951945A1 (de) * 1999-10-28 2001-05-03 Daimler Chrysler Ag Halbleiterbauelement mit Seitenwandmetallisierung
JP4544675B2 (ja) * 1999-12-21 2010-09-15 ローム株式会社 半導体装置の製造方法
EP1320889A1 (de) * 2000-09-29 2003-06-25 Infineon Technologies AG Verbindungseinrichtung
DE10124141B4 (de) * 2000-09-29 2009-11-26 Infineon Technologies Ag Verbindungseinrichtung für eine elektronische Schaltungsanordnung und Schaltungsanordnung
DE10103294C1 (de) * 2001-01-25 2002-10-31 Siemens Ag Träger mit einer Metallfläche und mindestens ein darauf angeordneter Chip, insbesondere Leistungshalbleiter
DE102004001956B4 (de) 2004-01-13 2007-02-01 Infineon Technologies Ag Umverdrahtungssubstratstreifen mit mehreren Halbleiterbauteilpositionen
US7347354B2 (en) * 2004-03-23 2008-03-25 Intel Corporation Metallic solder thermal interface material layer and application of the same
US7868472B2 (en) * 2004-04-08 2011-01-11 Avago Technologies General Ip (Singapore) Pte. Ltd. Thermal dissipation in integrated circuit systems
JP4882229B2 (ja) * 2004-09-08 2012-02-22 株式会社デンソー 半導体装置およびその製造方法
DE102005031836B4 (de) 2005-07-06 2007-11-22 Infineon Technologies Ag Halbleiterleistungsmodul mit SiC-Leistungsdioden und Verfahren zur Herstellung desselben
DE602005015103D1 (de) 2005-07-28 2009-08-06 Infineon Technologies Ag Verbindungsstruktur zur Befestigung eines Halbleiterchips auf einem Metallsubstrat, Halbleiterchip und elektronisches Bauelement mit der Verbindungsstruktur, und Verfahren zur Herstellung der Verbindungsstruktur
DE102005052563B4 (de) 2005-11-02 2016-01-14 Infineon Technologies Ag Halbleiterchip, Halbleiterbauteil und Verfahren zu deren Herstellung
US7508012B2 (en) 2006-01-18 2009-03-24 Infineon Technologies Ag Electronic component and method for its assembly
US8951478B2 (en) * 2006-03-30 2015-02-10 Applied Materials, Inc. Ampoule with a thermally conductive coating
DE102006031405B4 (de) * 2006-07-05 2019-10-17 Infineon Technologies Ag Halbleitermodul mit Schaltfunktionen und Verfahren zur Herstellung desselben
DE102006048448A1 (de) * 2006-10-11 2008-04-17 Endress + Hauser Wetzer Gmbh + Co. Kg Erzeugen einer Lotverbindung
US9214442B2 (en) 2007-03-19 2015-12-15 Infineon Technologies Ag Power semiconductor module, method for producing a power semiconductor module, and semiconductor chip
CN101950737A (zh) * 2009-11-23 2011-01-19 杭州士兰集成电路有限公司 P型硅衬底背面金属化的制作方法
US8587116B2 (en) 2010-09-30 2013-11-19 Infineon Technologies Ag Semiconductor module comprising an insert
DE102016226103B3 (de) 2016-12-22 2018-05-09 Conti Temic Microelectronic Gmbh Verfahren zur Herstellung einer elektrischen Verbindung und elektrische Verbindung zwischen zwei Komponenten
US10910508B1 (en) * 2018-05-04 2021-02-02 National Technology & Engineering Solutions Of Sandia, Llc Method of fabricating photosensitive devices with reduced process-temperature budget

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2474039A (en) * 1945-03-03 1949-06-21 Metals & Controls Corp Method of forming composite metal having a nickel-plated beryllium-copper base and gold or silver bonded thereto by a copper-plated iron sheet
GB1149606A (en) * 1967-02-27 1969-04-23 Motorola Inc Mounting for a semiconductor wafer which is resistant to fatigue caused by thermal stresses
DE2522773A1 (de) * 1973-08-09 1976-12-02 Siemens Ag Weichgeloetete kontaktanordnung
US4451972A (en) * 1980-01-21 1984-06-05 National Semiconductor Corporation Method of making electronic chip with metalized back including a surface stratum of solder
DE3406542A1 (de) * 1984-02-23 1985-08-29 Telefunken electronic GmbH, 7100 Heilbronn Verfahren zum herstellen eines halbleiterbauelementes
JPS63238994A (ja) * 1987-03-25 1988-10-05 Tdk Corp 半田組成物
DE3740773A1 (de) * 1987-12-02 1989-06-15 Philips Patentverwaltung Verfahren zum herstellen elektrisch leitender verbindungen
DE3823347A1 (de) * 1988-07-09 1990-01-11 Semikron Elektronik Gmbh Leistungs-halbleiterelement
DE69021438T2 (de) * 1989-05-16 1996-01-25 Marconi Gec Ltd Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung.
US5027189A (en) * 1990-01-10 1991-06-25 Hughes Aircraft Company Integrated circuit solder die-attach design and method
DE9212486U1 (de) * 1992-09-16 1993-03-04 Siemens AG, 8000 München Halbleiterkörper mit verlöteter Trägerplatte
DE69325065T2 (de) * 1992-10-02 1999-10-28 Matsushita Electric Ind Co Ltd Halbleitervorrichtung, Bildabtastvorrichtung und Verfahren zu ihrer Herstellung
DE4241439A1 (de) * 1992-12-10 1994-06-16 Daimler Benz Ag Verfahren zur Erzeugung einer formschlüssigen Verbindung zwischen metallischen Verbindern und metallischen Kontakten von Halbleiteroberflächen
US5816478A (en) * 1995-06-05 1998-10-06 Motorola, Inc. Fluxless flip-chip bond and a method for making
US5803343A (en) * 1995-10-30 1998-09-08 Delco Electronics Corp. Solder process for enhancing reliability of multilayer hybrid circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9082878B2 (en) 2010-09-09 2015-07-14 Infineon Technologies Ag Method of fabricating a power semiconductor chip package
US8461645B2 (en) 2011-03-16 2013-06-11 Infineon Technologies Austria Ag Power semiconductor device

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JPH1012507A (ja) 1998-01-16
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US5901901A (en) 1999-05-11
CN1168536A (zh) 1997-12-24
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SG69995A1 (en) 2000-01-25
ATE265090T1 (de) 2004-05-15
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EP0790647A2 (de) 1997-08-20
DE59711523D1 (de) 2004-05-27

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