TW201308543A - 接合構造體 - Google Patents

接合構造體 Download PDF

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Publication number
TW201308543A
TW201308543A TW101119420A TW101119420A TW201308543A TW 201308543 A TW201308543 A TW 201308543A TW 101119420 A TW101119420 A TW 101119420A TW 101119420 A TW101119420 A TW 101119420A TW 201308543 A TW201308543 A TW 201308543A
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Taiwan
Prior art keywords
layer
electrode
modulus
young
intermediate layer
Prior art date
Application number
TW101119420A
Other languages
English (en)
Inventor
Taichi Nakamura
Hidetoshi Kitaura
Akihiro Yoshizawa
Original Assignee
Panasonic Corp
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Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Publication of TW201308543A publication Critical patent/TW201308543A/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/264—Bi as the principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
    • B23K35/007—Interlayers, transition pieces for metallurgical bonding of workpieces at least one of the workpieces being of copper or another noble metal
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0233—Sheets, foils
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
    • B32B15/016—Layered products comprising a layer of metal all layers being exclusively metallic all layers being formed of aluminium or aluminium alloys
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
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Abstract

於經由以Bi為主成分之接合材料104將半導體元件102接合於Cu電極103上而成之接合構造體106中，經由如楊氏模數自接合材料104朝向被接合材料(半導體元件102、Cu電極103)傾斜地增大之積層體209a而接合半導體元件102與Cu電極103，藉此確保對於功率半導體模組之使用時之溫度循環中產生之熱應力的應力緩和性。

Description

接合構造體
本發明係關於半導體零件之內部接合，尤其係關於一種要求優異之機械特性與耐熱性之經由Bi系焊錫接合功率半導體模組之半導體元件與電極而成之接合構造體。
於電子安裝領域中，自先前以來，多用Sn-Pb共晶焊錫，但由於擔心鉛之有害性或對環境之關注度提高，故近年來期待不使用鉛之接合。
因此，對於作為通常之焊錫材之Sn-Pb共晶焊錫，正開發其替代材料並使之實用化。
另一方面，關於半導體零件之內部接合，對高溫鉛焊錫之替代材料進行了各種研究。
對於該替代焊錫材料之候補，可列舉Au系、Zn系、Sn系、Bi系焊錫材料。其中，關於Au系之焊錫材料，因如下等理由而不具有通用性：例如，使熔點為280℃之Au-20重量%Sn等部分實用化，但由於主成分為Au，故材料物性較硬，而且材料成本較高，而限定為使用於小型零件中。
Zn系之焊錫材料由於腐蝕性較強，而且彈性模數過高，故於應用於半導體零件之內部接合時機械特性之提高成為課題。
Sn系之焊錫材料雖然具有優異之機械特性，但熔點低至未達250℃而缺乏耐熱性。因此，為了提高Sn系之耐熱性，研究例如藉由形成SnCu化合物而利用金屬間化合物化 來提高熔點之接合材料，但由於金屬間化合物化時之凝固收縮會導致於接合時產生空隙，故於改善機械特性、散熱特性方面存在問題。
因此種理由，將熔點為270℃附近之Bi系作為高溫鉛焊錫替代材料之有力候補而進行研究。
例如，專利文獻1係將該Bi系之焊錫材料用於接合材料之例。
圖8係專利文獻1所記載之先前之接合構造體之剖面圖，功率半導體模組401中，於功率半導體元件402與電極403之間具有接合部404，於該接合部404中使用有Bi-Ag系焊錫材料，且含有15~60重量%之Ag。
然而，若功率半導體元件402之動作溫度為於Si之情形時之150℃，則專利文獻1所記載之Bi-Ag系焊錫材料具有接合可靠性，但於功率半導體元件402之動作溫度為GaN、SiC等動作溫度高於Si之175℃、或200℃之環境下，專利文獻1所記載之Bi-Ag系焊錫材料有於接合部404產生龜裂、剝離等之虞。
認為其原因在於：對於基於功率半導體元件402之熱膨脹係數(α3 ppm/K)、與Cu電極403之線膨脹係數(α18 ppm/K)之差的熱應力，Bi-Ag系焊錫材料無法完全地應力緩和，因此會於接合部404產生龜裂、剝離等。
因此，上述專利文獻1所記載之利用Bi-Ag系焊錫材料之接合構造體中，於功率半導體元件402之動作溫度高於150℃之情形時，對於該高溫區域之應力緩和性之提高成 為課題。
另一方面，專利文獻2之課題在於：防止接合構造體之龜裂或剝離。
於專利文獻2中表示有如下方法：藉由使被覆形成於半導體元件上之保護樹脂亦被覆形成於半導體元件之中間接合層與焊錫接合層之間之外周面區域，而提高半導體元件內部之耐龜裂性，且減輕施加於半導體元件與焊錫材料之界面、或焊錫材料與電極之界面之熱應力。
先前技術文獻 專利文獻
專利文獻1：日本專利特開2006-310507號公報
專利文獻2：日本專利特開2011-023631號公報
於專利文獻2所記載之發明中，藉由將保護樹脂被覆填充於特定區域，而實現包含隔著焊錫材料之半導體元件與電極之接合構造體之應力緩和性的提高，但本發明之技術性課題在於：利用與以填充保護樹脂作為特徵之專利文獻2中所記載之發明不同的方法，於功率半導體模組之接合構造體中，改善應力緩和性，而防止接合部產生龜裂或剝離。
本發明者等人考慮到藉由形成如對於外部應力之應變自接合材料朝向被接合材料(半導體元件、Cu電極)傾斜地變 化之積層構造體，而有效地緩和、吸收基於被接合材料(半導體元件、Cu電極)之熱膨脹係數差的熱應力，從而完成了本發明。
本發明1係一種接合構造體，其係藉由以Bi為主成分之接合材料將半導體元件接合於Cu電極而成者，其特徵在於：由上述接合材料與形成於該接合材料之表面之中間層構成積層體，經由該積層體而接合上述半導體元件之表面之Cu與上述Cu電極，且於將上述半導體元件之表面之Cu之楊氏模數(Young modulus)設為E1，將上述中間層之楊氏模數設為E2，將上述接合材料之楊氏模數設為E3，將上述Cu電極之楊氏模數設為E4之情形時，以各楊氏模數E1~E4滿足以下條件(p1)、(q1)之兩者或其中一者之方式，相對於上述半導體元件及上述Cu電極構成上述積層體 E3<E2<E1………(p1)
E3<E2<E4………(q1)。
本發明2係如上述發明1之接合構造體，其特徵在於：上述積層體為包含上述接合材料、及形成於該接合材料之上、下兩面之2個中間層的3層之積層體，且若將上述半導體元件之側之第1中間層之楊氏模數設為E21，將上述Cu電極之側之第2中間層之楊氏模數設為E24，則以各楊氏模數E1、E21、E24、E3、E4滿足以下條件(p2)及(q2)之方式，相對於上述半導體元件及上述Cu電極構成3層之積層體 E3<E21<E1………(p2)
E3<E24<E4………(q2)。
本發明3係如上述發明1之接合構造體，其特徵在於：上述積層體為包含上述接合材料、及形成於該接合材料之上述半導體元件之側之中間層的2層之積層體，且於將上述半導體元件之側之中間層之楊氏模數設為E21之情形時，以各楊氏模數E1、E21、E3滿足以下條件(p2)之方式，相對於上述半導體元件及上述Cu電極構成2層之積層體 E3<E21<E1………(p2)。
本發明4係如上述發明1之接合構造體，其特徵在於：上述積層體為包含上述接合材料、及形成於該接合材料之上述Cu電極之側之中間層的2層之積層體，且於將上述中間層之楊氏模數設為E24之情形時，以各楊氏模數E24、E3、E4滿足以下條件(q2)之方式，相對於上述半導體元件及上述Cu電極構成2層之積層體 E3<E24<E4………(q2)。
本發明5係如上述發明1~4中任一發明之接合構造體，其特徵在於：上述中間層係選自由AuSn化合物、AgSn化合物、CuSn化合物、Au、及Ag所組成之群中之金屬的至少一種。
本發明6係如上述發明1~5中任一發明之接合構造體，其特徵在於：上述中間層為CuSn化合物。
本發明經由如楊氏模數自接合材料朝向被接合材料傾斜地增大之積層構造而接合半導體元件與Cu電極，藉此，相對於功率半導體模組之使用時之溫度循環中產生之熱應 力，而發揮所謂之彈簧效果從而顯現優異之應力緩和功能，故可品質良好地接合半導體元件與電極，並且可提高接合可靠性。
實施形態1所記載之發明係一種接合構造體，其係藉由以Bi為主成分之接合材料將半導體元件接合於Cu電極而成者，由接合材料與形成於該接合材料之表面之中間層構成積層體，經由該積層體接合半導體元件之表面之Cu與上述Cu電極，且使各楊氏模數朝向上述接合材料、上述中間層、上述半導體元件之一方向、或朝向上述接合材料、上述中間層、上述Cu電極之一方向依序增大，或者，進而使各楊氏模數自上述接合材料經由中間層而朝向上述半導體元件與上述Cu電極之兩方向依序增大。
若容易理解地說明該接合構造體，則於接合構造體中，於將半導體元件之表面之Cu之楊氏模數設為E1，將上述中間層之楊氏模數設為E2，將上述接合材料之楊氏模數設為E3，且將上述Cu電極之楊氏模數設為E4之情形時，以各楊氏模數E1~E4滿足以下條件(p1)、(q1)之兩者或其中一者之方式，相對於上述半導體元件與上述Cu電極構成上述積層體 E3<E2<E1………(p1)
E3<E2<E4………(q1)。
又，以下說明之實施形態2~4所記載之發明為實施形態1所記載之發明之下階概念性發明，實施形態2所記載之發 明係於上述接合材料之上、下兩面形成中間層，並使該3層之積層體(中間層、接合材料、中間層)介於上述半導體元件與上述Cu電極之間，且使各楊氏模數自上述接合材料經由上述中間層而朝向上述半導體元件與上述Cu電極之兩面依序增大，從而實現應力緩和。
繼而，實施形態3所記載之發明係於上述接合材料之面向上述半導體元件之面形成中間層而構成2層之積層體(中間層、接合材料)，且使各楊氏模數朝向上述接合材料、上述中間層、上述半導體元件依序增大，從而緩和應力。
實施形態4所記載之發明係如下接合構造體：於上述接合材料之上述Cu電極之側之面形成中間層而構成2層之積層體(中間層、接合材料)，且與實施形態3所記載之發明同樣地使各楊氏模數依序增大，從而實現應力緩和。
再者，於實施形態所記載之發明中，作為電極、或下述障壁金屬層之最下層之材質的銅為包含銅以及銅合金之概念。
以下，基於圖示說明實施形態所記載之發明。
圖1係將實施形態所記載之發明之接合構造體設為構成要素之安裝構造體的剖面圖。
首先，藉由接合材料104接合半導體元件102與Cu電極103而形成接合構造體106，繼而，以密封樹脂105密封接合構造體106而形成功率半導體模組100，最後，使用焊錫材料109將功率半導體模組100安裝於基板101上，而形成安裝構造體110。
對接合構造體106進行詳細敍述。
圖2A、圖2B、圖2C係接合構造體106之製造步驟圖。此處，對如圖2C所示般於接合材料104之下表面形成有第2中間層206、且於接合材料104之上表面形成有第1中間層207之情形，亦即，插入有3層之積層體209a之情形進行說明。
首先，圖2A係供給Cu電極103之步驟圖。
於供給Cu電極103時，在含有5%之氫之氮氣環境中(室溫)供給Cu電極103。藉由電解電鍍法使作為表面處理層之Ag層201、及電極表面處理層202預先成膜於包含Cu合金之Cu電極103上。
圖2B係將具備Bi層203之半導體元件102載置於作為Cu電極103之表面處理層之Ag層201上之步驟圖。
於載置半導體元件102時，在含有5%之氫之氮氣環境中將Cu電極103加熱至320℃。
於包含GaN、厚度為0.3 mm、大小為4 mm×5 mm之半導體元件102上，藉由蒸鍍法，預先自GaN側起成膜包含Cr 0.1 μm/Ni 1 μm/Cu 3 μm之多層之障壁金屬層204、及Bi基礎層205，又，藉由電解電鍍法於Bi基礎層205上成膜包含厚度10 μm之Bi之Bi層203。
若對上述障壁金屬層204進行敍述，則半導體元件102側之Cr係為了藉由與Si歐姆接合來確保導通而成膜。
又，障壁金屬層204之Ni係為了防止由Cu成分擴散至半導體元件之器件中所導致之器件功能下降，亦即用於防止 Cu之擴散而成膜。
障壁金屬層204之Cu係與上述Bi基礎層205接觸之層。設置該Cu層之理由在於，因存在上述Bi層203之Bi與Ni於界面形成金屬間化合物Bi3Ni，該較脆之金屬化合物層於例如功率半導體模組之使用時因熱應力而變形時成為龜裂之起點之虞，故於Bi與障壁金屬層之Ni之間成膜Cu而防止Bi向Ni擴散。
選定Cu之原因在於，由於Cu係對於Bi之溶解量較少(0.4 at%左右)之金屬，故發揮防止Bi之擴散之障壁效果。又，關於Cu之厚度，若為1 μm以上則可防止Bi之擴散，但考慮到利用電鍍法之成膜厚度之偏差為2 μm，而設為3 μm。
以上述Bi層203與作為Cu電極103之表面處理層之Ag層201接觸之方式，以50 gf~150 gf左右之荷重將半導體元件102載置於Cu電極103上。
另外，於下述本發明之實施例中，以60 gf之荷重將半導體元件102載置於Cu電極103上。
圖2C係藉由自然冷卻使Ag層201之一部分擴散至經熔融之Bi層203之狀態之接合材料104凝固之步驟圖。於該圖2C之步驟中，在含有5%之氫之氮氣環境中進行自然冷卻，而使接合材料104凝固，藉此使Cu電極103與半導體元件102接合，從而製造接合構造體106。
對接合材料104進行說明。
如上所述，於圖2B~圖2C之Bi層203熔融直至凝固期間，作為Cu電極103之表面處理層之Ag層201擴散至Bi 中。
由於上述Bi層203之Bi與Ag形成<Bi-3.5重量%Ag>之2元共晶，故Ag相對於Bi擴散後之接合材料104之熔點為262℃。
形成Ag層201作為Cu電極103之表面處理層之目的在於，為了確保熔融Bi相對於半導體元件102之下部整個面之濕潤性。
對第2中間層206、第1中間層207進行說明。
首先，第2中間層206係於320℃之加熱狀態下藉由電極表面處理層202中之擴散反應、或藉由電極表面處理層202與Cu電極103之Cu之擴散反應而形成之層。
同樣地，第1中間層207亦係於320℃之加熱狀態下藉由Bi基礎層205中之擴散反應、或藉由作為障壁金屬層204之最下層之Cu與Bi基礎層205之擴散反應而形成之層。
上述接合構造體106係將Cu電極103與半導體元件102之表面之Cu經由第2中間層206、接合材料104及第1中間層207之3層之積層體209a進行接合而成者。於接合部208之應力緩和中，必需使各楊氏模數朝向接合材料104、第2中間層206、及Cu電極103、或朝向接合材料104、第1中間層207、及半導體元件102依序增大，亦即傾斜地增大。
此係藉由使上述第1中間層207之楊氏模數處於接合材料104之楊氏模數與半導體元件102之表面之楊氏模數之間，亦即取中間值，且使第2中間層206之楊氏模數處於接合材料104之楊氏模數與Cu電極103之楊氏模數之間，亦即取中 間值而達成。
對3層之積層體209a進行更詳細之說明。
若將面向半導體元件102之側之第1中間層207之楊氏模數設為E21，且將面向Cu電極103之側之第2中間層206之楊氏模數設為E24，則於將半導體元件102之表面之Cu之楊氏模數設為E1，將接合材料104之楊氏模數設為E3，且將Cu電極103之楊氏模數設為E4之情形時，以滿足以下條件(p)及(q)之方式，相對於半導體元件102及Cu電極103構成上述積層體209a E3<E21<E1………(p)
E3<E24<E4………(q)。
於此情形時，所謂中間層之楊氏模數取中間值，例如，若以靠近半導體元件102側之第1中間層207進行說明，則不僅指靠近接合材料104之楊氏模數E3與半導體元件102之障壁金屬層204之下層(Cu)之楊氏模數之大致中央之數值，而且亦可為接近於障壁金屬層204之下層(Cu)之楊氏模數或接合材料之楊氏模數之數值，亦即，自中值偏向一方之楊氏模數之數值。下述實施例1為前者之例，實施例3為後者之例。
另一方面，如實施形態3、4所記載之發明所示，可使2層之積層體介於半導體元件與電極之間而實現應力緩和。
圖3表示積層體為2層之情形時之實施形態3所記載之發明之接合構造體。
積層體之中間層係形成於接合材料104之上述半導體元 件102之側。於該積層體209b中於接合材料104之上述Cu電極103之側未形成中間層。
經由接合材料104與第1中間層207之2層之積層體209b接合Cu電極103與半導體元件102之表面之Cu，並將第1中間層207之楊氏模數設定於接合材料104之楊氏模數與半導體元件102之障壁金屬層204之下層(Cu)之楊氏模數之間，藉此以使接合材料104與第1中間層207之2層之積層體209b之各楊氏模數朝向接合材料104、第1中間層207、半導體元件102之障壁金屬層之下層(Cu)依序增大之方式構成。
因此，若基於與在接合材料104之半導體元件側形成有中間層之2層之積層體相關之實施形態3所記載之發明對該方面進行說明，則對2層之積層體209b進行更詳細之說明。
於將半導體元件102之側之第1中間層207之楊氏模數設為E21，將半導體元件102之表面之Cu之楊氏模數設為E1，且將接合材料104之楊氏模數設為E3之情形時，以滿足以下條件(p)之方式，於半導體元件102與Cu電極103之間構成2層之積層體209b E3<E21<E1………(p)。
其次，圖4表示積層體為另一2層構造之情形時之實施形態4所記載之發明之接合構造體。
於該圖4中，積層體之中間層係形成於接合材料104之上述Cu電極103側。於該積層體209c中於接合材料104之半導體元件102之側未形成上述中間層。
經由接合材料104與第2中間層206之2層之積層體209c接 合Cu電極103與半導體元件102之表面之Cu，並將第2中間層206之楊氏模數設定於接合材料104之楊氏模數與Cu電極103之楊氏模數之間，藉此以使接合材料104與第2中間層206之2層之積層體209c之各楊氏模數朝向接合材料104、第2中間層206、Cu電極103依序增大之方式構成。
對2層之積層體209c進行更詳細之說明。
於將面向電極之第2中間層206之楊氏模數設為E24之情形時，且於將接合材料104之楊氏模數設為E3，將Cu電極103之楊氏模數設為E4之情形時，以滿足以下條件(q)之方式，於半導體元件102與Cu電極103之間構成2層之積層體209c E3<E24<E4………(q)。
於製作接合構造體106時，如圖3或圖4所示般即便僅於接合材料104之一面形成中間層而設為2層之積層體209b、209c，亦可發揮彈簧效果，但若如圖2C所示般於接合材料104之上、下表面形成中間層而設為3層之積層體209a，則可更良好地發揮彈簧效果。
又，中間層之材質較佳為選自由AuSn化合物、AgSn化合物、CuSn化合物、Au、及Ag所組成之群，更佳為CuSn化合物。
進而，關於中間層之厚度，以Au/Sn之構成為例進行說明。
接合前之Au/Sn之構成於接合後變為AuSn化合物之反應係以下式(a)表示。
Au+4Sn → AuSn4………(a)
此處，若將接合前之Au之厚度設為LAu，將Sn之厚度設為LSn，則於化學計量上兩者之關係如下式(b)所示。
LSn=4×LAu×ρAu×MSn/ρSn×MAu………(b) 於式(b)中，ρ、M、下標分別表示密度、原子量、各元素。
因此，例如，若基於下述實施例1進行敍述，則可知於將Au成膜為0.1 μm之情形時，若將各物性值代入(b)式中，則相當之接合前之Sn之厚度為0.6 μm而較強，故若接合前之Sn之厚度未達0.6 μm，則於接合後，僅生成上式(a)之金屬間化合物，且於接合前之Sn成膜過程中，所有Sn消失。
因此，考慮到於實施例1中電鍍之成膜偏差，而以僅確實地生成金屬間化合物之方式，尋求將Sn之厚度成膜為較0.6 μm相當薄之0.3 μm。
因此，即便於Au之成膜厚度為0.1 μm以外之情形時，只要適當地基於上述設計思想，以於接合後不殘留Sn之單層之方式設定接合前之Sn之厚度即可。
若於接合後殘留有Sn之單層，則有於接合部208中形成Sn之熔點即232℃之相，且於功率半導體100相對於基板101安裝時重新熔融之虞，因此使得於接合後不殘留Sn之單層。
以上為關於Au/Sn之構成之說明，其他關於Ag/Sn、Sn、Au、及Ag之對於各水準之厚度的厚度之思考方法亦只要 仿照上述內容即可。
如上所述，若接合構造體106之製作已完成，則如上述圖1所示，使用接合構造體106製作功率半導體模組100，並利用焊錫材料109將其安裝於基板101上，而製作安裝構造體110(參照圖5)。
安裝時之焊錫材料109通常使用Sn-3重量%Ag-0.5重量%Cu(熔點217℃)，但只要為無鉛之Sn系焊錫，則並不限定於此，例如，亦可使用Sn-0.7重量%Cu(熔點227℃)、Sn-3.5重量%Ag-0.5重量%Bi-6.0重量%In(熔點220℃)等。
-實施例-
以下，對作為實施形態所記載之發明之接合構造體之實施例、將由接合構造體所獲得之功率半導體模組安裝於基板上而成之安裝構造體之製造例、及安裝構造體之良率之評價試驗例進行說明。
《接合構造體之實施例》
於下述實施例1~15中，實施例1~5係如上所述般分別於接合材料104之上、下表面形成有第1、第2中間層207、206之例，實施例6~10係僅於接合材料104中之上述半導體元件102之側形成有第1中間層207之例，實施例11~15係僅於接合材料104中之上述Cu電極103之側形成有第2中間層206之例。
又，依據先前技術，將未設置電極表面處理層202及Bi基礎層205，且未形成藉由加熱、擴散所形成之第1、第2中間層207、206之情形設為比較例1。
再者，於圖6中，關於實施例1~15，彙總了接合前之電極表面處理層202、Bi基礎層205之構成與厚度、及接合後之第2中間層206、第1中間層207之組成與厚度。
(1)實施例1
如圖6所示，將Au 0.1 μm/Sn 0.3 μm之2層形成為積層狀而作為電極表面處理層202。於此情形時，距Bi層203較遠之側為Au，靠近Bi層203之側為Sn。
同樣地，將Au 0.1 μm/Sn 0.3 μm之2層形成為積層狀而作為Bi基礎層205。於此情形時，距Bi層203較遠之側為Au，靠近Bi層203之側為Sn。
繼而，加熱至320℃，藉由電極表面處理層202中之擴散反應而生成金屬間化合物，從而形成包含2 μm之AuSn化合物之第2中間層206。同樣地，藉由Bi基礎層205中之擴散反應而生成金屬間化合物，從而形成包含2 μm之AuSn化合物之第1中間層207。
對於上述AuSn化合物，藉由能量分散型X射線光譜法(Energy Dispersive X-ray Spectroscopy)，確認其為AuSn4(Au與Sn之原子量比為1比4)。
(2)實施例2
如圖6所示，將Ag 0.5 μm/Sn 0.1 μm之2層形成為積層狀而作為電極表面處理層202，並將Ag 0.5 μm/Sn 0.1 μm之2層形成為積層狀而作為Bi基礎層205。於此情形時，距Bi層203較遠之側為Ag，靠近Bi層203之側為Sn。
繼而，加熱至320℃，藉由電極表面處理層202之擴散反 應，而形成包含2 μm之AgSn化合物之第2中間層206。同樣地，藉由Bi基礎層205之擴散反應，而形成包含2 μm之AgSn化合物之第1中間層207。
對於上述AgSn化合物，藉由能量分散型X射線光譜法，確認其為Ag3Sn(Ag與Sn之原子量比為3比1)。
(3)實施例3
如圖6所示，形成0.5 μm之Sn之單層作為電極表面處理層202，且形成0.5 μm之Sn之單層作為Bi基礎層205。
繼而，加熱至320℃，藉由電極表面處理層202與Cu電極103之Cu之擴散反應，而形成包含2 μm之CuSn化合物之第2中間層206。同樣地，藉由Bi基礎層205與作為障壁金屬層204之最下層之Cu之擴散反應，而形成包含2 μm之CuSn化合物之第1中間層207。
對於上述CuSn化合物，藉由能量分散型X射線光譜法，確認其為Cu6Sn5(Cu與Sn之原子量比為6比5)。
(4)實施例4
如圖6所示，形成2 μm之Au之單層作為電極表面處理層202，且形成2 μm之Au之單層作為Bi基礎層205。
繼而，加熱至320℃，藉由電極表面處理層202之擴散，而形成包含0.5 μm之Au之第2中間層206，同樣地，藉由Bi基礎層205之擴散，而形成包含0.5 μm之Au之第1中間層207。另外，Au未與電極、或障壁金屬層204之最下層之Cu形成金屬間化合物。
(5)實施例5
如圖6所示，形成2 μm之Ag之單層作為電極表面處理層202，且形成2 μm之Ag之單層作為Bi基礎層205。
繼而，加熱至320℃，藉由電極表面處理層202之擴散，而形成包含0.5 μm之Ag之第2中間層206，同樣地，藉由Bi基礎層205之擴散，而形成包含0.5 μm之Ag之第1中間層207。另外，Ag未與電極、或障壁金屬層204之最下層之Cu形成金屬間化合物。
(6)實施例6~10
於以圖6所示之構成與厚度形成2層或單層之Bi基礎層205後，加熱至320℃，而形成圖6所示之組成與厚度之第1中間層207。未形成第2中間層206。
(7)實施例11~15
於以圖6所示之構成與厚度形成2層或單層之電極表面處理層202後，加熱至320℃，而形成圖6所示之組成與厚度之第2中間層206。未形成第1中間層207。
《安裝構造體之製造例》
如圖5所示，使用藉由上述實施例而完成之接合構造體106，且使用引線107進行引線接合(wire bonding)(亦可為條帶接合(ribbon bonding))，並實施密封而形成功率半導體模組100，其後利用焊錫材料將該功率半導體模組100安裝於基板101上，從而形成安裝構造體110。
對於上述焊錫材料109，如上所述，使用通常之焊錫材料即Sn-3重量%Ag-0.5重量%Cu(熔點217℃)。
因此，對上述安裝構造體110之製品良率進行評價。
《安裝構造體之良率評價試驗例》
將低溫側固定為-65℃，將高溫側設定為150℃、175℃、200℃之3個階段，於重複進行300個循環之低溫-高溫間之溫度循環試驗(1個循環為30分鐘/30分鐘)後，以超音波影像觀察製品，並以目測判定接合構造體之接合材料之龜裂、剝離之有無，算出相對於接合部之表面積龜裂、剝離未達20%之製品良率(N數=20)，並以下述基準評價其優劣。
○：良率為80%以上(良品)。
×：良率未達80%(不良品)。
《關於良率試驗之評價》
圖7表示良率試驗之結果。
首先，於實施例1~15中，於溫度循環試驗條件之高溫側為150℃、175℃、200℃之任一者之情形時，良率均為80%以上，判定為良品(○)。
相對於此，於比較例1中，於溫度循環試驗條件之高溫側為150℃之情形時，良率為95%，但若高溫側升溫至175℃、200℃，則良率降至65%、50%，而判定為不良品(×)。
一般而言，於溫度循環試驗中，若高溫側與低溫側之溫度差△T較大，則基於半導體元件102之熱膨脹係數(α3 ppm/K)、與作為Cu電極103之材料之Cu之線膨脹係數(α18 ppm/K)之差的熱應力會變大，而對接合構造體中之接合部208施加該應力。
若觀察比較例1(先前技術)，則可知高溫側雖然具有對於150℃之耐熱應力，但不具備對於175℃、200℃之耐熱應力。
相對於此，於本發明之實施例1~15中，任一者均判定為良品。
因此，將實施例1作為代表例，考察實施例相對於比較例1之優勢之理由。
首先，若觀察接合部之各構成之楊氏模數，則由於比較例1之構成為Cu電極103、經Ag層擴散之Bi層203(接合材料)、及作為障壁金屬層204之最下層之Cu層之3層構造，故成為Cu(110×109 N/m2)/Bi-3.5重量%Ag(32×109 N/m2)/Cu(110×109 N/m2)。
相對於此，於實施例1之構成中，由於在經Ag層擴散之Bi層203(接合材料)之上、下表面積層第1、第2中間層207、206，故成為Cu(110×109 N/m2)/AuSn4(55.6×109 N/m2)/Bi-3.5重量%Ag(32×109 N/m2)/AuSn4(55.6×109 N/m2)/Cu(110×109 N/m2)。
如下式(c)所示，楊氏模數為材料富有彈性地做出行為之情形時之應力與應變之比，E=σ/ε………(c)式(c)中，E表示楊氏模數，σ表示應力，ε表示應變。
由於楊氏模數與應變量成反比，故於施加有一定應力之情形時，楊氏模數較小者可產生應變之量較大。
因此，認為比較例1與實施例1之差異在於，是否有中間 層AuSn化合物(AuSn4)介於Cu層與Bi-3.5重量%Ag層之間，於實施例1中，由於具有中間層，故使楊氏模數自Bi-3.5重量%Ag之接合材料朝向Cu傾斜地增大，從而發揮彈簧效果，且顯現應力緩和功能。
然而，於比較例1中，由於不存在此種楊氏模數之傾斜之增大，且接合材料之楊氏模數與電極或障壁金屬層之楊氏模數之差異較大，故可推斷不會發揮所謂之彈簧效果，此係實施例1相對於比較例1之優勢，亦即，由高溫側之溫度條件導致產生良率之差之理由。
對於其他實施例2~15之各中間層亦相同， 試樣2、7、12之中間層(Ag3Sn)：楊氏模數=74.5×109 N/m2
試樣3、8、13之中間層(Cu6Sn5)：楊氏模數=93.5×109 N/m2
試樣4、9、14之中間層(Au)：楊氏模數=80×109 N/m2
試樣5、10、15之中間層(Ag)：楊氏模數=76×109 N/m2
可推斷藉由在Cu與Bi-3.5重量%Ag之間插入上述各種中間層，而發揮彈簧效果，且顯現應力緩和功能。
因此，以下詳細地研究實施例1~15之試驗結果。
若將於接合材料104之兩面存在第1、第2中間層207、206之實施例1~5，與僅存在第1中間層207之實施例6~10、及僅存在第2中間層206之實施例11~15加以對比，則可知 圖7之良率中存在10~15%之差，於兩面存在中間層之實施例1~5之良率具有優勢。
因此，可以說即便中間層僅存在於接合材料104之上述半導體元件102或上述Cu電極103側，亦有效地顯現應力緩和功能，但為了進一步促進應力緩和功能，較理想的是於接合材料104之上述半導體元件102側與上述Cu電極103之側之兩者設置中間層。
又，於實施例4~5、實施例9~10、及實施例14~15中，接合後之中間層之厚度與接合前之Au、Ag層之厚度相比，大幅度地減少為0.5 μm。其原因在於，擴散至靠近接合前之電極表面處理層、Bi基礎層之部分之Bi-3.5重量%Ag中，但即便為此種構成，於上述良率試驗中證實亦藉由發揮所需之彈簧效果而有效地顯現應力緩和功能。
又，本發明之特徵在於，使楊氏模數自積層體朝向半導體元件或電極傾斜地增大，例如，實施例1之第1中間層207(AuSn4)之楊氏模數為55.6×109 N/m2，為接近於作為障壁金屬層204之最下層之Cu層之楊氏模數(110×109 N/m2)、與接合材料(Bi-3.5重量%Ag)之楊氏模數(32×109 N/m2)之大致中央之數值，但於實施例3中，第1中間層207(Cu6Sn5)之楊氏模數為93.5×109 N/m2，為接近於障壁金屬層204之Cu層之楊氏模數(110×109 N/m2)之數值。
因此，即便第1、第2中間層207、206之楊氏模數為接近於半導體元件之表面、亦即障壁金屬層之下層之Cu或電極Cu之楊氏模數之值，參照上述試驗結果亦發揮彈簧效果， 故可以說只要第1、第2中間層207、206之楊氏模數處於半導體元件之表面之Cu之楊氏模數、與Cu電極之楊氏模數之間，則亦可不設計為中央附近之數值。
產業上之可利用性
包含本發明之接合構造體之安裝構造體係經由如楊氏模數自接合材料朝向被接合材料(半導體元件、Cu電極)傾斜地增大之積層構造而接合半導體元件與Cu電極，藉此確保對於功率半導體模組之使用時之溫度循環中產生之熱應力之應力緩和性，從而可應用於功率半導體模組、小電力電晶體等半導體封裝之用途。
100‧‧‧功率半導體模組
101‧‧‧基板
102‧‧‧半導體元件
103‧‧‧Cu電極
104‧‧‧接合材料
105‧‧‧密封樹脂
106‧‧‧接合構造體
107‧‧‧引線
109‧‧‧焊錫材料
110‧‧‧安裝構造體
201‧‧‧Ag層
202‧‧‧電極表面處理層
203‧‧‧Bi層
204‧‧‧障壁金屬層
205‧‧‧Bi基礎層
206‧‧‧第2中間層
207‧‧‧第1中間層
208‧‧‧接合部
209a‧‧‧積層體
209b‧‧‧積層體
209c‧‧‧積層體
401‧‧‧功率半導體模組
402‧‧‧功率半導體元件
403‧‧‧電極
404‧‧‧接合部
405‧‧‧樹脂
406‧‧‧焊錫材料
407‧‧‧基板
408‧‧‧引線
圖1係將接合構造體作為構成要素之安裝構造體之剖面圖。
圖2A係本發明之實施形態2中之接合構造體之製造步驟圖。
圖2B係本發明之實施形態2中之接合構造體之製造步驟圖。
圖2C係本發明之實施形態2中之接合構造體之製造步驟圖。
圖3係本發明之實施形態3中之接合構造體之構成圖。
圖4係本發明之實施形態4中之接合構造體之構成圖。
圖5係安裝構造體之放大剖面圖。
圖6係對於本發明之實施形態中之實施例1~15，彙總有接合前之電極表面處理層及Bi基礎層之構成與厚度、以及 接合後之第2中間層、第1中間層之組成與厚度之圖表。
圖7係表示接合構造體之良率試驗結果之圖表。
圖8係表示先前技術之安裝構造體之放大剖面圖。
102‧‧‧半導體元件
103‧‧‧Cu電極
104‧‧‧接合材料
201‧‧‧Ag層
202‧‧‧電極表面處理層
204‧‧‧障壁金屬層
206‧‧‧第2中間層
207‧‧‧第1中間層
208‧‧‧接合部
209a‧‧‧積層體

Claims (6)

  1. 一種接合構造體，其係藉由以Bi為主成分之接合材料將半導體元件接合於Cu電極而成者，其特徵在於：由上述接合材料與形成於該接合材料之表面之中間層構成積層體，經由該積層體而接合半導體元件之表面之Cu與上述Cu電極；於將上述半導體元件之表面之Cu之楊氏模數設為E1，將上述中間層之楊氏模數設為E2，將上述接合材料之楊氏模數設為E3，且將上述Cu電極之楊氏模數設為E4之情形時，以各楊氏模數E1~E4滿足以下條件(p1)、(q1)之兩者或其中一者之方式，相對於上述半導體元件及上述Cu電極構成上述積層體E3<E2<E1………(p1) E3<E2<E4………(q1)。
  2. 如請求項1之接合構造體，其中上述積層體為包含上述接合材料、及形成於該接合材料之上、下兩面之2個中間層的3層之積層體，且若將上述半導體元件之側之第1中間層之楊氏模數設為E21，將上述Cu電極之側之第2中間層之楊氏模數設為E24，則以各楊氏模數E1、E21、E24、E3、E4滿足以下條件(p2)及(q2)之方式，相對於上述半導體元件及上述Cu電極構成上述3層之積層體E3<E21<E1………(p2) E3<E24<E4………(q2)。
  3. 如請求項1之接合構造體，其中上述積層體為包含上述接合材料、及形成於該接合材料之上述半導體元件之側之中間層的2層，且於將上述中間層之楊氏模數設為E21之情形時，以各楊氏模數E1、E21、E3滿足以下條件(p2)之方式，相對於上述半導體元件及上述Cu電極構成上述2層之積層體E3<E21<E1………(p2)。
  4. 如請求項1之接合構造體，其中上述積層體為包含上述接合材料、及形成於該接合材料之上述Cu電極之側之中間層的2層之積層體，且於將上述中間層之楊氏模數設為E24之情形時，以各楊氏模數E24、E3、E4滿足以下條件(q2)之方式，相對於上述半導體元件及上述Cu電極構成上述2層之積層體E3<E24<E4………(q2)。
  5. 如請求項1至4中任一項之接合構造體，其中上述中間層係選自由AuSn化合物、AgSn化合物、CuSn化合物、Au、及Ag所組成之群中之金屬的至少一種。
  6. 如請求項1至5中任一項之接合構造體，其中上述中間層為CuSn化合物。
TW101119420A 2011-06-03 2012-05-30 接合構造體 TW201308543A (zh)

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