JP5723225B2 - 接合構造体 - Google Patents
接合構造体 Download PDFInfo
- Publication number
- JP5723225B2 JP5723225B2 JP2011125656A JP2011125656A JP5723225B2 JP 5723225 B2 JP5723225 B2 JP 5723225B2 JP 2011125656 A JP2011125656 A JP 2011125656A JP 2011125656 A JP2011125656 A JP 2011125656A JP 5723225 B2 JP5723225 B2 JP 5723225B2
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- Prior art keywords
- layer
- young
- modulus
- intermediate layer
- electrode
- Prior art date
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/264—Bi as the principal constituent
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
- B23K35/007—Interlayers, transition pieces for metallurgical bonding of workpieces at least one of the workpieces being of copper or another noble metal
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
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Description
このため、一般的なはんだ材であるSn−Pb共晶はんだについては、代替材料が開発、実用化されている。
この代替はんだ材料の候補には、Au系、Zn系、Sn系、Bi系のものが挙げられる。 このうち、Au系のはんだ材料に関しては、例えば、融点が280℃のAu−20重量%Snなどが一部実用化されているが、主成分がAuであるため、材料物性が硬いうえ、材料コストが高く、小型部品に使用が限定されるなどの理由から汎用性がない。
Zn系のはんだ材料は腐食性が強いうえ、弾性率が高すぎるため、半導体部品の内部接合への適用においては機械特性の向上が課題である。
Sn系のはんだ材料は優れた機械特性を有するが、融点が250℃未満と低く耐熱性に乏しい。そこで、Sn系の耐熱性向上を目的として、例えばSnCu化合物を形成することで、金属間化合物化により融点を上げた接合材料が検討されているが、金属間化合物化の際の凝固収縮により接合時に空隙が発生するため、機械特性、放熱特性の改善が課題である。
例えば、特許文献1はこのBi系のはんだ材料を接合材料に用いた例である。
図6は、当該特許文献1に記載された従来の接合構造体の断面図であり、パワー半導体モジュール401は、パワー半導体素子402と電極403との間に接合部404を有し、この接合部404には、Bi−Ag系はんだ材料が用いられており、15〜60重量%のAgを含ませている。
これは、パワー半導体素子の熱膨張係数(α≒3ppm/K)、Cu(電極)の線膨張係数(α≒18ppm/K)の差に基づく熱応力に対して、Bi−Ag系はんだ材料が応力緩和しきれないため、接合部にクラック、剥離などが生じることに因ると考えられる。
従って、前記特許文献1のBi−Ag系はんだ材料による接合構造体では、パワー半導体素子の動作温度が150℃以上である場合、当該高温域に対する応力緩和性の向上が課題となる。
特許文献2には、半導体素子上に被覆形成される保護樹脂を、半導体素子の中間接合層とはんだ接合層の間の外周面域にも被覆形成させることにより、半導体素子内部の耐クラック性を向上して、半導体素子とはんだ材料の界面や、はんだ材料と電極の界面に加わる熱的応力を軽減することが示される(請求項1、段落13〜段落15、段落19、段落23参照)。
上記接合材料と、上記接合材料の上記半導体素子に臨む面に形成した第1中間層とで積層体を構成し、
上記半導体素子の表面のCuのヤング率をE1、上記第1中間層のヤング率をE21、上記接合材料のヤング率をE3とした場合に、
各ヤング率E1、E21、E3が、次の条件(p)
E3<E21<E1 …(p)
を満たすとともに、
上記第1中間層が、AuSn化合物、AgSn化合物、CuSn化合物から選ばれた一種のみの単層で構成されることを特徴とする接合構造体である。
上記第2中間層のヤング率をE24、上記Cu電極のヤング率をE4とした場合に、
上記接合材料、上記第2中間層及び上記Cu電極の各ヤング率が、次の条件(q)
E3<E24<E4 …(q)
を満たすとともに、
上記第2中間層が、AuSn化合物、AgSn化合物、CuSn化合物から選ばれた一種のみの単層で構成されることを特徴とする接合構造体である。
即ち、本発明では、接合材料から被接合材料(半導体素子、Cu電極)に向けて、ヤング率が傾斜的に増大するような積層構造を介して半導体素子とCu電極を接合することにより、パワー半導体モジュールの使用時における温度サイクルで生じる熱応力に対して、いわゆる〈バネ効果〉を働かせて優れた応力緩和機能を発現させるため、半導体素子と電極とを品質良く接合し、もって接合信頼性を向上できる。
これを分かり易く説明すると、接合構造体においては、上記半導体素子の接合材料に臨む表面のCuのヤング率をE1、第1中間層のヤング率をE21、接合材料のヤング率をE3とした場合に、
各ヤング率E1、E21、E3が、次の条件(p)
E3<E21<E1 …(p)
を満たすように、上記積層体を半導体素子に対して構成する。
本発明1では、上記第1中間層は、AuSn化合物、AgSn化合物、CuSn化合物から選ばれた一種のみからなる単層で構成される。
これを分かり易く説明すると、接合構造体においては、上記半導体素子の表面のCuのヤング率をE1、第1中間層のヤング率をE21、接合材料のヤング率をE3、第2中間層のヤング率をE24、Cu電極のヤング率をE4とした場合に、
各ヤング率E1、E21、E3、E24、E4が、次の条件(p)、(q)
E3<E21<E1 …(p)
E3<E24<E4 …(q)
の両方を満たすように、上記積層体を半導体素子とCu電極に対して構成する。
本発明2において、上記第2中間層はAuSn化合物、AgSn化合物、CuSn化合物から選ばれた一種のみからなる単層で構成され、同じく上記第1中間層もAuSn化合物、AgSn化合物、CuSn化合物から選ばれた一種のみの単層で構成される。
尚、本発明では、電極、或いは後述するバリアメタル層の最下層の材質としての銅は、銅並びに銅合金を包含する概念である。
図1は、本発明の接合構造体を構成要素とする実装構造体の断面図である。
先ず、接合材料104により半導体素子102と電極103を接合して接合構造体106を形成し、次いで、当該接合構造体106を封止樹脂105で封止してパワー半導体モジュール100を形成し、最後に、当該パワー半導体モジュール100をはんだ材料109を用いて基板101に実装して、実装構造体110を形成している。
図2は、この接合構造体の製造工程図であり、接合材料の上・下面に中間層を夫々形成する場合(つまり、3層の積層体を介在させた上記本発明2の場合)を説明する。
先ず、図2(a)は、電極103を供給する工程図である。
電極103の供給に際しては、水素5%を含んだ窒素雰囲気中(室温)に電極103を供給する。
Cu合金で構成された電極103には、表面処理層として、予め電解めっき法によりAg層201、及び電極表面処理層202を成膜させている。
次いで、電極103上にBi層203を具備した半導体素子102を載置する。
半導体素子102を載置するに際しては、水素5%を含んだ窒素雰囲気中で、電極103を320℃に加熱している。
GaNで構成され、厚み0.3mm、4mm×5mmの大きさの半導体素子102には、予め蒸着法により、GaN側からCr0.1μm/Ni1μm/Cu3μmの多層よりなるバリアメタル層204、Bi下地層205を成膜し、また、電気めっき法によりBi下地層205上に厚み10μmのBiよりなるBi層203を成膜している。
また、バリアメタル層204のNiは、半導体素子のデバイスにCu成分が拡散することによるデバイスの機能低下を防ぐため(つまりCuの拡散防止用)に成膜される。
最後に、バリアメタル層204のCuは前記Bi下地層205に接する層である。このCu層を設ける理由については、前記Bi層203のBiとNiは界面に金属間化合物Bi3Niを形成し、この脆い金属化合物層が例えばパワー半導体モジュールの使用時に熱応力により変形する際に亀裂の起点となる恐れがあることから、Biとバリアメタル層のNiとの間にCuを成膜してBiのNiへの拡散を防止するためである。
Cuを選定したのは、Biに対する溶解量が少ない(0.4at%程度)金属であることから、Biの拡散を防ぐバリア効果を発現させるためである。また、Cuの厚みに関しては、1μm以上あればBiの拡散を防ぐことが可能であるが、電気めっき法での成膜厚みのバラつき2μmを考慮し、3μmとしている。
次いで、上記Bi層203は電極103の表面処理層であるAg層201に接するように、半導体素子102を50gf〜150gf程度の荷重で、電極103の上に載置している。
ちなみに、後述する本発明の実施例では60gfの荷重で、半導体素子102を電極103の上に載置している。
図2(c)の工程では、水素5%を含んだ窒素雰囲気中で自然冷却させ、接合材料104が凝固することにより電極103と半導体素子102とを接合させ、接合構造体106を製造する。
前述したように、図2(b)〜(c)のBi層203が溶融して凝固するまでの間、Biには電極103の表面処理層であるAg層201が拡散する。
上記Bi層203のBiはAgと〈Bi−3.5重量%Ag〉の2元共晶を形成するため、Biに対してAgが拡散した後の接合材料104の融点は262℃となる。
電極103の表面処理層としてAg層201を形成する目的は、半導体素子102の下部全面に対する溶融Biの濡れ性を確保するためである。
先ず、中間層A(206)は、320℃の加熱状態で電極表面処理層202中の拡散反応により、或いは電極表面処理層202と電極103のCuとの拡散反応により形成された層である。
同様に、中間層B(207)も、320℃の加熱状態でBi下地層205中の拡散反応により、或いはバリアメタル層204の最下層であるCuとBi下地層205との拡散反応により形成された層である。
これは、上記中間層B(207)のヤング率が接合材料104のヤング率と半導体素子102の表面のヤング率との間にあり(つまり中間の値をとり)、且つ、中間層A(206)のヤング率が接合材料104のヤング率と電極103のヤング率との間にある(つまり中間の値をとる)ことにより達成される。
そこで、この点を3層積層体に関する前記本発明2に基づいて説明すると、前述したように、半導体素子の表面のCuのヤング率をE1、接合材料のヤング率をE3、Cu電極のヤング率をE4とし、半導体素子に臨む側の第1中間層(=中間層B)のヤング率をE21とし、電極に臨む側の第2中間層(=中間層A)のヤング率をE24とすると、
各ヤング率E1、E21、E24、E3、E4が、次の条件(p)及び(q)
E3<E21<E1 …(p)
E3<E24<E4 …(q)
を満たすように構成される。
この場合、中間層のヤング率が中間の値をとるとは、例えば、半導体素子側に近い第1中間層のヤング率E21について説明すると、接合材料のヤング率E3と半導体素子のバリアメタル層の下層(Cu)のヤング率E1とのほぼ中央寄りの数値だけを意味するのではなく、バリアメタル層の下層(Cu)のヤング率E1、又は接合材料のヤング率E3に近い数値(つまり、中央値から一方のヤング率の方に偏った数値)であっても差し支えない。後述の実施例1は前者の例、実施例3は後者の例である。
本発明1では、Cu電極と半導体素子の表面のCuを、接合材料104と中間層B(207)との2層積層体を介して接合し、中間層B(207)のヤング率を接合材料104のヤング率と半導体素子102のバリアメタル層の下層(Cu)のヤング率との間に設定することにより、上記接合材料104と中間層B(207)の2層積層体の各ヤング率が、接合材料104、中間層B(207)、半導体素子102のバリアメタル層の下層(Cu)に向けて順次増大するように構成させる。
この2層積層体に関する本発明1では、前述したように、半導体素子の表面のCuのヤング率はE1、接合材料のヤング率をE3とし、半導体素子に臨む第1中間層(=中間層B)のヤング率をE21とした場合に、
各ヤング率E1、E21、E3が、次の条件(p)
E3<E21<E1 …(p)
を満たすように構成される。
また、単層からなる中間層の材質は、AuSn化合物、AgSn化合物、CuSn化合物よりなる群の一種から選定され、好ましくはCuSn化合物である。
接合前のAu/Snの構成が接合後にAuSn化合物になる反応は、下式(a)で表される。
Au+4Sn→AuSn4 …(a)
ここで、接合前のAuの厚みをLAu、Snの厚みをLSnとすると、化学量論的に両者の関係は下式(b)のようになる。
LSn=4×LAu×ρAu×MSn/ρSn×MAu …(b)
(式(b)中、ρは密度、Mは原子量、添え字は各元素を夫々表す。)
そこで、例えば、後述の実施例1に基づいて述べると、Auを0.1μm成膜する場合、上記(b)式に各物性値を代入すると、相当する接合前のSnの厚みは0.6μm強となるため、接合前のSnの厚みが0.6μm未満であれば、接合後には、上式(a)の金属間化合物のみが生成し、接合前のSn成膜のうち、全てのSnが消失することがわかる。
そこで、実施例1ではめっきの成膜ばらつきを考慮して、金属間化合物のみが確実に生成するように、Snの厚みは0.6μmよりかなり薄い0.3μmの成膜を狙った。
従って、Auの成膜厚みは0.1μm以外の場合でも、適宜、上記設計思想に基づき、接合後にSnの単層を残さないように、接合前のSnの厚みを設定すればよい。
接合後にSnの単層が残ると、接合部208中でSnの融点である232℃の相が形成されてしまい、パワー半導体100の基板101に対する実装時に再溶融する恐れがあるため、接合後にSnの単層を残さないようにしている。
以上が、Au/Snの構成に関する説明であるが、他のAg/Sn、Sn、Au、Agの各水準に対する厚みに関する厚みの考え方も、上記に倣えばよい。
実装の際のはんだ材料109は、一般的には、Sn−3重量%Ag−0.5重量%Cu(融点217℃)を用いるが、鉛フリーのSn系はんだであれば、これに限らず、例えば、Sn−0.7重量%Cu(融点227℃)、Sn−3.5重量%Ag−0.5重量%Bi−6.0重量%In(融点220℃)等を用いても良い。
下記の実施例1〜6のうち、実施例1〜3は前述した通り、接合材料の上・下面に中間層A・Bを夫々形成した例、実施例4〜6は接合材料のうちの半導体素子に臨む面に中間層Bのみを形成した例である。
また、従来技術に準拠して、電極表面処理層202及びBi下地層205を設けず、加熱・拡散による中間層A、Bを形成しない場合を比較例1とした。
尚、図4には、上記実施例1〜6について、接合前の電極表面処理層202、Bi下地層205の構成と厚み、接合後の中間層A及び/又は中間層Bの組成と厚みをまとめた。
電極表面処理層202としてAu0.1μm/Sn0.3μmの2層を積層状に形成した。この場合、Bi層203から遠い側がAuであり、Bi層203に近い側がSnである。
同様に、Bi下地層205としてAu0.1μm/Sn0.3μmの2層を積層状に形成した。この場合、Bi層203から遠い側がAuであり、Bi層203に近い側がSnである。
次いで、320℃に加熱して、電極表面処理層202中の拡散反応により金属間化合物を生成させて、AuSn化合物2μmよりなる中間層A(206)を形成した。同様に、Bi下地層205中の拡散反応により金属間化合物を生成させて、AuSn化合物2μmよりなる中間層B(207)を形成した。
上記AuSn化合物については、EDX(エネルギー分散型X線分光器)により、AuSn4(AuとSnが原子量比で1対4)であることを確認した。
図4に示すように、電極表面処理層202としてAg0.5μm/Sn0.1μmの2層を積層状に形成し、Bi下地層205としてAg0.5μm/Sn0.1μmの2層を積層状に形成した。この場合、Bi層203から遠い側がAgであり、Bi層203に近い側がSnである。
次いで、320℃に加熱して、電極表面処理層202の拡散反応により、AgSn化合物2μmよりなる中間層A(206)を形成した。同様に、Bi下地層205の拡散反応により、AgSn化合物2μmよりなる中間層B(207)を形成した。
上記AgSn化合物については、EDX(エネルギー分散型X線分光器)により、Ag3Sn(AgとSnが原子量比で3対1)であることを確認した。
図4に示すように、電極表面処理層202としてSn0.5μmの単層を形成し、Bi下地層205としてSn0.5μmの単層を形成した。
次いで、320℃に加熱して、電極表面処理層202と電極103のCuとの拡散反応により、CuSn化合物2μmよりなる中間層A(206)を形成した。同様に、Bi下地層205とバリアメタル層204の最下層であるCuとの拡散反応により、CuSn化合物2μmよりなる中間層B(207)を形成した。
上記CuSn化合物については、EDX(エネルギー分散型X線分光器)により、Cu6Sn5(CuとSnが原子量比で6対5)であることを確認した。
図4に示す構成と厚みで2層又は単層のBi下地層205を形成した後、320℃に加熱して、図4に示す組成と厚みの中間層B(207)を形成した。中間層A(206)は形成しなかった。
図3に示すように、上記実施例により完成させた接合構造体を使用して、ワイヤ107を用いてワイヤボンディング(リボンボンディングでも良い)を行い、封止を実施してパワー半導体モジュール100を形成した後、このパワー半導体モジュール100をはんだ材料で基板101に実装して、実装構造体110を形成した。
上記はんだ材料109には、前述した通り、一般的なはんだ材料であるSn−3重量%Ag−0.5重量%Cu(融点217℃)を用いた。
《実装構造体による歩留まり評価試験例》
低温側を−65℃に固定し、高温側を150℃、175℃、200℃の3段階に設定して、低温−高温間の温度サイクル試験(1サイクル30分/30分)を300サイクル繰り返した後、製品を超音波映像で観察して、接合構造体の接合材料のクラック、剥離の有無を目視で判定し、接合部の表面積に対してクラック、剥離が20%未満に収まる製品歩留まり(N数=20)を算出し、下記の基準でその優劣を評価した。
○:歩留まりが80%以上(良品)であった。
×:歩留まりが80%未満(不良品)であった。
図5は歩留まり試験の結果を表す。
先ず、実施例1〜6では、温度サイクル試験条件の高温側が150℃、175℃、200℃のいずれの場合も、歩留まりが80%以上であり、良品(○)の判定であった。
これに対して、比較例1では、温度サイクル試験条件の高温側が150℃の場合には、歩留まりは95%であったが、高温側が175℃、200に昇温すると、歩留まりは65%、50%に低下して、不良品(×)の判定となった。
比較例1(従来技術)を見ると、高温側が150℃に対する耐熱応力は有するが、175℃、200℃に対する耐熱応力は具備しないことがわかる。
そこで、実施例1を代表例として、比較例1に対する実施例の優位性の理由を考察する。
先ず、接合部の各構成のヤング率を見ると、比較例1の構成は、電極103と、Ag層が拡散したBi層203(接合材料)と、バリアメタル層204の最下層であるCu層との3層構造なので、Cu(110×109N/m2)/Bi−3.5重量%Ag(32×109N/m2)/Cu(110×109N/m2)となる。
これに対して、実施例1の構成では、Ag層が拡散したBi層203(接合材料)の上・下面に中間層A・Bが積層するので、Cu(110×109N/m2)/AuSn4(55.6×109N/m2))/Bi−3.5重量%Ag(32×109N/m2)/AuSn4(55.6×109N/m2))/Cu(110×109N/m2)となっている。
E=σ/ε …(c)
(式(c)中、Eはヤング率、σは応力、εは歪みを表す)
ヤング率とひずみ量は反比例するため、一定の応力が加わった場合、ヤング率が小さい方が、ひずむことができる量が大きいことになる。
従って、比較例1と実施例1の違いは、〈Cu〉層と〈Bi−3.5重量%Ag〉層の間に中間層のAuSn化合物(AuSn4)が介在するか否かということになるが、実施例1では、Bi−3.5重量%Agの接合材料からCuに向けて、中間層があることで傾斜的にヤング率が増大することになり、〈バネ効果〉が働き応力緩和機能が発現したものと考えられる。
しかしながら、比較例1では、このような傾斜的なヤング率の増大はなく、接合材料のヤング率と電極又はバリアメタル層のそれとの差異は大きいため、いわゆる〈バネ効果〉は働かず、これが比較例1に対する実施例1の優位性、つまり、高温側の温度条件により歩留まりの差が生じた理由であると推定できる。
試料2、5の中間層(Ag3Sn) :ヤング率=74.5×109N/m2
試料3、6の中間層(Cu6Sn5):ヤング率=93.5×109N/m2
CuとBi−3.5重量%Agの間に上記各種の中間層が介在することにより、〈バネ効果〉が働き、応力緩和機能が発現したものと推定できる。
接合材料の両面に中間層A、Bが存在する実施例1〜3と、中間層Bのみの実施例4〜6とを対比すると、図5の歩留まりには10〜15%の差があり、中間層が両方存在する実施例1〜3の方が歩留まりに優位性があることが分かる。
従って、中間層は半導体素子側又は電極側のみにあっても応力緩和機能は有効に発現するが、応力緩和機能をより促進するためには半導体素子側と電極側の両方に中間層を設けることが望ましいといえる。
従って、中間層A、Bのヤング率は半導体素子の表面(つまり、バリアメタル層の下層のCu)又は電極Cuのそれに近い値でも、上記試験結果に照らしてバネ効果が働くので、中間層A、Bのヤング率は半導体素子の表面のCuのそれと、Cu電極のそれとの間にあれば、中央付近の数値に設計しなくても差し支えないといえる。
Claims (2)
- Cu電極、Biを主成分とする接合材料を含む積層体、 接合材料に臨む表面にCu層を設けた半導体素子の順に接合した接合構造体において、
上記接合材料と、上記接合材料の上記半導体素子に臨む面に形成した第1中間層とで積層体を構成し、
上記半導体素子の表面のCuのヤング率をE1、上記第1中間層のヤング率をE21、上記接合材料のヤング率をE3とした場合に、
各ヤング率E1、E21、E3が、次の条件(p)
E3<E21<E1 …(p)
を満たすとともに、
上記第1中間層が、AuSn化合物、AgSn化合物、CuSn化合物から選ばれた一種のみの単層で構成されることを特徴とする接合構造体。 - 上記接合材料のCu電極に臨む面に形成した第2中間層を付加し、
上記第2中間層のヤング率をE24、上記Cu電極のヤング率をE4とした場合に、
上記接合材料、上記第2中間層及び上記Cu電極の各ヤング率が、次の条件(q)
E3<E24<E4 …(q)
を満たすとともに、
上記第2中間層が、AuSn化合物、AgSn化合物、CuSn化合物から選ばれた一種のみの単層で構成されることを特徴とする請求項1に記載の接合構造体。
Priority Applications (6)
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JP2011125656A JP5723225B2 (ja) | 2011-06-03 | 2011-06-03 | 接合構造体 |
EP12793525.2A EP2717303A4 (en) | 2011-06-03 | 2012-05-22 | RELATED STRUCTURE |
CN201280025481.0A CN103563062A (zh) | 2011-06-03 | 2012-05-22 | 接合结构体 |
PCT/JP2012/003318 WO2012164865A1 (ja) | 2011-06-03 | 2012-05-22 | 接合構造体 |
US14/123,657 US20140103531A1 (en) | 2011-06-03 | 2012-05-22 | Bonded structure |
TW101119420A TW201308543A (zh) | 2011-06-03 | 2012-05-30 | 接合構造體 |
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JP2011125656A JP5723225B2 (ja) | 2011-06-03 | 2011-06-03 | 接合構造体 |
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US (1) | US20140103531A1 (ja) |
EP (1) | EP2717303A4 (ja) |
JP (1) | JP5723225B2 (ja) |
CN (1) | CN103563062A (ja) |
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US10043775B2 (en) | 2014-02-10 | 2018-08-07 | Mitsubishi Electric Corporation | Bonding material, bonding method and semiconductor device for electric power |
JP6020496B2 (ja) | 2014-03-20 | 2016-11-02 | 株式会社豊田中央研究所 | 接合構造体およびその製造方法 |
WO2022172565A1 (ja) * | 2021-02-09 | 2022-08-18 | アルプスアルパイン株式会社 | 電流センサ |
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US6815342B1 (en) * | 2001-11-27 | 2004-11-09 | Lsi Logic Corporation | Low resistance metal interconnect lines and a process for fabricating them |
JP4479577B2 (ja) | 2005-04-28 | 2010-06-09 | 株式会社日立製作所 | 半導体装置 |
JP5224430B2 (ja) * | 2006-03-17 | 2013-07-03 | 株式会社豊田中央研究所 | パワー半導体モジュール |
JP2009147111A (ja) * | 2007-12-14 | 2009-07-02 | Fuji Electric Device Technology Co Ltd | 接合材、その製造方法および半導体装置 |
JP2009269075A (ja) * | 2008-05-09 | 2009-11-19 | Sumitomo Metal Mining Co Ltd | 応力緩和層を有する積層はんだ材の製造方法および製造装置 |
WO2009157130A1 (ja) * | 2008-06-23 | 2009-12-30 | パナソニック株式会社 | 接合構造および電子部品 |
JP2010103206A (ja) * | 2008-10-22 | 2010-05-06 | Panasonic Corp | 半導体装置及びその製造方法 |
US20100101639A1 (en) * | 2008-10-24 | 2010-04-29 | Epistar Corporation | Optoelectronic device having a multi-layer solder and manufacturing method thereof |
CN102047398B (zh) * | 2009-04-30 | 2014-04-02 | 松下电器产业株式会社 | 接合结构体 |
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JPWO2011049128A1 (ja) * | 2009-10-20 | 2013-03-14 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
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EP2717303A1 (en) | 2014-04-09 |
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US20140103531A1 (en) | 2014-04-17 |
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WO2012164865A1 (ja) | 2012-12-06 |
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