CN113348555B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN113348555B
CN113348555B CN201980089809.7A CN201980089809A CN113348555B CN 113348555 B CN113348555 B CN 113348555B CN 201980089809 A CN201980089809 A CN 201980089809A CN 113348555 B CN113348555 B CN 113348555B
Authority
CN
China
Prior art keywords
metal layer
layer
wiring
pad
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201980089809.7A
Other languages
English (en)
Other versions
CN113348555A (zh
Inventor
籏崎晃次
加藤敦史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Publication of CN113348555A publication Critical patent/CN113348555A/zh
Application granted granted Critical
Publication of CN113348555B publication Critical patent/CN113348555B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H01L2224/0348—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80359—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80905—Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
    • H01L2224/80906—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Wire Bonding (AREA)

Abstract

一实施方式的半导体装置具备：第1芯片，具有第1半导体衬底、设置于第1半导体衬底的第1半导体元件、连接于第1半导体元件的第1配线层、及连接于第1配线层的第1焊垫；以及第2芯片，具有第2半导体衬底、设置于第2半导体衬底的第2半导体元件、连接于第2半导体元件的第2配线层、及连接于第2配线层并且接合于第1焊垫的第2焊垫。第1焊垫及第2焊垫中的至少一个具有与另一个焊垫接合的第1金属层、热膨胀率高于第1金属层的第2金属层、及设置于第1金属层与第2金属层之间的势垒金属层。

Description

半导体装置及其制造方法
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
将半导体衬底彼此贴合的贴合技术中，例如，是将形成有存储器等半导体元件的半导体衬底与形成有该半导体元件的周边电路的半导体衬底进行贴合。此时，各衬底的焊垫(pad)被接合。
[背景技术文献]
[专利文献]
[专利文献1]日本专利特开2013-229415号公报
发明内容
[发明要解决的问题]
所述贴合技术中，通过使各焊垫中包含的金属热膨胀而使它们接合。然而，如果该金属的热膨胀量不充分，则会发生贴合不良。
本发明的实施方式提供一种能够避免贴合不良的半导体装置及其制造方法。
[解决问题的技术手段]
一实施方式的半导体装置具备：第1芯片，具有第1半导体衬底、设置于第1半导体衬底的第1半导体元件、连接于第1半导体元件的第1配线层、及连接于第1配线层的第1焊垫；以及第2芯片，具有第2半导体衬底、设置于第2半导体衬底的第2半导体元件、连接于第2半导体元件的第2配线层、及连接于第2配线层并且接合于第1焊垫的第2焊垫。第1焊垫及第2焊垫中的至少一个具有与另一个焊垫接合的第1金属层、热膨胀率高于第1金属层的第2金属层、及设置于第1金属层与第2金属层之间的势垒金属(barrier metal)层。
[发明的效果]
根据一实施方式，能够避免贴合不良。
附图说明
图1是表示一实施方式的半导体装置的主要部分的结构的剖视图。
图2是将半导体元件的一部分放大所得的剖视图。
图3是表示通孔部的形成步骤的剖视图。
图4是表示金属膜及势垒金属层的形成步骤的剖视图。
图5是表示金属膜的蚀刻步骤的剖视图。
图6是表示层间绝缘膜的成膜步骤的剖视图。
图7是表示通孔部的形成步骤的剖视图。
图8是表示金属层的形成步骤的剖视图。
图9是表示将存储器芯片与电路芯片的贴合部位的一部分放大所得的剖视图。
图10是表示焊垫接合的退火温度与热膨胀量的关系的图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式不限定本发明。
图1是表示一实施方式的半导体装置的主要部分的结构的剖视图。
本实施方式的半导体装置是将存储器芯片1(第1芯片)与电路芯片2(第2芯片)贴合而成的三维型半导体存储器。首先，对存储器芯片1的构成进行说明。存储器芯片1具有半导体衬底10、绝缘层11、半导体元件12(第1半导体元件)、接触插塞13a～13c、配线层14a,14b、焊垫15(第1焊垫)、及层间绝缘膜16。
半导体衬底10例如是硅衬底。半导体衬底10上设置有绝缘层11。绝缘层11例如是氧化硅层或氮化硅层。绝缘层11上设置有半导体元件12。
图2是将半导体元件12的一部分放大所得的剖视图。如图2所示，半导体元件12具有积层体120及存储膜130。
积层体120中，多个电极层121与多个绝缘层122在与半导体衬底10正交的Z方向上交替地积层。各电极层121例如是钨等金属层，且是存储膜130的字线。各绝缘层122例如是氧化硅层。如图1所示，积层体120的端部形成为阶梯状。在该阶梯状的端部，各电极层111经由接触插塞13a连接于配线层14a。
如图2所示，存储膜130在Z方向上贯通积层体120，且具备阻挡绝缘膜131、电荷存储层132、隧道绝缘膜133、信道层134、及核心绝缘膜135。电荷存储层132例如是氮化硅膜，隔着阻挡绝缘膜131形成于电极层121及绝缘层122的侧面。阻挡绝缘膜131、隧道绝缘膜133及核心绝缘膜135例如是氧化硅膜。信道层134例如是硅层，隔着隧道绝缘膜133形成于电荷存储层132的侧面。信道层134经由接触插塞13b连接于配线层14a(参照图1)。
如图1所示，配线层14a经由接触插塞13c连接于焊垫15或配线层14b。例如铝或铜能够用作接触插塞13a～13c及配线层14a,14b的材料。当接触插塞13a～13c与配线层14a,14b之间的金属材料不同时，期望在它们之间形成势垒金属层以防止金属扩散。
另外，图1中，将配线层14,14b的一部分简化而一体地示出，但实际上是由被层间绝缘膜16绝缘分离的多个配线所构成。
焊垫15具有金属层151(第1金属层)、势垒金属层152、及金属层153(第2金属层)。金属层151接合于电路芯片2。势垒金属层152设置于金属层151与金属层153之间。能够用势垒金属层152来防止金属层151的扩散。金属层153设置于与配线层14b相同的层。
本实施方式中，金属层151的材料是铜，金属层153的材料是铝，势垒金属层152的材料为氮化钛。另外，关于金属层151及金属层153的各材料，只要满足金属层153的热膨胀率大于金属层151的热膨胀率的关系，则无特别限制。
接下来，对电路芯片2的构成进行说明。如图1所示，电路芯片2具有衬底20、半导体元件21(第2半导体元件)、接触插塞22a～22e、配线层23a～23c、焊垫24(第2焊垫)、及层间绝缘膜25。
衬底20例如是硅衬底。在衬底20上设置有用于驱动存储器芯片1的半导体元件21。
半导体元件21是具有栅极电极21a、栅极绝缘膜21b及扩散层21c的MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)。扩散层21c是源极区域或漏极区域。栅极电极21a设置于栅极绝缘膜21b上，且经由接触插塞22a连接于配线层23a。扩散层21c经由接触插塞22b连接于配线层23a。
配线层23a经由接触插塞22c连接于配线层23b。配线层23b经由接触插塞22d连接于配线层23c。配线层23c经由接触插塞22e连接于焊垫24。
本实施方式中，例如铝或铜等能够用作接触插塞22a～22e及配线层23a～23c的材料。当接触插塞22a～22e与配线层23a～23c之间的金属材料不同时，期望在它们之间形成势垒金属层以防止金属扩散。
另外，图1中，将配线层23a～23c的一部分简化而一体地示出，但实际上是由被层间绝缘膜25绝缘分离的多个配线所构成。
焊垫24具有金属层241(第1金属层)、势垒金属层242、及金属层243(第2金属层)。金属层241接合于存储器芯片1的金属层151。势垒金属层242设置于金属层241与金属层243之间。能够用势垒金属层242防止金属层241的扩散。金属层243连接于接触插塞22e。另外，图1中虽未示出，但电路芯片2也可具有位于与金属层243相同的层的配线层。
本实施方式中，金属层241的材料是铜，金属层243的材料是铝，势垒金属层242的材料为氮化钛。另外，关于金属层241及金属层243的各材料，只要满足金属层243的热膨胀率大于金属层241的热膨胀率的关系，则无特别限制。
以下，对如所述构成的半导体装置的制造步骤的一部分进行说明。此处，参照图3～图8对焊垫15的制造步骤进行说明。另外，焊垫24也能够采用与焊垫15相同的制造步骤。
首先，如图3所示，在覆盖配线层14a的层间绝缘膜16a形成通孔部100。通孔部100到达配线层14a。
接下来，如图4所示，在层间绝缘膜15a的上表面形成金属膜200，且在该金属膜200上进一步形成势垒金属层201。金属膜200的材料是铝，该铝也嵌埋在通孔部100内。嵌埋在通孔部100内的铝是接触插塞13c。
接下来，如图5所示，例如利用RIE(Reactive Ion Etching，反应性离子蚀刻)来蚀刻金属膜200及势垒金属层201。由此，具有相同厚度t1的金属层153及配线层14b在同一层同时图案化。同时，势垒金属层152也在金属层153及配线层14b上图案化。另外，属于配线层14b的配线的一部分例如能够用作接合垫(bonding pad)。该接合垫与用于将电路芯片2连接于其他安装衬底等的接合线(未图示)接合。
接下来，如图6所示，层间绝缘膜16b以覆盖金属层153、配线层14b、势垒金属层152的方式在层间绝缘膜16a上成膜。层间绝缘膜16b能够例如利用CVD(Chemical VaporDeposition，化学气相沉积)及CMP(Chemical Mechanical Polishing，化学机械研磨)形成。
接下来，如图7所示，在层间绝缘膜16b形成孔部101。本实施方式中，孔部101的开口部的面积小于金属层153的平面积。而且，孔部101的深度d与金属层153的厚度t1相同。
接下来，如图8所示，通过将铜嵌埋于孔部101，而形成金属层151。如所述那样，孔部101的深度d与金属层153的厚度t1相同，因此金属层151的厚度t2与金属层153的厚度t1相同。然后，使存储器芯片1上下反转(旋转180度)而贴合于电路芯片2。
图9是将存储器芯片1与电路芯片2的贴合部位的一部分放大所得的剖视图。如图9所示，焊垫15的金属层151与焊垫24的金属层241接合。焊垫15具有热膨胀率大于金属层151的金属层153，焊垫24具有热膨胀率大于金属层241的金属层243。
图10是表示焊垫接合的退火温度与热膨胀量的关系的图。图10中，实线L1表示本实施方式的焊垫15的热膨胀量。具体来说，金属层151的材料是铜，金属层153的材料是铝，各层的厚度为600nm。另一方面，虚线L2表示比较例的焊垫的热膨胀率。该焊垫的材料是铜，厚度为1200nm。
如图10所示，在各退火温度下，本实施方式的焊垫15的热膨胀量大于比较例的焊垫的热膨胀量。因此，当焊垫15与焊垫24接合时即使退火温度低，也能够利用金属层153及金属层243的热膨胀，来补充金属层151及金属层241的热膨胀的不足。
因此，根据本实施方式，因能够无间隙地接合金属层151及金属层241，所以能够避免贴合不良。
而且，本实施方式中，金属层151与金属层153不经由接触插塞而连接。同样地，金属层241与金属层243也不经由接触插塞而连接。因此，在退火温度高的情况下，也能够避免所述接触插塞中包含的金属材料(铜)被吸到金属层151、241侧这一缺陷的发生。
另外，本实施方式中，焊垫15及焊垫24两者具有热膨胀率不同的2个金属层。然而，焊垫15或焊垫24也可具有所述2个金属层。即，焊垫15与焊垫24中的至少一个具有与另一个焊垫接合的第1金属层、热膨胀率高于所述第1金属层的第2金属层、设置于所述第1金属层与所述第2金属层之间的势垒金属层即可。该情况下，能够通过第2金属层补充第1金属层的热膨胀量的不足，而避免焊垫15与焊垫24的接合不良。
以上，对若干实施方式进行了说明，但这些实施方式仅作为例子提出，并不意图限定发明的范围。本说明书中说明的新颖的装置、方法、程序及系统能够以其他各种形态实施。此外，对于本说明书中说明的装置、方法、程序及系统的形态，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更。随附的权利要求书及与其均等的范围意图包含发明的范围及主旨中所包含的这种形态及变化例。

Claims (14)

1.一种半导体装置，具备：
第1芯片，具有第1半导体衬底、设置于所述第1半导体衬底的第1半导体元件、连接于第1半导体元件的第1配线层、及连接于所述第1配线层的第1焊垫；以及
第2芯片，具有第2半导体衬底、设置于所述第2半导体衬底的第2半导体元件、连接于所述第2半导体元件的第2配线层、及连接于所述第2配线层并且接合于所述第1焊垫的第2焊垫，
所述第1焊垫及所述第2焊垫中的至少一个具有与另一个焊垫接合的第1金属层、热膨胀率高于所述第1金属层的第2金属层、及设置于所述第1金属层与所述第2金属层之间的势垒金属层。
2.根据权利要求1所述的半导体装置，其中
所述第2金属层的平面积大于所述第1金属层的平面积。
3.根据权利要求1或2所述的半导体装置，其中
所述第2金属层包含铝。
4.根据权利要求1所述的半导体装置，其中
所述第1金属层包含铜。
5.根据权利要求1所述的半导体装置，其中
在所述第1配线层或所述第2配线层与所述第2金属层之间，还具备与所述第2金属层为相同材料的接触插塞。
6.根据权利要求1所述的半导体装置，其中
所述第2金属层设置于与属于所述第1配线层或所述第2配线层的配线相同的层。
7.根据权利要求1所述的半导体装置，其中
所述第1金属层的厚度与所述第2金属层的厚度相同。
8.一种半导体装置的制造方法，
在第1芯片形成第1半导体衬底、设置于所述第1半导体衬底的第1半导体元件、连接于第1半导体元件的第1配线层、及连接于所述第1配线层的第1焊垫，
形成第2半导体衬底、设置于所述第2半导体衬底的第2半导体元件、连接于所述第2半导体元件的第2配线层、及连接于所述第2配线层的第2焊垫，且
将所述第1焊垫与所述第2焊垫接合，
在所述第1焊垫及所述第2焊垫中的至少一个，形成与另一个焊垫接合的第1金属层、热膨胀率高于所述第1金属层的第2金属层、及设置于所述第1金属层与所述第2金属层之间的势垒金属层。
9.根据权利要求8所述的半导体装置的制造方法，其中
在所述第2金属层上形成孔部，所述孔部具有比所述第2金属层的平面积小的开口部的面积，在所述孔部内形成所述第1金属层。
10.根据权利要求8或9所述的半导体装置的制造方法，其中
使用铝来形成所述第2金属层。
11.根据权利要求8所述的半导体装置的制造方法，其中
使用铜来形成所述第1金属层。
12.根据权利要求8所述的半导体装置的制造方法，其中
在所述第1配线层或所述第2配线层与所述第2金属层之间，形成与所述第2金属层为相同材料的接触插塞。
13.根据权利要求8所述的半导体装置的制造方法，其中
在与属于所述第1配线层或所述第2配线层的配线相同的层，所述第2金属层与所述配线同时形成。
14.根据权利要求8所述的半导体装置的制造方法，其中
所述第1金属层的厚度与所述第2金属层的厚度形成为相同。
CN201980089809.7A 2019-03-18 2019-03-18 半导体装置及其制造方法 Active CN113348555B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/011275 WO2020188719A1 (ja) 2019-03-18 2019-03-18 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
CN113348555A CN113348555A (zh) 2021-09-03
CN113348555B true CN113348555B (zh) 2023-08-18

Family

ID=72520716

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980089809.7A Active CN113348555B (zh) 2019-03-18 2019-03-18 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US20210407938A1 (zh)
CN (1) CN113348555B (zh)
TW (1) TWI720527B (zh)
WO (1) WO2020188719A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023141977A (ja) * 2022-03-24 2023-10-05 キオクシア株式会社 半導体装置、半導体記憶装置、及び半導体装置の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426732A (zh) * 2012-05-18 2013-12-04 上海丽恒光微电子科技有限公司 低温晶圆键合的方法及通过该方法形成的结构
CN104916619A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置及其制造方法
JP2016021497A (ja) * 2014-07-15 2016-02-04 パナソニックＩｐマネジメント株式会社 半導体装置およびその製造方法
CN108140559A (zh) * 2015-08-25 2018-06-08 英帆萨斯邦德科技有限公司 传导阻障直接混合型接合

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8288211B2 (en) * 2005-08-26 2012-10-16 Innovative Micro Technology Wafer level hermetic bond using metal alloy with keeper layer
JP6014354B2 (ja) * 2012-04-25 2016-10-25 株式会社日立製作所 半導体装置の製造方法
JP6212720B2 (ja) * 2013-09-20 2017-10-18 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US9257399B2 (en) * 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
US9343369B2 (en) * 2014-05-19 2016-05-17 Qualcomm Incorporated Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems
JP6952629B2 (ja) * 2018-03-20 2021-10-20 株式会社東芝 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426732A (zh) * 2012-05-18 2013-12-04 上海丽恒光微电子科技有限公司 低温晶圆键合的方法及通过该方法形成的结构
CN104916619A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置及其制造方法
JP2016021497A (ja) * 2014-07-15 2016-02-04 パナソニックＩｐマネジメント株式会社 半導体装置およびその製造方法
CN108140559A (zh) * 2015-08-25 2018-06-08 英帆萨斯邦德科技有限公司 传导阻障直接混合型接合

Also Published As

Publication number Publication date
WO2020188719A1 (ja) 2020-09-24
TW202036736A (zh) 2020-10-01
US20210407938A1 (en) 2021-12-30
TWI720527B (zh) 2021-03-01
CN113348555A (zh) 2021-09-03

Similar Documents

Publication Publication Date Title
US11462496B2 (en) Semiconductor device
US10541230B2 (en) Semiconductor device and method for manufacturing same
TWI782794B (zh) 半導體裝置
US9917030B2 (en) Semiconductor structure and fabrication method thereof
US10090351B2 (en) Semiconductor device having gaps within the conductive parts
TWI397972B (zh) Semiconductor device manufacturing method
US20210091024A1 (en) Semiconductor device and method for manufacturing the same
US11195849B2 (en) Semiconductor device and method of manufacturing the same
TW202034403A (zh) 半導體裝置及其製造方法
CN113380781B (zh) 半导体装置及其制造方法
TWI814153B (zh) 半導體裝置及其製造方法
CN113348555B (zh) 半导体装置及其制造方法
US11355512B2 (en) Semiconductor device including a plug connected to a bit line and containing tungsten
TWI854341B (zh) 半導體裝置
TWI812000B (zh) 半導體裝置
TWI559414B (zh) 基底穿孔製程
JP2010212525A (ja) 半導体装置の製造方法及び半導体基板
JP2023177154A (ja) 半導体装置およびその製造方法
JP2015028972A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant