TWI814153B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
- Publication number
- TWI814153B TWI814153B TW110144381A TW110144381A TWI814153B TW I814153 B TWI814153 B TW I814153B TW 110144381 A TW110144381 A TW 110144381A TW 110144381 A TW110144381 A TW 110144381A TW I814153 B TWI814153 B TW I814153B
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- Prior art keywords
- insulating film
- film
- layer
- bonding pad
- semiconductor device
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 113
- 238000004519 manufacturing process Methods 0.000 title claims description 47
- 238000005476 soldering Methods 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 355
- 239000002184 metal Substances 0.000 claims description 355
- 239000000758 substrate Substances 0.000 claims description 59
- 239000010949 copper Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 14
- 229920001709 polysilazane Polymers 0.000 claims description 14
- 239000011701 zinc Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910052725 zinc Inorganic materials 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 2
- 239000001301 oxygen Substances 0.000 claims 2
- 229910052760 oxygen Inorganic materials 0.000 claims 2
- 239000010410 layer Substances 0.000 description 273
- 239000011229 interlayer Substances 0.000 description 78
- 239000000463 material Substances 0.000 description 50
- 235000012431 wafers Nutrition 0.000 description 49
- 230000004888 barrier function Effects 0.000 description 34
- 230000004048 modification Effects 0.000 description 16
- 238000012986 modification Methods 0.000 description 16
- 238000000137 annealing Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 238000009413 insulation Methods 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000005304 joining Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 230000001737 promoting effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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Abstract
根據一實施方式,半導體裝置具備第1絕緣膜、設置於上述第1絕緣膜內之第1焊墊、設置於上述第1絕緣膜上之第2絕緣膜、及在上述第2絕緣膜內設置於上述第1焊墊上之第2焊墊。進而,上述第1絕緣膜包含第1膜及第2膜,該第1膜與上述第1焊墊及上述第2絕緣膜相接,該第2膜與上述第1焊墊及上述第2絕緣膜隔開間隔而設,且具有設置於與上述第1焊墊之至少一部分相同高度之部分;且/或,上述第2絕緣膜包含第3膜及第4膜,該第3膜與上述第2焊墊及上述第1絕緣膜相接,該第4膜與上述第2焊墊及上述第1絕緣膜隔開間隔而設,且具有設置於與上述第2焊墊之至少一部分相同高度之部分。
Description
本發明之實施方式係關於一種半導體裝置及其製造方法。
於將某一基板與另一基板貼合而製造半導體裝置之情形時,較理想為減少該等基板之金屬焊墊彼此之接合不良。
本發明提供一種能夠將焊墊彼此恰當地接合之半導體裝置及其製造方法。
根據一實施方式,半導體裝置具備第1絕緣膜、設置於上述第1絕緣膜內之第1焊墊、設置於上述第1絕緣膜上之第2絕緣膜、及在上述第2絕緣膜內設置於上述第1焊墊上之第2焊墊。進而,上述第1絕緣膜包含第1膜及第2膜,該第1膜與上述第1焊墊及上述第2絕緣膜相接,該第2膜與上述第1焊墊及上述第2絕緣膜隔開間隔而設,且具有設置於與上述第1焊墊之至少一部分相同高度之部分;且/或,上述第2絕緣膜包含第3膜及第4膜,該第3膜與上述第2焊墊及上述第1絕緣膜相接,該第4膜與上述第2焊墊及上述第1絕緣膜隔開間隔而設,且具有設置於與上述第2焊墊之至少一部分相同高度之部分。
根據上述構成,可提供一種能夠將焊墊彼此恰當地接合之半導體裝置及其製造方法。
以下,參照附圖對本發明之實施方式進行說明。圖1~圖33中,對相同之構成標註相同之符號,並省略重複說明。
(第1實施方式)圖1係表示第1實施方式之半導體裝置之構造之剖視圖。圖1之半導體裝置例如係三維記憶體,如下所述,係藉由將包含陣列區域1之陣列晶圓與包含電路區域2之電路晶圓貼合而製成。
陣列區域1具備包含複數個記憶胞之記憶胞陣列11、記憶胞陣列11上之絕緣膜12、及記憶胞陣列11下之層間絕緣膜13。絕緣膜12例如為氧化矽膜(SiO
2膜)或氮化矽膜(SiN膜)。層間絕緣膜13例如為氧化矽膜、或包含氧化矽膜與其他絕緣膜之積層膜。層間絕緣膜13係第2絕緣膜之例。
電路區域2設置於陣列區域1下。符號S表示陣列區域1與電路區域2之交界面(貼合面)。電路區域2具備層間絕緣膜14、及層間絕緣膜14下之基板15。層間絕緣膜14例如為氧化矽膜、或包含氧化矽膜與其他絕緣膜之積層膜。層間絕緣膜14係第1絕緣膜之例。基板15例如為矽(Si)基板等半導體基板。
圖1中示出了與基板15之表面平行且相互垂直之X方向及Y方向、以及與基板15之表面垂直之Z方向。於本說明書中,將+Z方向視為上方向,將-Z方向視為下方向。-Z方向與重力方向可一致,亦可不一致。
陣列區域1具備複數個字元線WL及源極線SL作為記憶胞陣列11內之複數個電極層。圖1中示出了記憶胞陣列11之階梯構造部21。各字元線WL經由接觸插塞22與字配線層23電性連接。貫通上述複數個字元線WL之各柱狀部CL經由介層插塞24與位元線BL電性連接,且與源極線SL電性連接。源極線SL包含作為半導體層之下部層SL1、及作為金屬層之上部層SL2。
電路區域2具備複數個電晶體31。各電晶體31具備隔著閘極絕緣膜而設置於基板15上之閘極電極32、以及設置於基板15內之未圖示之源極擴散層及汲極擴散層。又,電路區域2具備設置於該等電晶體31之閘極電極32、源極擴散層或汲極擴散層上之複數個接觸插塞33、設置於該等接觸插塞33上且包含複數個配線之配線層34、以及設置於配線層34上且包含複數個配線之配線層35。
電路區域2進而具備設置於配線層35上且包含複數個配線之配線層36、設置於配線層36上之複數個介層插塞37、以及設置於該等介層插塞37上之複數個金屬焊墊38。金屬焊墊38例如為包含Cu(銅)層之金屬層。金屬焊墊38係第1焊墊之例。電路區域2作為控制陣列區域1之動作之控制電路(邏輯電路)發揮功能。該控制電路包含電晶體31等,且電性連接於金屬焊墊38。
陣列區域1具備設置於金屬焊墊38上之複數個金屬焊墊41、以及設置於金屬焊墊41上之複數個介層插塞42。又,陣列區域1具備設置於該等介層插塞42上且包含複數個配線之配線層43、以及設置於配線層43上且包含複數個配線之配線層44。金屬焊墊41例如為包含Cu層之金屬層。金屬焊墊41係第2焊墊之例。上述位元線BL包含於配線層44中。上述控制電路經由金屬焊墊41、38等而電性連接於記憶胞陣列11,且經由金屬焊墊41、38等而控制記憶胞陣列11之動作。
陣列區域1進而具備設置於配線層44上之複數個介層插塞45、設置於該等介層插塞45上及絕緣膜12上之金屬焊墊46、以及設置於金屬焊墊46上及絕緣膜12上之鈍化膜47。金屬焊墊46例如為包含Cu層之金屬層,作為圖1之半導體裝置之外部連接焊墊(接合焊墊)發揮功能。鈍化膜47例如為氧化矽膜等絕緣膜,具有使金屬焊墊46之上表面露出之開口部P。金屬焊墊46可經由該開口部P並藉由接合線、焊錫球、金屬凸塊等而連接於安裝基板或其他裝置。
圖2係表示第1實施方式之柱狀部CL之構造之剖視圖。圖2中示出了圖1所示之複數個柱狀部CL中之一個。
如圖2所示,記憶胞陣列11具備在層間絕緣膜13(圖1)上交替積層之複數個字元線WL與複數個絕緣層51。字元線WL例如為W(鎢)層。絕緣層51例如為氧化矽膜。
柱狀部CL依序包含阻擋絕緣膜52、電荷儲存層53、隧道絕緣膜54、通道半導體層55及核心絕緣膜56。電荷儲存層53例如為氮化矽膜等絕緣膜,隔著阻擋絕緣膜52而形成於字元線WL及絕緣層51之側面。電荷儲存層53亦可為多晶矽層等半導體層。通道半導體層55例如為多晶矽層,隔著隧道絕緣膜54而形成於電荷儲存層53之側面。阻擋絕緣膜52、隧道絕緣膜54及核心絕緣膜56例如為氧化矽膜或金屬絕緣膜。
圖3及圖4係表示第1實施方式之半導體裝置之製造方法之剖視圖。
圖3中示出了包含複數個陣列區域1之陣列晶圓W1、以及包含複數個電路區域2之電路晶圓W2。陣列晶圓W1亦被稱為「記憶體晶圓」,電路晶圓W2亦被稱為「CMOS(Complementary Metal Oxide Semiconductor,互補金屬氧化物半導體)晶圓」。
圖3之陣列晶圓W1之方向與圖1之陣列區域1之方向相反。於本實施方式中,藉由將陣列晶圓W1與電路晶圓W2貼合而製造半導體裝置。圖3中示出了為進行貼合而使方向反轉之前之陣列晶圓W1,圖1中示出了為進行貼合而使方向反轉並貼合及切割後之陣列區域1。
圖3中,符號S1表示陣列晶圓W1之上表面,符號S2表示電路晶圓W2之上表面。陣列晶圓W1具備設置於絕緣膜12下之基板16。基板16例如為矽基板等半導體基板。基板15係第1基板之例,基板16係第2基板之例。
於本實施方式中,首先,如圖3所示,於陣列晶圓W1之基板16上形成記憶胞陣列11、絕緣膜12、層間絕緣膜13、階梯構造部21、金屬焊墊41等,於電路晶圓W2之基板15上形成層間絕緣膜14、電晶體31、金屬焊墊38等。例如,於基板16上依序形成介層插塞45、配線層44、配線層43、介層插塞42及金屬焊墊41。又,於基板15上依序形成接觸插塞33、配線層34、配線層35、配線層36、介層插塞37及金屬焊墊38。繼而,如圖4所示,藉由機械壓力將陣列晶圓W1與電路晶圓W2貼合。藉此,層間絕緣膜13與層間絕緣膜14被接著。繼而,對陣列晶圓W1及電路晶圓W2進行退火。藉此,金屬焊墊41與金屬焊墊38得以接合。
然後,藉由CMP(Chemical Mechanical Polishing,化學機械拋光)將基板15薄膜化,並藉由CMP去除基板16之後,將陣列晶圓W1及電路晶圓W2切斷成複數個晶片。以此方式來製造圖1之半導體裝置。再者,金屬焊墊46與鈍化膜47例如係於基板15薄膜化及去除基板16之後形成於絕緣膜12上。
再者,本實施方式係將陣列晶圓W1與電路晶圓W2貼合,但亦可取而代之,將陣列晶圓W1彼此貼合。上文中參照圖1~圖4敍述之內容、以及下文中將參照圖5~圖33敍述之內容亦同樣適用於將陣列晶圓W1彼此貼合之情況。
又,圖1中示出了層間絕緣膜13與層間絕緣膜14之交界面、以及金屬焊墊41與金屬焊墊38之交界面,但於上述退火之後,通常不再能觀察到上述交界面。但是,可藉由檢測例如金屬焊墊41之側面或金屬焊墊38之側面之斜率、或者金屬焊墊41之側面與金屬焊墊38之位置偏移,推定上述交界面所處之位置。
以下,參照圖5~圖15對本實施方式之半導體裝置更詳細地說明。
圖5係表示第1實施方式之半導體裝置之構造之剖視圖。
圖5(a)係表示圖1所示之複數對金屬焊墊38、41中之一對之縱剖視圖。圖5(a)中,金屬焊墊38在層間絕緣膜14內設置於介層插塞37上,金屬焊墊41在層間絕緣膜13內設置於介層插塞42下。圖5(b)係沿著圖5(a)所示之A-A'線之橫剖視圖,表示金屬焊墊41之XY剖面。圖5(c)係沿著圖5(a)所示之B-B'線之橫剖視圖,表示金屬焊墊38之XY剖面。
以下,對圖5(a)所示之金屬焊墊38、41及層間絕緣膜14、13更詳細地說明。於該說明中,亦適當地參照圖5(b)及圖5(c)。
如圖5(a)所示,金屬焊墊38包含障壁金屬層38a及焊墊材料層38b。障壁金屬層38a形成於層間絕緣膜14之側面及上表面,焊墊材料層38b隔著障壁金屬層38a而形成於層間絕緣膜14內。同樣,金屬焊墊41包含障壁金屬層41a及焊墊材料層41b。障壁金屬層41a形成於層間絕緣膜13之側面及下表面,焊墊材料層41b隔著障壁金屬層41a而形成於層間絕緣膜14內。障壁金屬層38a、41a例如為包含Ti(鈦)元素或Ta(鉭)元素之金屬層。焊墊材料層38b、41b例如為包含Cu層之金屬層。藉此,金屬焊墊38、41亦被稱為「Cu焊墊」。
本實施方式之層間絕緣膜14包含絕緣膜14a及絕緣膜14b。絕緣膜14a與金屬焊墊38及層間絕緣膜13相接,配置於金屬焊墊38之橫向及下方向等。另一方面,絕緣膜14b與金屬焊墊38及層間絕緣膜13均不相接,配置於金屬焊墊38之橫向。即,絕緣膜14b與金屬焊墊38及層間絕緣膜13隔開間隔而配置。於本實施方式中,絕緣膜14b之厚度較金屬焊墊38之厚度薄,故整個絕緣膜14b位於與金屬焊墊38之一部分相同之高度。因此,與XY平面平行之B-B'線穿過金屬焊墊38與絕緣膜14b之兩者。絕緣膜14a係第1膜之例,絕緣膜14b係第2膜之例。
再者,上述「高度」之基準例如係交界面S。又,上述「高度」之基準亦可為基板15之上表面。此基準於下文出現之「高度」一詞中亦同樣。
本實施方式之絕緣膜14a與絕緣膜14b均為SiO
2膜。但是,本實施方式之絕緣膜14a例如係使用dTEOS(densified tetraethyl orthosilicate,稠化四乙氧基矽烷)而形成。另一方面,本實施方式之絕緣膜14b例如係使用PSZ(聚矽氮烷)而形成。因此,絕緣膜14b包含N(氮)原子作為雜質原子,絕緣膜14b內之N原子濃度變得較絕緣膜14a內之N原子濃度高。進而,絕緣膜14b於製造半導體裝置時之熱步驟中會收縮。於製造本實施方式之半導體裝置時,如下所述,藉由利用絕緣膜14b之此種性質,可將金屬焊墊38與金屬焊墊41恰當地接合。
再者,本實施方式之絕緣膜14b亦可為在製造半導體裝置時之熱步驟中會收縮之其他SiO
2膜(例如NSG(None-doped Silicate Glass,無摻雜矽酸鹽玻璃)膜)。又,本實施方式之絕緣膜14a、14b亦可為SiO
2膜以外之膜。
本實施方式之層間絕緣膜13包含絕緣膜13a及絕緣膜13b。絕緣膜13a與金屬焊墊41及層間絕緣膜14相接,配置於金屬焊墊41之橫向及上方向等。另一方面,絕緣膜13b與金屬焊墊41及層間絕緣膜14均不相接,配置於金屬焊墊41之橫向。即,絕緣膜13b與金屬焊墊41及層間絕緣膜14隔開間隔而配置。於本實施方式中,絕緣膜13b之厚度較金屬焊墊41之厚度薄,故整個絕緣膜13b位於與金屬焊墊41之一部分相同之高度。因此,與XY平面平行之A-A'線通過金屬焊墊41及絕緣膜13b兩者。絕緣膜13a係第3膜之例,絕緣膜13b係第4膜之例。
本實施方式之絕緣膜13a與絕緣膜13b均為SiO
2膜。但是,本實施方式之絕緣膜13a例如使用dTEOS而形成。另一方面,本實施方式之絕緣膜13b例如係使用PSZ而形成。因此,絕緣膜13b包含N原子作為雜質原子,絕緣膜13b內之N原子濃度高於較絕緣膜13a內之N原子濃度。再者,絕緣膜13b於製造半導體裝置時之熱步驟中會收縮。於製造本實施方式之半導體裝置時,如下所述,藉由利用絕緣膜13b之此種性質,可將金屬焊墊38與金屬焊墊41恰當地接合。
再者,本實施方式之絕緣膜13b亦可為於製造半導體裝置時之熱步驟中會收縮之其他SiO
2膜(例如NSG膜)。又,本實施方式之絕緣膜13a、13b亦可為SiO
2膜以外之膜。
如圖5(a)所示,本實施方式之絕緣膜13a包含設置於金屬焊墊41之側面與絕緣膜13b之側面之間的部分P1。藉此,絕緣膜13b不與金屬焊墊41相接。部分P1係第2部分之例。同樣地,本實施方式之絕緣膜14a包含設置於金屬焊墊38之側面與絕緣膜14b之側面之間的部分P2。藉此,絕緣膜14b不與金屬焊墊38相接。部分P2係第1部分之例。
圖5(b)示出了絕緣膜13a之部分P1之XY剖面。如圖5(b)所示,本實施方式之部分P1具有包圍金屬焊墊41之環狀之平面形狀。部分P1進而被絕緣膜13b包圍成環狀。
圖5(c)示出了絕緣膜14a之部分P2之XY剖面。如圖5(c)所示,本實施方式之部分P2具有包圍金屬焊墊38之環狀之平面形狀。部分P2進而被絕緣膜14b包圍成環狀。
圖6係表示第1實施方式之半導體裝置之2個構造例之剖視圖。
圖6(a)表示本實施方式之半導體裝置之構造之第1例。圖6(a)係表示較圖5(b)更廣範圍之橫剖視圖。於該例中,各金屬焊墊41具有實心四邊形之平面形狀,包圍各金屬焊墊41之部分P1具有中空四邊形之平面形狀。於該例中,1個絕緣膜13b隔著複數個部分P1將複數個金屬焊墊41個別地包圍。
圖6(b)表示本實施方式之半導體裝置之構造之第2例。圖6(b)與圖6(a)同樣,係表示較圖5(b)更廣範圍之橫剖視圖,但表示與圖6(a)所示之構造不同之構造。於該例中,各金屬焊墊41具有實心六邊形之平面形狀,包圍各金屬焊墊41之部分P1具有近似中空六邊形之平面形狀。具體而言,各部分P1具有複數個(此處為6個)六邊形組合而成之環狀之平面形狀,該等六邊形各自具有與1個金屬焊墊41相同之尺寸。同樣,絕緣膜13b亦具有複數個六邊形組合而成之平面形狀,該等六邊形各自具有與1個金屬焊墊41相同之尺寸。如此,該例之金屬焊墊41、部分P1及絕緣膜13b之平面形狀具有蜂窩構造。該例中,同樣地,1個絕緣膜13b隔著複數個部分P1將複數個金屬焊墊41個別地包圍。
再者,第1例中之金屬焊墊38、部分P2及絕緣膜14b之平面形狀分別與金屬焊墊41、部分P1及絕緣膜13b之平面形狀相同。又,第2例中之金屬焊墊38、部分P2及絕緣膜14b之平面形狀分別與金屬焊墊41、部分P1及絕緣膜13b之平面形狀相同。
圖7係表示第1實施方式之第1變化例之半導體裝置之構造之剖視圖。圖7(a)~圖7(c)分別對應於圖5(a)~圖5(c)。
本變化例之絕緣膜14b與第1實施方式之絕緣膜14b同樣,不與金屬焊墊38及層間絕緣膜13相接,配置於金屬焊墊38之橫向等。同樣,本變化例之絕緣膜13b不與金屬焊墊41及層間絕緣膜14相接,配置於金屬焊墊41之橫向等。
但是,本變化例之絕緣膜14b之厚度較金屬焊墊38之厚度厚,絕緣膜14b僅一部分位於與金屬焊墊38之一部分相同之高度。藉此,本變化例之絕緣膜14b不僅包含位於較金屬焊墊38之下表面更高位置之部分,亦包含位於較金屬焊墊38之下表面更低位置之部分。同樣,本變化例之絕緣膜13b之厚度較金屬焊墊41之厚度厚,絕緣膜13b僅一部分位於與金屬焊墊41之一部分相同之高度。藉此,本變化例之絕緣膜13b不僅包含位於較金屬焊墊41之上表面更低位置之部分,亦包含位於較金屬焊墊41之上表面更高位置之部分。根據本變化例,可利用具有此種形狀之絕緣膜14b、13b而將金屬焊墊38與金屬焊墊41恰當地接合。
再者,本變化例之絕緣膜14b之厚度亦可較金屬焊墊38之厚度薄,本變化例之絕緣膜13b之厚度亦可較金屬焊墊41之厚度薄。
圖8係表示第1實施方式之第2變化例之半導體裝置之構造之剖視圖。圖8(a)~圖8(c)分別對應於圖5(a)~圖5(c)。
本變化例之層間絕緣膜14包含具有與第1變化例之絕緣膜14a、14b相同形狀之絕緣膜14a、14b。另一方面,本變化例之層間絕緣膜13包含絕緣膜13a,但不包含絕緣膜13b。根據本變化例,可利用具有此種形狀之絕緣膜14b而將金屬焊墊38與金屬焊墊41恰當地接合。
圖9係表示第1實施方式之第3變化例之半導體裝置之構造之剖視圖。圖9(a)~圖9(c)分別對應於圖5(a)~圖5(c)。
本變化例之層間絕緣膜13包含具有與第1變化例之絕緣膜13a、13b相同形狀之絕緣膜13a、13b。另一方面,本變化例之層間絕緣膜14包含絕緣膜14a,但不包含絕緣膜14b。根據本變化例,可利用具有此種形狀之絕緣膜13b而將金屬焊墊38與金屬焊墊41恰當地接合。
圖10係表示第1實施方式之半導體裝置之製造方法之概況之剖視圖。圖10(a)~圖10(c)表示圖3及圖4所示之方法之詳情。
圖10(a)中示出了與電路區域2(電路晶圓W2)貼合之前之陣列區域1(陣列晶圓W1)。圖10(a)中,金屬焊墊38之上表面相對於層間絕緣膜14之上表面向下方向凹陷,金屬焊墊41之下表面相對於層間絕緣膜13之下表面向上方向凹陷。該等凹陷被稱為碟狀凹陷(dishing),例如於藉由CMP使層間絕緣膜14、13之表面平坦化時產生。即使將陣列區域1與電路區域2貼合,仍會擔心因該等凹陷而導致無法恰當地將金屬焊墊41與金屬焊墊38接合。
圖10(b)示出了與電路區域2貼合後且進行用於將金屬焊墊38、41接合之退火之前的陣列區域1。圖10(b)中,因上述凹陷而導致金屬焊墊41與金屬焊墊38之間產生了間隙。若不消除該間隙,則會擔心產生金屬焊墊41與金屬焊墊38之接合不良。
圖10(c)示出了與電路區域2貼合後且進行了用於將金屬焊墊38、41接合之退火後的陣列區域1。圖10(c)中,金屬焊墊41與金屬焊墊38之間之間隙已消除,金屬焊墊41與金屬焊墊38恰當地接合。該現象緣於因退火而引起之金屬焊墊41、38之熱膨脹、以及因退火而體現出來的絕緣膜14b、13b之作用。
此處,對本實施方式之絕緣膜14b、13b之作用進行說明。
本實施方式之絕緣膜14b、13b例如係使用PSZ(聚矽氮烷)而形成。因此,當對金屬焊墊41、38進行退火時,絕緣膜14b、13b被加熱而收縮。藉此,從絕緣膜14b、13b對金屬焊墊41、38施加壓縮應力,金屬焊墊41與金屬焊墊38容易接近。藉此,根據本實施方式,藉由金屬焊墊41、38之熱膨脹及絕緣膜14b、13b之作用,能夠將金屬焊墊41與金屬焊墊38恰當地接合。
本實施方式之絕緣膜14b之厚度因上述退火時之收縮而減少例如大於9%且25%以下之量。於用T1表示收縮前之絕緣膜14b之厚度,用T2表示收縮後之絕緣膜14b之厚度之情形時,T1×0.75≦T2<T1×0.91之關係成立。同樣,本實施方式之絕緣膜13b之厚度因上述退火時之收縮而減少例如大於9%且25%以下之量。藉此,能夠產生足夠之壓縮應力,從而能夠將金屬焊墊41與金屬焊墊38充分恰當地接合。
本實施方式之金屬焊墊41、38例如包含Cu層。藉此,為了抑制退火對Cu層造成之不良影響,較理想為於400℃以下進行金屬焊墊41、38之退火。藉此,較理想為,本實施方式之絕緣膜14b之厚度藉由400℃以下之退火而減少大於9%且25%以下之量。此種絕緣膜14b例如可藉由使用PSZ形成絕緣膜14b而實現。此情況對於絕緣膜13b亦同樣。
本實施方式之層間絕緣膜14較理想為不僅包含使用PSZ等形成之絕緣膜14b,亦包含使用dTEOS等形成之絕緣膜14a。理由如下,於基板15上剛形成PSZ膜之後,PSZ膜便立即具有接近液體之性質,而難以對PSZ膜進行加工(例如CMP)。
圖11~圖15係表示第1實施方式之半導體裝置之製造方法之詳情之剖視圖。圖11(a)~圖15(b)表示圖10(a)~圖10(c)所示之方法之詳情。
圖11(a)中示出了電路區域2(電路晶圓W2)之一部分。當形成電路區域2時,於基板15之上方形成絕緣膜14a1,於絕緣膜14a1內形成介層插塞37,於絕緣膜14a1及介層插塞37上形成絕緣膜14a2(圖11(a))。絕緣膜14a1、14a2係絕緣膜14a之一部分,例如使用dTEOS作為原料氣體並藉由CVD(Chemical Vapor Deposition,化學氣相沈積)而形成。
繼而,藉由微影法及RIE(Reactive Ion Etching,反應性離子蝕刻),於絕緣膜14a2內形成凹部H1(圖11(b))。繼而,於凹部H1內形成絕緣膜14b(圖12(a))。絕緣膜14b例如係使用PSZ藉由塗佈法而形成。本實施方式之絕緣膜14b例如可形成為具有圖5(c)及圖6(a)所示之平面形狀,亦可形成為具有圖6(b)所示之平面形狀。
繼而,於絕緣膜14a2、14b上形成絕緣膜14a3(圖12(b))。絕緣膜14a3係絕緣膜14a之一部分,例如係使用dTEOS藉由CVD而形成。繼而,藉由微影法及RIE,於絕緣膜14a2、14a3內形成凹部H2(圖13(a))。其結果為,介層插塞37之上表面露出於凹部H2內。凹部H2被用作供嵌埋金屬焊墊38之焊墊槽。
繼而,於介層插塞37及絕緣膜14a1、14a2、14a3上形成障壁金屬層38a(圖13(b))。障壁金屬層38a例如為包含Ti元素或Ta元素之金屬層,藉由CVD而形成。
繼而,於介層插塞37及絕緣膜14a1、14a2、14a3上,隔著障壁金屬層38a而形成焊墊材料層38b(圖14(a))。焊墊材料層38b例如為Cu層,藉由鍍覆法而形成。
繼而,藉由CMP使焊墊材料層38b之表面平坦化(圖14(b))。其結果為,凹部H2外之障壁金屬層38a及焊墊材料層38b被去除,於凹部H2內形成金屬焊墊38。本實施方式之金屬焊墊38形成於與絕緣膜14a1、14a2、14a3相接但不與絕緣膜14b相接之位置。圖14(b)中,絕緣膜14b之厚度較金屬焊墊38之厚度薄,整個絕緣膜13b位於與金屬焊墊38之一部分相同之高度。
圖15(a)中示出了陣列區域1(陣列晶圓W1)之一部分。圖15(a)所示之陣列區域1與電路區域2同樣,係藉由圖11(a)~圖14(b)所示之步驟而形成。其中,基板16、絕緣膜13a內之絕緣膜13a1、13a2、13a3、絕緣膜13b、介層插塞42、障壁金屬層41a、焊墊材料層41b等分別與基板15、絕緣膜14a內之絕緣膜14a1、14a2、14a3、絕緣膜14b、介層插塞37、障壁金屬層38a、焊墊材料層38b等同樣地被處理。
繼而,以金屬焊墊41配置於金屬焊墊38上且絕緣膜13a1(層間絕緣膜13)配置於絕緣膜14a1(層間絕緣膜14)上之方式,將基板15與基板16貼合(圖15(b))。具體而言,藉由利用機械壓力將層間絕緣膜14與層間絕緣膜13貼合,而將層間絕緣膜14與層間絕緣膜13接著。進而,藉由對金屬焊墊38、41及層間絕緣膜14、13等進行退火,而將金屬焊墊41與金屬焊墊38接合。於上述退火時,絕緣膜14b、13b會收縮,由此可促進金屬焊墊38、41之接合。
然後,藉由CMP使基板15薄膜化,並藉由CMP去除基板16之後,將陣列晶圓W1及電路晶圓W2(參照圖4)切斷成複數個晶片。以此方式來製造圖5等所示之本實施方式之半導體裝置。
再者,利用圖11(a)~圖15(b)所示之方法形成之絕緣膜14b、13b亦可具有本實施方式之第1~第3變化例中之任一種形狀。絕緣膜14b之形狀可藉由調整凹部H1之形狀而控制。同樣,絕緣膜13b之形狀亦可藉由調整與凹部H1對應之凹部之形狀而控制。
如上所述,本實施方式之半導體裝置具備不僅包含絕緣膜14a亦包含絕緣膜14b之層間絕緣膜14、以及不僅包含絕緣膜13a亦包含絕緣膜13b之層間絕緣膜14。絕緣膜14a、13a例如使用dTEOS而形成。絕緣膜14b、13b例如使用PSZ而形成。藉此,根據本實施方式,可利用絕緣膜14b、13b之作用而將金屬焊墊38與金屬焊墊41恰當地接合。
(第2實施方式)圖16係表示第2實施方式之半導體裝置之構造之剖視圖。
圖16與圖5(a)同樣,係表示圖1所示之複數對金屬焊墊38、41中之1對之縱剖視圖。圖16中,金屬焊墊38在層間絕緣膜14內設置於介層插塞37上,金屬焊墊41在層間絕緣膜13內設置於介層插塞42下。進而,介層插塞37在層間絕緣膜14內設置於配線層36上,介層插塞42在層間絕緣膜13內設置於配線層43下。
以下,對圖16所示之金屬焊墊38、41及層間絕緣膜14、13更詳細地說明。於該說明中,針對與圖5(a)所示之金屬焊墊38、41及層間絕緣膜14、13共通之事項,適當地省略說明。
如圖16所示,本實施方式之層間絕緣膜14包含複數個絕緣膜14a、絕緣膜14c及絕緣膜14d。各絕緣膜14a例如為使用dTEOS而形成之SiO
2膜。絕緣膜14c設置於介層插塞37之橫向,且被夾在2個絕緣膜14a之間。絕緣膜14c例如為SiCN膜(碳氮化矽膜)。絕緣膜14d設置於配線層36之上表面,且被夾在2個絕緣膜14a之間。絕緣膜14d例如為SiN膜。
同樣,本實施方式之層間絕緣膜13包含複數個絕緣膜13a、絕緣膜13c及絕緣膜13d。各絕緣膜13a例如為使用dTEOS而形成之SiO
2膜。絕緣膜13c設置於介層插塞42之橫向,且被夾在2個絕緣膜13a之間。絕緣膜13c例如為SiCN膜。絕緣膜13d設置於配線層43之下表面,且被夾在2個絕緣膜13a之間。絕緣膜13d例如為SiN膜。
本實施方式之半導體裝置進而具備設置於最上位之絕緣膜14a內之金屬層39。金屬層39位於介層插塞37之橫向,與介層插塞37相接。又,金屬層39位於金屬焊墊38之下方向及配線層36之上方向,與金屬焊墊38及配線層36均不相接。即,金屬層39與金屬焊墊38及配線層36隔開間隔而配置。本實施方式之金屬層39具有包圍介層插塞37之環狀之平面形狀。金屬層39係第1層及第1金屬層之例。
於本實施方式中,金屬層39之厚度較介層插塞37之厚度薄,故整個金屬層39位於與介層插塞37之一部分相同之高度。因此,金屬層39之上表面位於較介層插塞37之上表面更低之高度,金屬層39之下表面位於較介層插塞37之下表面更高之高度。又,本實施方式之金屬層39之厚度較金屬焊墊38之厚度薄,例如為金屬焊墊38之厚度之5%以上且30%以下。於用T3表示金屬焊墊38之厚度,用T4表示金屬層39之厚度之情形時,T3×0.05≦T4≦T3×0.30之關係成立。
本實施方式之金屬層39具有較金屬焊墊38之焊墊材料層38b之線膨脹係數大之線膨脹係數。藉此,於製造半導體裝置時之熱步驟中,金屬層39之熱膨脹率變得較焊墊材料層38b之熱膨脹率大。於製造本實施方式之半導體裝置時,如下所述,可利用金屬層39之此種性質來將金屬焊墊38與金屬焊墊41恰當地接合。例如,焊墊材料層38b為Cu(銅)層,金屬層39為Al(鋁)層或Zn(鋅)層。於相同溫度下,鋁或鋅具有較銅大之線膨脹係數。例如,20℃下之銅、鋁及鋅之線膨脹係數分別為16.5×10
-6/℃、23.1×10
-6/℃及30.2×10
-6/℃。再者,關於線膨脹係數之更詳細之說明將於下文敍述。
本實施方式之半導體裝置進而具備設置於最下位之絕緣膜13a內之金屬層48。金屬層48位於介層插塞42之橫向,與介層插塞42相接。又,金屬層48位於金屬焊墊41之上方向及配線層43之下方向,與金屬焊墊41及配線層43均不相接。即,金屬層48與金屬焊墊41及配線層43隔開間隔而配置。本實施方式之金屬層48具有包圍介層插塞42之環狀之平面形狀。金屬層48係第2層及第2金屬層之例。
於本實施方式中,金屬層48之厚度介層插塞42之厚度薄,故整個金屬層48位於與介層插塞42之一部分相同之高度。因此,金屬層48之下表面位於較介層插塞42之下表面更高之高度,金屬層48之上表面位於較介層插塞42之上表面更低之高度。又,本實施方式之金屬層48之厚度較金屬焊墊41之厚度薄,例如為金屬焊墊41之厚度之5%以上且30%以下。
本實施方式之金屬層48具有較金屬焊墊41之焊墊材料層41b之線膨脹係數大之線膨脹係數。藉此,於製造半導體裝置時之熱步驟中,金屬層48之熱膨脹率大於焊墊材料層41b之熱膨脹率。於製造本實施方式之半導體裝置時,如下所述,利用金屬層48之此種性質,可將金屬焊墊38與金屬焊墊41恰當地接合。例如,焊墊材料層41b為Cu層,金屬層48為Al層或Zn層。
再者,本實施方式之半導體裝置可代替金屬層39,而具備具有較焊墊材料層38b大之線膨脹係數之非金屬層,亦可代替金屬層48,而具備具有較焊墊材料層41b大之線膨脹係數之非金屬層。於此情形時,利用上述非金屬層之此種性質,可將金屬焊墊38與金屬焊墊41恰當地接合。上述非金屬層可由無機物形成,亦可由有機物形成。
圖17係表示第2實施方式之第1變化例之半導體裝置之構造之剖視圖。
本變化例之金屬層39不僅與介層插塞37相接,亦與金屬焊墊39相接。同樣地,本變化例之金屬層48不僅與介層插塞42相接,亦與金屬焊墊41相接。根據本變化例,與第2實施方式同樣地,利用金屬層39、48大幅膨脹之性質,可將金屬焊墊38與金屬焊墊41恰當地接合。
圖18係表示第2實施方式之第2變化例之半導體裝置之構造之剖視圖。
本變化例之金屬層39以與介層插塞37分離之狀態將介層插塞37環狀包圍,且不與介層插塞37相接。同樣地,本變化例之金屬層48以與介層插塞42分離之狀態將介層插塞42環狀包圍,且不與介層插塞42相接。根據本變化例,與第2實施方式同樣地,利用金屬層39、48大幅膨脹之性質,可將金屬焊墊38與金屬焊墊41恰當地接合。
圖19係表示第2實施方式之第3變化例之半導體裝置之構造之剖視圖。
本變化例之半導體裝置具備具有與第1實施方式之金屬層39相同形狀之金屬層39,但不具備金屬層48。根據本變化例,可利用金屬層39大幅膨脹之性質來將金屬焊墊38與金屬焊墊41恰當地接合。
圖20係表示第2實施方式之第4變化例之半導體裝置之構造之剖視圖。
本變化例之半導體裝置具備具有與第1實施方式之金屬層48相同形狀之金屬層48,但不具備金屬層39。根據本變化例,可利用金屬層48大幅膨脹之性質來將金屬焊墊38與金屬焊墊41恰當地接合。
圖21係表示第2實施方式之半導體裝置之製造方法之概況之剖視圖。圖21(a)~圖21(c)表示圖3及圖4所示之方法之詳情。
圖21(a)與圖10(a)同樣,示出了與電路區域2(電路晶圓W2)貼合之前之陣列區域1(陣列晶圓W1)。圖21(a)中,同樣地,金屬焊墊38之上表面相對於層間絕緣膜14之上表面向下方向凹陷,金屬焊墊41之下表面相對於層間絕緣膜13之下表面向上方向凹陷。即使將陣列區域1與電路區域2貼合,仍會擔心因上述凹陷而導致無法將金屬焊墊41與金屬焊墊38恰當地接合。
圖21(b)與圖10(b)同樣,示出了與電路區域2貼合後且進行用於將金屬焊墊38、41接合之退火之前之陣列區域1。圖21(b)中,同樣地,因上述凹陷而導致金屬焊墊41與金屬焊墊38之間產生了間隙。若不消除該間隙,則會擔心產生金屬焊墊41與金屬焊墊38之接合不良。
圖21(c)與圖10(c)同樣,示出了與電路區域2貼合後且進行了用於將金屬焊墊38、41接合之退火之後之陣列區域1。圖21(c)中,同樣地,金屬焊墊41與金屬焊墊38之間的間隙已消除,金屬焊墊41與金屬焊墊38恰當地接合。此現象緣於因退火引起之金屬焊墊41、38之熱膨脹、以及因退火而體現出來的金屬層39、48之作用。
此處,對本實施方式之金屬層39、48之作用進行說明。
本實施方式之金屬焊墊38、41內之焊墊材料層38b、41b例如為Cu層。另一方面,本實施方式之金屬層39、48例如為Al層或Zn層。因此,金屬層39、48之線膨脹係數變得大於焊墊材料層38b、41b之線膨脹係數。其結果為,於金屬焊墊38、41及金屬層39、41經退火之情形時,金屬層39、48之熱膨脹率變得大於焊墊材料層38b、41b之熱膨脹率,金屬層39、48大幅膨脹。藉此,從金屬層39、48對金屬焊墊41、38施加壓縮應力,金屬焊墊41與金屬焊墊38容易接近。藉此,根據本實施方式,藉由金屬焊墊41、38之熱膨脹、以及金屬層39、48之進一步熱膨脹,可將金屬焊墊41與金屬焊墊38恰當地接合。為了抑制退火對Cu層造成之不良影響,較理想為於400℃以下進行本實施方式之金屬焊墊41、38之退火。
圖22~圖27係表示第2實施方式之半導體裝置之製造方法之詳情之剖視圖。圖22(a)~圖27(b)表示圖21(a)~圖21(c)所示之方法之詳情。
圖22(a)中示出了電路區域2(電路晶圓W2)之一部分。當形成電路區域2時,於基板15之上方形成絕緣膜14a4(圖21(a))。絕緣膜14a4係絕緣膜14a之一部分,例如係使用dTEOS作為原料氣體並藉由CVD而形成。再者,於以下說明中,省略層間絕緣膜14內之絕緣膜14c、14d(圖16)之說明。
繼而,藉由微影法及RIE,於絕緣膜14a4內形成凹部H3(圖22(b))。繼而,於凹部H3內形成金屬層39(圖23(a))。金屬層39例如為Al層或Zn層。本實施方式之金屬層39係藉由利用CVD於凹部H3之內部及外部堆積金屬層39,並利用CMP去除凹部H3外部之金屬層39而形成。
繼而,於絕緣膜14a4及金屬層39上形成絕緣膜14a5(圖23(b))。絕緣膜14a5係絕緣膜14a之一部分,例如使用dTEOS藉由CVD而形成。
繼而,藉由微影法及RIE,於絕緣膜14a4、14a5及金屬層39內形成凹部H4(圖24(a))。其結果為,未圖示之配線層36之上表面露出於凹部H4內。凹部H4以貫通金屬層39之方式形成,被用作供嵌埋介層插塞37之導孔。
繼而,於未圖示之配線層36及絕緣膜14a5上形成介層插塞37之材料(圖24(b))。該材料可與金屬插塞38之材料相同,亦可與金屬插塞38之材料不同。前者之情形時,介層插塞37例如以包含Cu層之方式形成。後者之情形時,介層插塞37例如以包含W(鎢)層之方式形成。繼而,藉由CMP使該材料之表面平坦化(圖25(a))。其結果為,凹部H4外之該材料被去除,於凹部H4內藉由單層金屬鑲嵌而形成介層插塞37。圖25(a)中,介層插塞37與金屬層39相接,被金屬層39呈環狀包圍。進而,圖25(a)中,金屬層39之厚度較介層插塞37之厚度薄,整個金屬層39位於與介層插塞37之一部分相同之高度。
繼而,於絕緣膜14a5及介層插塞37上形成絕緣膜14a6(圖25(b))。絕緣膜14a6係絕緣膜14a之一部分,例如使用dTEOS藉由CVD而形成。繼而,藉由微影法及RIE,於絕緣膜14a6內形成凹部H5(圖26(a))。其結果為,介層插塞37之上表面露出於凹部H5內。凹部H5被用作供嵌埋金屬焊墊38之焊墊槽。
繼而,於介層插塞37及絕緣膜14a5、14a6上形成障壁金屬層38a(圖26(b))。障壁金屬層38a例如為包含Ti元素或Ta元素之金屬層,藉由CVD而形成。
繼而,於介層插塞37及絕緣膜14a5、14a6上隔著障壁金屬層38a而形成焊墊材料層38b(圖27(a))。焊墊材料層38b例如為Cu層,藉由鍍覆法而形成。
繼而,藉由CMP使焊墊材料層38b之表面平坦化(圖27(b))。其結果為,凹部H5外之障壁金屬層38a及焊墊材料層38b被去除,於凹部H5內藉由單層金屬鑲嵌而形成金屬焊墊38。本實施方式之金屬焊墊38形成於與介層插塞37相接但不與金屬層39相接之位置。
圖28(a)中示出了陣列區域1(陣列晶圓W1)之一部分。圖28(a)所示之陣列區域1與電路區域2同樣,係藉由圖22(a)~圖27(b)所示之步驟而形成。其中,基板16、絕緣膜13a內之絕緣膜13a4、13a5、13a6、介層插塞42、障壁金屬層41a、焊墊材料層41b、金屬層48等分別與基板15、絕緣膜14a內之絕緣膜14a1、14a2、14a3、絕緣膜14b、介層插塞37、障壁金屬層38a、焊墊材料層38b、金屬層39等同樣地被處理。再者,圖28(a)中,省略了層間絕緣膜13內之絕緣膜13c、13d(圖16)之圖示。
繼而,以金屬焊墊41配置於金屬焊墊38上且絕緣膜13a1(層間絕緣膜13)配置於絕緣膜14a1(層間絕緣膜14)上之方式,將基板15與基板16貼合(圖28(b))。具體而言,藉由利用機械壓力將層間絕緣膜14與層間絕緣膜13貼合,而將層間絕緣膜14與層間絕緣膜13接著。進而,藉由對金屬焊墊38、41及層間絕緣膜14、13等進行退火,而將金屬焊墊41與金屬焊墊38接合。於上述退火時,金屬層39、48會膨脹,由此可促進金屬焊墊38、41之接合。
然後,藉由CMP使基板15薄膜化,並藉由CMP去除基板16之後,將陣列晶圓W1及電路晶圓W2(參照圖4)切斷成複數個晶片。以此方式來製造圖21等所示之本實施方式之半導體裝置。
再者,利用圖22(a)~圖28(b)所示之方法形成之金屬層39、48亦可具有本實施方式之第1~第4變化例中之任一種形狀。金屬層39之形狀可藉由調整凹部H3之形狀而控制。同樣,金屬層38之形狀亦可藉由調整與凹部H3對應之凹部之形狀而控制。
圖29~圖32係表示第2實施方式之半導體裝置之另一製造方法之詳情之剖視圖。
首先,實施圖22(a)~圖25(b)所示之步驟。但是,省略了與介層插塞37相關之步驟(圖23(a)~圖25(a))。圖29(a)中示出了實施圖25(b)所示之步驟之後之電路區域2(電路晶圓W2)。
繼而,藉由微影法及RIE,於絕緣膜14a6內形成凹部H5(圖29(b))。繼而,藉由微影法及RIE,在位於凹部H5下之絕緣膜14a5、14a4及金屬層39內形成凹部H4(圖30(a))。其結果為,未圖示之配線層36之上表面露出於凹部H4內。
繼而,於未圖示之配線層36及絕緣膜14a5、14a6上形成障壁金屬層38a(圖30(b))。障壁金屬層38a例如為包含Ti元素或Ta元素之金屬層,藉由CVD而形成。
繼而,於未圖示之配線層36及絕緣膜14a5、14a6上隔著障壁金屬層38a而形成焊墊材料層38b(圖31(a))。焊墊材料層38b例如為Cu層,藉由鍍覆法而形成。
繼而,藉由CMP使焊墊材料層38b之表面平坦化(圖31(b))。其結果為,凹部H5、H4外之障壁金屬層38a及焊墊材料層38b被去除,於凹部H5、H4內藉由雙道金屬鑲嵌分別形成金屬焊墊38及介層插塞37。此情形時之介層插塞37與金屬焊墊38同樣,係由障壁金屬層38a及焊墊材料層38b形成。
圖32(a)中示出了陣列區域1(陣列晶圓W1)之一部分。圖32(a)所示之陣列區域1與電路區域2同樣,係藉由圖29(a)~圖31(b)所示之步驟而形成。其中,基板16、絕緣膜13a內之絕緣膜13a4、13a5、13a6、介層插塞42、障壁金屬層41a、焊墊材料層41b、金屬層48等分別與基板15、絕緣膜14a內之絕緣膜14a1、14a2、14a3、絕緣膜14b、介層插塞37、障壁金屬層38a、焊墊材料層38b、金屬層39等同樣地被處理。
繼而,以金屬焊墊41配置於金屬焊墊38上且絕緣膜13a1(層間絕緣膜13)配置於絕緣膜14a1(層間絕緣膜14)上之方式,將基板15與基板16貼合(圖32(b))。具體而言,藉由利用機械壓力將層間絕緣膜14與層間絕緣膜13貼合,而將層間絕緣膜14與層間絕緣膜13接著。進而,藉由對金屬焊墊38、41及層間絕緣膜14、13等進行退火,而將金屬焊墊41與金屬焊墊38接合。於上述退火時,金屬層39、48會膨脹,由此能夠促進金屬焊墊38、41之接合。
然後,藉由CMP使基板15薄膜化,並藉由CMP去除基板16之後,將陣列晶圓W1及電路晶圓W2(參照圖4)切斷成複數個晶片。以此方式來製造圖21等所示之本實施方式之半導體裝置。
再者,利用圖29(a)~圖32(b)所示之方法形成之金屬層39、48亦可具有本實施方式之第1~第4變化例中之任一種形狀。金屬層39之形狀可藉由調整凹部H3之形狀而控制。同樣,金屬層38之形狀亦可藉由調整與凹部H3對應之凹部之形狀而控制。
圖33係用以對第2實施方式之半導體裝置之材料進行說明之曲線圖。
圖33表示矽(Si)、銅(Cu)、鋁(Al)及鋅(Zn)之線膨脹係數之溫度相關性。如圖33所示,相同溫度下之上述物質之線膨脹係數於圖33所示之大致所有溫度區域中,按Zn>Al>Cu>Si之順序變大。藉此,於本實施方式中,藉由將金屬焊墊38、41內之焊墊材料層38b、41b設為Cu層,將金屬層39、48設為Al層或Zn層,可使金屬層39、48之線膨脹係數大於金屬焊墊38、41內之焊墊材料層38b、41b之線膨脹係數。
如上所述,本實施方式之半導體裝置於電路區域2內具備金屬層39,於陣列區域1內具備金屬層48。例如,金屬焊墊38、41包含Cu層,與此相對,金屬層39、48成為Al層或Zn層。藉此,根據本實施方式,可藉由金屬層39、48之作用而將金屬焊墊38與金屬焊墊41恰當地接合。
以上,對若干個實施方式進行了說明,但上述實施方式僅作為例子提出,並不意圖限定發明之範圍。本說明書中所說明之新穎之裝置及方法可以其他各種方式加以實施。又,可於不脫離發明主旨之範圍內對本說明書中所說明之裝置及方法之形態進行各種省略、替換、變更。隨附之申請專利範圍及與其同等之範圍意圖包含發明範圍或主旨中所含之此種形態或變化例。
[相關申請案之引用]
本申請案基於2021年6月16日提出申請之在先日本專利申請案第2021-100408號之優先權而主張優先權利益,藉由引用將其全部內容併入本文中。
1:陣列區域
2:電路區域
11:記憶胞陣列
12:絕緣膜
13:層間絕緣膜
13a:絕緣膜
13a1:絕緣膜
13a2:絕緣膜
13a3:絕緣膜
13a4:絕緣膜
13a5:絕緣膜
13a6:絕緣膜
13b:絕緣膜
13c:絕緣膜
13d:絕緣膜
14:層間絕緣膜
14a:絕緣膜
14a1:絕緣膜
14a2:絕緣膜
14a3:絕緣膜
14a4:絕緣膜
14a5:絕緣膜
14a6:絕緣膜
14b:絕緣膜
14c:絕緣膜
14d:絕緣膜
15:基板
21:階梯構造部
22:接觸插塞
23:字配線層
24:介層插塞
31:電晶體
32:閘極電極
33:接觸插塞
34:配線層
35:配線層
36:配線層
37:介層插塞
38:金屬焊墊
38a:障壁金屬層
38b:焊墊材料層
39:金屬層
41:金屬焊墊
41a:障壁金屬層
41b:焊墊材料層
42:介層插塞
43:配線層
44:配線層
45:介層插塞
46:金屬焊墊
47:鈍化膜
48:金屬層
51:絕緣層
52:阻擋絕緣膜
53:電荷儲存層
54:隧道絕緣膜
55:通道半導體層
56:核心絕緣膜
BL:位元線
CL:柱狀部
H1:凹部
H2:凹部
H3:凹部
H4:凹部
H5:凹部
P:開口部
P1:部分
P2:部分
SL:交界面
SL:源極線
SL1:下部層
SL2:上部層
W1:陣列晶圓
W2:電路晶圓
WL:字元線
圖1係表示第1實施方式之半導體裝置之構造之剖視圖。 圖2係表示第1實施方式之柱狀部之構造之剖視圖。 圖3係表示第1實施方式之半導體裝置之製造方法之剖視圖(1/2)。 圖4係表示第1實施方式之半導體裝置之製造方法之剖視圖(2/2)。 圖5(a)~(c)係表示第1實施方式之半導體裝置之構造之剖視圖。 圖6(a)、(b)係表示第1實施方式之半導體裝置之構造之2個例子之剖視圖。 圖7(a)~(c)係表示第1實施方式之第1變化例之半導體裝置之構造之剖視圖。 圖8(a)~(c)係表示第1實施方式之第2變化例之半導體裝置之構造之剖視圖。 圖9(a)~(c)係表示第1實施方式之第3變化例之半導體裝置之構造之剖視圖。 圖10(a)~(c)係表示第1實施方式之半導體裝置之製造方法之概況之剖視圖。 圖11(a)、(b)係表示第1實施方式之半導體裝置之製造方法之詳情之剖視圖(1/5)。 圖12(a)、(b)係表示第1實施方式之半導體裝置之製造方法之詳情之剖視圖(2/5)。 圖13(a)、(b)係表示第1實施方式之半導體裝置之製造方法之詳情之剖視圖(3/5)。 圖14(a)、(b)係表示第1實施方式之半導體裝置之製造方法之詳情之剖視圖(4/5)。 圖15(a)、(b)係表示第1實施方式之半導體裝置之製造方法之詳情之剖視圖(5/5)。 圖16係表示第2實施方式之半導體裝置之構造之剖視圖。 圖17係表示第2實施方式之第1變化例之半導體裝置之構造之剖視圖。 圖18係表示第2實施方式之第2變化例之半導體裝置之構造之剖視圖。 圖19係表示第2實施方式之第3變化例之半導體裝置之構造之剖視圖。 圖20係表示第2實施方式之第4變化例之半導體裝置之構造之剖視圖。 圖21(a)~(c)係表示第2實施方式之半導體裝置之製造方法之概況之剖視圖。 圖22(a)、(b)係表示第2實施方式之半導體裝置之製造方法之詳情之剖視圖(1/7)。 圖23(a)、(b)係表示第2實施方式之半導體裝置之製造方法之詳情之剖視圖(2/7)。 圖24(a)、(b)係表示第2實施方式之半導體裝置之製造方法之詳情之剖視圖(3/7)。 圖25(a)、(b)係表示第2實施方式之半導體裝置之製造方法之詳情之剖視圖(4/7)。 圖26(a)、(b)係表示第2實施方式之半導體裝置之製造方法之詳情之剖視圖(5/7)。 圖27(a)、(b)係表示第2實施方式之半導體裝置之製造方法之詳情之剖視圖(6/7)。 圖28(a)、(b)係表示第2實施方式之半導體裝置之製造方法之詳情之剖視圖(7/7)。 圖29(a)、(b)係表示第2實施方式之半導體裝置之另一製造方法之詳情之剖視圖(1/4)。 圖30(a)、(b)係表示第2實施方式之半導體裝置之另一製造方法之詳情之剖視圖(2/4)。 圖31(a)、(b)係表示第2實施方式之半導體裝置之另一製造方法之詳情之剖視圖(3/4)。 圖32(a)、(b)係表示第2實施方式之半導體裝置之另一製造方法之詳情之剖視圖(4/4)。 圖33係用以對第2實施方式之半導體裝置之材料進行說明之曲線圖。
1:陣列區域
2:電路區域
13:層間絕緣膜
13a:絕緣膜
13b:絕緣膜
14:層間絕緣膜
14a:絕緣膜
14b:絕緣膜
37:介層插塞
38:金屬焊墊
38a:障壁金屬層
38b:焊墊材料層
41:金屬焊墊
41a:障壁金屬層
41b:焊墊材料層
42:介層插塞
P1:部分
P2:部分
Claims (20)
- 一種半導體裝置,其具備第1絕緣膜、設置於上述第1絕緣膜內之第1焊墊、設置於上述第1絕緣膜上之第2絕緣膜、及在上述第2絕緣膜內設置於上述第1焊墊上之第2焊墊;上述第1絕緣膜包含第1膜及第2膜,該第1膜與上述第1焊墊及上述第2絕緣膜相接,該第2膜與上述第1焊墊及上述第2絕緣膜隔開間隔而設,且具有設置於與上述第1焊墊之至少一部分相同高度之部分;且/或,上述第2絕緣膜包含第3膜及第4膜,該第3膜與上述第2焊墊及上述第1絕緣膜相接,該第4膜與上述第2焊墊及上述第1絕緣膜隔開間隔而設,且具有設置於與上述第2焊墊之至少一部分相同高度之部分。
- 如請求項1之半導體裝置,其中上述第1膜與上述第2膜包含矽及氧,且/或,上述第3膜與上述第4膜包含矽及氧。
- 如請求項1或2之半導體裝置,其中上述第2膜具有較上述第1膜高之氮原子濃度,且/或,上述第4膜具有較上述第3膜高之氮原子濃度。
- 如請求項1之半導體裝置,其中上述第1膜包含設置於上述第1焊墊之側面與上述第2膜之側面之間的第1部分,且/或,上述第3膜包含設置於上述第2焊墊之側面與上述第4膜之側面之間的第2部分。
- 如請求項4之半導體裝置,其中上述第1部分具有包圍上述第1焊墊之環狀之平面形狀,且/或,上述第2部分具有包圍上述第2焊墊之環狀之平面形狀。
- 如請求項5之半導體裝置,其中上述第1部分具有包含複數個六邊形之環狀之平面形狀,且/或,上述第2部分具有包含複數個六邊形之環狀之平面形狀。
- 一種半導體裝置之製造方法,其包括如下步驟:於第1基板上形成第1絕緣膜;於上述第1絕緣膜內形成第1焊墊;於第2基板上形成第2絕緣膜;於上述第2絕緣膜內形成第2焊墊;於上述第1絕緣膜上配置上述第2絕緣膜,於上述第1焊墊上配置上述第2焊墊,以此方式將上述第1基板與上述第2基板貼合;且,上述第1絕緣膜形成為包含第1膜及第2膜,該第1膜與上述第1焊墊及上述第2絕緣膜相接,該第2膜與上述第1焊墊及上述第2絕緣膜隔開間隔而設,且具有設置於與上述第1焊墊之至少一部分相同高度之部分;且/或,上述第2絕緣膜形成為包含第3膜及第4膜,該第3膜與上述第2焊墊及上述第1絕緣膜相接,該第4膜與上述第2焊墊及上述第1絕緣膜隔開間隔而設,且具有設置於與上述第2焊墊之至少一部分相同高度之部分。
- 如請求項7之半導體裝置之製造方法,其中上述第2膜於上述貼合後被加熱而收縮,且/或,上述第4膜於上述貼合後被加熱而收縮。
- 如請求項7或8之半導體裝置之製造方法,其中上述第2膜之厚度因上述收縮而減少大於9%且25%以下之量,且/或,上述第4膜之厚度因上述收縮而減少大於9%且25%以下之量。
- 如請求項7之半導體裝置之製造方法,其中上述第2膜包含聚矽氮烷,且/或,上述第4膜包含聚矽氮烷。
- 一種半導體裝置,其具備第1絕緣膜、設置於上述第1絕緣膜內之第1插塞、在上述第1絕緣膜內設置於上述第1插塞上之第1焊墊、設置於上述第1絕緣膜上之第2絕緣膜、在上述第2絕緣膜內設置於上述第1焊墊上之第2焊墊、及在上述第2絕緣膜內設置於上述第2焊墊上之第2插塞,且進而具備第1層且/或第2層,該第1層具有較上述第1焊墊大之線膨脹係數,且具有於上述第1絕緣膜內設置於與上述第1插塞之至少一部分相同高度之部分,該第2層具有較上述第2焊墊大之線膨脹係數,且具有在上述第2絕緣膜內設置於與上述第2插塞之至少一部分相同高度之部分。
- 如請求項11之半導體裝置,其中上述第1層包含第1金屬層,且/或,上述第2層包含第2金屬層。
- 如請求項11或12之半導體裝置,其中上述第1焊墊包含銅,上述第1層包含鋁或鋅,且/或,上述第2焊墊包含銅,上述第2層包含鋁或鋅。
- 如請求項11之半導體裝置,其中上述第1層之厚度為上述第1焊墊之厚度之5%以上且30%以下,且/或,上述第2層之厚度為上述第2焊墊之厚度之5%以上且30%以下。
- 如請求項11之半導體裝置,其中上述第1層與上述第1插塞相接,且/或,上述第2層與上述第2插塞相接。
- 如請求項11之半導體裝置,其中上述第1層與上述第1插塞隔開間隔而設,且/或,上述第2層與上述第2插塞隔開間隔而設。
- 如請求項11之半導體裝置,其中上述第1層與上述第1焊墊相接,且/或,上述第2層與上述第2焊墊相接。
- 如請求項11之半導體裝置,其中上述第1層與上述第1焊墊隔開間隔而設,且/或,上述第2層與上述第2焊墊隔開間隔而設。
- 一種半導體裝置之製造方法,其包括如下步驟:於第1基板上形成第1絕緣膜;於上述第1絕緣膜內形成第1插塞;於上述第1絕緣膜內在上述第1插塞上形成第1焊墊;於第2基板上形成第2絕緣膜;於上述第2絕緣膜內形成第2插塞;於上述第2絕緣膜內在上述第2插塞上形成第2焊墊;於上述第1絕緣膜上配置上述第2絕緣膜,於上述第1焊墊上配置上述第2焊墊,以此方式將上述第1基板與上述第2基板貼合;且進而包括如下步驟:於上述第1絕緣膜內形成第1層,該第1層具有較上述第1焊墊大之線膨脹係數,且具有設置於與上述第1插塞之至少一部分相同高度之部分;且/或,於上述第2絕緣膜內形成第2層,該第2層具有較上述第2焊墊大之線膨脹係數,且具有設置於與上述第2插塞之至少一部分相同高度之部分。
- 如請求項19之半導體裝置之製造方法,其中上述第1層係於形成上述第1插塞之前形成,且/或,上述第2層係於形成上述第2插塞之前形成。
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US20220406739A1 (en) | 2022-12-22 |
US11862586B2 (en) | 2024-01-02 |
CN115483222A (zh) | 2022-12-16 |
JP2022191901A (ja) | 2022-12-28 |
TW202315066A (zh) | 2023-04-01 |
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