TWI720527B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI720527B
TWI720527B TW108123221A TW108123221A TWI720527B TW I720527 B TWI720527 B TW I720527B TW 108123221 A TW108123221 A TW 108123221A TW 108123221 A TW108123221 A TW 108123221A TW I720527 B TWI720527 B TW I720527B
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metal layer
layer
wiring
semiconductor device
pad
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TW202036736A (zh
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籏崎晃次
加藤敦史
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日商東芝記憶體股份有限公司
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Abstract

有關一實施形態之半導體裝置係具備:具有第1半導體基板，和設置於第1半導體基板之第1半導體元件，和連接於第1半導體元件之第1配線層，和連接於第1配線層之第1墊片的第1晶片，與具有第2半導體基板，和設置於第2半導體基板之第2半導體元件，和連接於第2半導體元件之第2配線層，和連接於第2配線層之同時，接合於第1墊片之第2墊片的第2晶片。第1墊片及第2墊片之至少一方則具有:與另一方的墊片加以接合之第1金屬層，和熱膨脹率較第1金屬層為高之第2金屬層，和設置於第1金屬層與第2金屬層之間的阻障金屬層。

Description

半導體裝置及其製造方法
本發明之實施形態係有關半導體裝置及其製造方法。
在貼合半導體基板彼此之貼合技術中，例如，貼合形成有記憶體等之半導體元件的半導體基板，和形成有其半導體元件之周邊電路之半導體基板。此時，接合各基板之墊片。 [先前技術文獻] [專利文獻] [專利文獻1] 日本特開2013-229415號公報
[發明欲解決之課題] 在上述之貼合技術中，經由使含於各墊片之金屬熱膨脹而使其接合。但其金屬的熱膨脹量當不充分時，產生有貼合不良。 本發明之實施形態係提供:可迴避貼合不良之半導體裝置及其製造方法。 [為了解決課題之手段] 有關一實施形態之半導體裝置係具備:具有第1半導體基板，和設置於第1半導體基板之第1半導體元件，和連接於第1半導體元件之第1配線層，和連接於第1配線層之第1墊片的第1晶片，與具有第2半導體基板，和設置於第2半導體基板之第2半導體元件，和連接於第2半導體元件之第2配線層，和連接於第2配線層之同時，接合於第1墊片之第2墊片的第2晶片。第1墊片及第2墊片之至少一方則具有:與另一方的墊片加以接合之第1金屬層，和熱膨脹率較第1金屬層為高之第2金屬層，和設置於第1金屬層與第2金屬層之間的阻障金屬層。 [發明效果] 如根據一實施形態，成為可迴避貼合不良者。
以下，將本發明之實施形態，參照圖面加以說明。本實施形態係未限定本發明者。 圖1係顯示有關一實施形態的半導體裝置之要部的構造的剖面圖。 有關本實施形態之半導體裝置係貼合記憶體晶片1(第1晶片)和電路晶片2(第2晶片)之3次元型半導體記憶體。首先，對記憶體晶片1之構成加以說明。記憶體晶片1係具有:半導體基板10，和絕緣層11，和半導體元件12(第1半導體元件)，和接觸塞13a~13c，和配線層14a，14b，和墊片15(第1墊片)，和層間絕緣膜16。 半導體基板10係例如為矽基板。對於半導體基板10上係設置有絕緣層11。絕緣層11係例如，氧化矽層或氮化矽層。對於絕緣層11上係設置有半導體元件12。 圖2係擴大半導體元件12之一部分的剖面圖。如圖2所示，半導體元件12係具有:層積體120及記憶體膜130。 在層積體120中，複數之電極層121與複數之絕緣層122則交互層積於正交於半導體基板10之Z方向。各電極層121係例如，鎢等之金屬層，而為記憶體膜130之字元線。各絕緣膜122係例如為氧化矽層。層積體120的端部係如圖1所示，形成為階梯狀。在此階梯狀的端部中，各電極層111係藉由接觸塞13a而連接於配線層14a。 記憶體膜130係如圖2所示，將層積體120貫通於Z方向，具備嵌段絕緣膜131，和電荷蓄積層132，和穿隧絕緣膜133和，通道層134，核心絕緣膜135。電荷蓄積層132係例如為氮化矽膜，而於電極層121及絕緣層122之側面，藉由嵌段絕緣膜131而加以形成。嵌段絕緣膜131，穿隧絕緣膜133及核心絕緣膜135係例如為氧化矽膜。通道層134係例如為矽層，而於電荷蓄積層132之側面，藉由穿隧絕緣膜133而加以形成。通道層134係藉由接觸塞13b而連接於配線層14a(參照圖1)。 如圖1所示，配線層14a係藉由接觸塞13c而連接於墊片15或配線層14b。對於接觸塞13a~13c及配線層14a，14b的材料係例如，可使用鋁或銅者。對於在接觸塞13a~13c與配線層14a，14b之間，金屬材料為不同之情況，係為了防止金屬擴散，於此等之間形成阻障金屬層者為佳。 然而，在圖1中，配線層14、14b之一部分則簡略化而一體地顯示，但實際上係以經由層間絕緣膜16所絕緣分離之複數的配線而加以構成。 墊片15係具有:金屬層151(第1金屬層)，和阻障金屬層152，和金屬層153(第2金屬層)。金屬層151係接合於電路晶片2。阻障金屬層152係設置於金屬層151與金屬層153之間。經由阻障金屬層152而可防止金屬層151之擴散者。金屬層153係設置於與配線層14b相同的層。 在本實施形態中，金屬層151的材料係為銅，而金屬層153的材料係為鋁，阻障金屬層152的材料係為氮化鈦。然而，對於金屬層151及金屬層153之各材料係金屬層153之熱膨脹率如為滿足較金屬層151之熱膨脹率為大的關係，未特別加以限制。 接著，對於電路晶片2之構成加以說明。電路晶片2係具有:如圖1所示之基板20，和半導體元件21(第2半導體元件)，和接觸塞22a～22e，和配線層23a～23c，和墊片24(第2墊片)，和層間絕緣膜25。 基板20係例如為矽基板。對於基板20上係設置有為了驅動記憶體晶片1之半導體元件21。 半導體元件21係具有閘極電極21a，閘極絕緣膜21b，及擴散層21c之MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)。擴散層21c係源極範圍或汲極範圍。閘極電極21a係設置於閘極絕緣膜21b上，藉由接觸塞22a而連接於配線層23a。擴散層21c係藉由接觸塞22b而連接於配線層23a。 配線層23a係藉由接觸塞22c連接於配線層23b。配線層23b藉由接觸塞22d連接於配線層23c。配線層23c係藉由接觸塞22e連接於墊片24。 在本實施形態中，對於接觸塞22a~22e及配線層23a~ 23c之材料係例如，可使用鋁或銅等者。對於在接觸塞22a~22e與配線層23a~23c之間，金屬材料為不同之情況，係為了防止金屬擴散，於此等之間形成阻障金屬層者為佳。 然而，在圖1中，配線層23a~23c之一部分則簡略化而一體地顯示，但實際上係以經由層間絕緣膜25所絕緣分離之複數的配線而加以構成。 墊片24係具有:金屬層241(第1金屬層)，和阻障金屬層242，和金屬層243(第2金屬層)。金屬層241係接合於記憶體晶片1之金屬層151。阻障金屬層242係設置於金屬層241與金屬層243之間。經由阻障金屬層242而可防止金屬層241之擴散者。金屬層243係連接於接觸塞22e。然而，圖1雖未圖示，但電路晶片2係具有位置於與金屬層243相同的層之配線層亦可。 在本實施形態中，金屬層241的材料係為銅，而金屬層243的材料係為鋁，阻障金屬層242的材料係為氮化鈦。然而，對於金屬層241及金屬層243之各材料係金屬層243之熱膨脹率如為滿足較金屬層241之熱膨脹率為大的關係，未特別加以限制。 以下，對於如上述所構成之半導體裝置之製造工程的一部分加以說明。在此係參照圖3~圖8，對於墊片15之製造工程加以說明。然而，墊片24亦可採用與墊片15相同之製造工程者。 首先，如圖3所示，於被覆配線層14a之層間絕緣膜16a，形成貫孔部100。貫孔部100係到達至配線層14a。 接著，如圖4所示，於層間絕緣膜15a之上面，形成金屬膜200，更於此金屬膜200上形成阻障金屬層201。金屬膜200之材料係為鋁，而鋁係亦埋入於貫孔部100內。埋入於貫孔部100內的鋁則為接觸塞13c。 接著，如圖5所示，例如經由RIE(Reactive Ion Etching)而蝕刻金屬膜200及阻障金屬層201。經由此，具有相同厚度t1之金屬層153及配線層14b則同時圖案化於相同的層。同時，對於金屬層153及配線層14b上係亦圖案化阻障金屬層152。然而，屬於配線層14b之配線的一部分係例如，可作為結合區而使用者。此結合區係與為了連接電路晶片2於其他的安裝基板等之銲接線(不圖示)加以接合。 接著，如圖6所示，層間絕緣膜16b則呈被覆金屬層153，配線層14b，阻障金屬層152地成膜於層間絕緣膜16a上。層間絕緣膜16b係例如，可經由CVD(Chemical Vapor Deposition)及CMP(Chemical Mechanical Polishing)而形成者。 接著，如圖7所示，形成孔部101於層間絕緣膜16b。在本實施形態中，孔部101之開口部的面積係較金屬層153之平面積為窄。另外，孔部101之深度d係與金屬層153之厚度t1相同。 接著，如圖8所示，經由埋入銅於孔部101之時，形成金屬層151。如上述，孔部101之深度d係與金屬層153之厚度t1相同之故，金屬層151之厚度t2係成為與金屬層153之厚度t1相同。之後，使記憶體晶片1之上下反轉(180度旋轉)而貼合於電路晶片2。 圖9係擴大記憶體晶片1與電路晶片2之貼合處的一部分之剖面圖。如圖9所示，墊片15之金屬層151與墊片24之金屬層241則接合著。墊片15係具有熱膨脹率較金屬層151為大之金屬層153，而墊片24係具有熱膨脹率較金屬層241為大之金屬層243。 圖10係顯示墊片接合之退火溫度與熱膨脹量的關係圖。在圖10中，實線L1係顯示有關本實施形態之墊片15的熱膨脹量。具體而言，金屬層151之材料為銅，而金屬層153之材料為鋁，各層的厚度為600nm。另一方面，點線L2係顯示有關比較例之墊片的熱膨脹率。此墊片的材料係為銅，厚度係1200nm。 如圖10所示，在各退火溫度中，有關本實施形態之墊片15的熱膨脹量係較有關比較例之墊片的熱膨脹量為大。因此，在墊片15與墊片24之接合時，退火溫度即使為低，經由金屬層153及金屬層243之熱膨脹，亦可補足金屬層151及金屬層241之熱膨脹的不足。 隨之，如根據本實施形態，因可無間隙接合金屬層151及金屬層241之故，成為可迴避貼合不良者。 另外，在本實施形態中，金屬層151與金屬層153係未藉由接觸塞而加以連接。同樣地，金屬層241與金屬層243亦未藉由接觸塞而加以連接。因此，對於退火溫度為高之情況，亦可迴避含於上述接觸塞之金屬材料(銅)則抽出至金屬層151，241側之不良情況的發生。 然而，在本實施形態中，墊片15及墊片24之雙方則具有熱膨脹率不同之2個金屬層。但墊片15或墊片24則亦可具有上述之2個金屬層。即，墊片15及墊片24之至少一方則如具有:與另一方的墊片加以接合之第1金屬層，和熱膨脹率較前述第1金屬層為高之第2金屬層，和設置於前述第1金屬層與前述第2金屬層之間的阻障金屬層即可。此情況，第2金屬層則經由補足第1金屬層之熱膨脹量的不足之時，可迴避墊片15與墊片24之接合不良者。 以上，雖已說明過幾個實施形態，但此等實施形態係作為例而提示之構成，未特意限定發明之範圍者。在本說明書所說明之新穎的裝置，方法，程序，及系統係可在其他種種之形態實施者。另外，對於在本說明書所說明之新穎的裝置，方法，程序，及系統的形態而言，在不脫離發明之內容的範圍內，可進行種種之省略，置換，變更者。附上之申請專利範圍及對於此等均等的範圍係特意呈包含於發明的範圍或內容之如此的形態或變形例。
1:記憶體晶片 2:電路晶片 10:半導體基板 11:絕緣層 12:半導體元件 13a～13c:接觸塞 14a、14b:配線層 15，24:墊片 16:層間絕緣膜 100:貫孔部 130:記憶體膜 131:嵌段絕緣膜 120:層積體 132:電荷蓄積層 133:穿隧絕緣膜 134:通道層 135:核心絕緣膜 151，153:金屬層 152:阻障金屬層 21a:閘極電極 21b:閘極絕緣膜 21c:擴散層 241，243:金屬層 242:阻障金屬層
圖1係顯示有關一實施形態的半導體裝置之要部的構造的剖面圖。 圖2係擴大半導體元件之一部分的剖面圖。 圖3係顯示貫孔部的形成工程的剖面圖。 圖4係顯示金屬膜及阻障金屬層之形成工程的剖面圖。 圖5係顯示金屬膜之蝕刻工程的剖面圖。 圖6係顯示層間絕緣膜的成膜工程之剖面圖。 圖7係顯示貫孔部的形成工程的剖面圖。 圖8係顯示金屬層的形成工程之剖面圖。 圖9係擴大記憶體晶片與電路晶片之貼合處的一部分之剖面圖。 圖10係顯示墊片接合之退火溫度與熱膨脹量的關係圖。
1:記憶體晶片
2:電路晶片
10:半導體基板
11:絕緣層
12:半導體元件
13a~13c:接觸塞
14a、14b:配線層
15，24:墊片
16:層間絕緣膜
20:基板
21:半導體元件
21a:閘極電極
21b:閘極絕緣膜
21c:擴散層
22a~22e:接觸塞
23a~23c:和配線層
24:墊片
25:層間絕緣膜
151，153:金屬層
152:阻障金屬層
241，243:金屬層
242:阻障金屬層

Claims (14)

  1. 一種半導體裝置，其特徵為具備：具有第1半導體基板，和設置於前述第1半導體基板之第1半導體元件，和連接於第1半導體元件之第1配線層，和連接於前述第1配線層之第1墊片的第1晶片，與具有第2半導體基板，和設置於前述第2半導體基板之第2半導體元件，和連接於前述第2半導體元件之第2配線層，和連接於前述第2配線層之同時，接合於前述第1墊片之第2墊片的第2晶片，前述第1墊片及前述第2墊片之至少一方則具有：與另一方的墊片加以接合之第1金屬層，和熱膨脹率較前述第1金屬層為高之第2金屬層，和設置於前述第1金屬層與前述第2金屬層之間的阻障金屬層；前述第1金屬層、前述第2金屬層、及前述阻障金屬層係各別設於層間絕緣膜中。
  2. 如申請專利範圍第1項記載之半導體裝置，其中，前述第2金屬層之平面積則較前述第1金屬層之平面積為大。
  3. 如申請專利範圍第1項記載之半導體裝置，其中，前述第2金屬層則含有鋁。
  4. 如申請專利範圍第1項記載之半導體裝置，其中，前 述第1金屬層則含有銅。
  5. 如申請專利範圍第1項記載之半導體裝置，其中，於前述第1配線層或前述第2配線層與前述第2金屬層之間，更具備與前述第2金屬層相同之材料的接觸塞。
  6. 如申請專利範圍第1項記載之半導體裝置，其中，前述第2金屬層係設置於與屬於前述第1配線層或前述第2配線層之配線相同的層。
  7. 如申請專利範圍第1項記載之半導體裝置，其中，前述第1金屬層之厚度則與前述第2金屬層之厚度相同。
  8. 一種半導體裝置之製造方法，係將第1半導體基板，和設置於前述第1半導體基板之第1半導體元件，和連接於第1半導體元件之第1配線層，和連接於前述第1配線層之第1墊片，形成於第1晶片，形成第2半導體基板，和設置於前述第2半導體基板之第2半導體元件，和連接於前述第2半導體元件之第2配線層，和連接於前述第2配線層之第2墊片，接合前述第1墊片，和前述第2墊片之半導體裝置之製造方法，其特徵為於前述第1墊片及前述第2墊片之至少一方，將與另一方的墊片加以接合之第1金屬層，和熱膨脹率較前述第1金 屬層為高之第2金屬層，和設置於前述第1金屬層與前述第2金屬層之間的阻障金屬層各形成於層間絕緣膜中。
  9. 如申請專利範圍第8項記載之半導體裝置之製造方法，其中，於前述第2金屬層上，形成具有較前述第2金屬層之平面積為窄之開口部的面積之孔部，再於前述孔部內，形成前述第1金屬層。
  10. 如申請專利範圍第8項記載之半導體裝置之製造方法，其中，使用鋁而形成前述第2金屬層。
  11. 如申請專利範圍第8項記載之半導體裝置之製造方法，其中，使用銅而形成前述第1金屬層。
  12. 如申請專利範圍第8項記載之半導體裝置之製造方法，其中，於前述第1配線層或前述第2配線層與前述第2金屬層之間，形成與前述第2金屬層相同之材料的接觸塞。
  13. 如申請專利範圍第8項記載之半導體裝置之製造方法，其中，於與屬於前述第1配線層或前述第2配線層之配線相同的層，將前述第2金屬層，與前述配線同時形成。
  14. 如申請專利範圍第8項記載之半導體裝置之製造方 法，其中，相同地形成前述第1金屬層之厚度與前述第2金屬層之厚度。
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