JP6291555B2 - 封止表面に至るワイヤボンドを有するパッケージ・オン・パッケージアセンブリ - Google Patents
封止表面に至るワイヤボンドを有するパッケージ・オン・パッケージアセンブリ Download PDFInfo
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- JP6291555B2 JP6291555B2 JP2016207566A JP2016207566A JP6291555B2 JP 6291555 B2 JP6291555 B2 JP 6291555B2 JP 2016207566 A JP2016207566 A JP 2016207566A JP 2016207566 A JP2016207566 A JP 2016207566A JP 6291555 B2 JP6291555 B2 JP 6291555B2
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- General Physics & Mathematics (AREA)
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Description
本願は、2011年5月3日に出願された韓国特許出願第10−2011−0041843号の優先権を主張するものであり、その開示内容は、参照することによって、ここに含まれるものとする。
なお、原出願の特許請求の範囲は、以下の通りである。
[請求項1]
超小型電子パッケージにおいて、
第1の領域および第2の領域を有する基板であって、第1の表面および前記第1の表面から遠く離れた第2の表面を有している、基板と、
前記第1の領域内において前記第1の表面の上に重なる少なくとも1つの超小型電子素子と、
前記第2の領域内において前記基板の前記第1の表面および前記第2の表面の少なくとも1つに露出した導電要素であって、前記導電要素の少なくともいくつかは、前記少なくとも1つの超小型電子素子に電気的に接続されている、導電要素と、
前記導電要素のそれぞれに接合された基部と、前記基板から遠く離れてかつ前記基部から遠く離れた端面とを有する複数のワイヤボンドであって、各ワイヤボンドは、その前記基部と前記端面との間に延在する縁面を画定しており、第1のワイヤボンドは、第1の信号電位を送るように構成されており、第2のワイヤボンドは、前記第1の信号電位と異なる第2の信号電位を同時に送るように構成されている、複数のワイヤボンドと、
前記第1または第2の表面の少なくとも1つから延在する誘電体封止層であって、前記封止層は、前記ワイヤボンドが前記封止層によって互いに分離されるように前記ワイヤボンド間の空間を充填しており、前記封止層は、前記基板の少なくとも前記第2の領域の上に重なっており、前記ワイヤボンドの未封止部分は、少なくとも前記封止層によって覆われていない前記ワイヤボンドの前記端面の一部によって画定されている、誘電体封止層と、
を備えている、ことを特徴とする超小型電子パッケージ。
[請求項2]
前記基板は、リードフレームであり、前記導電要素は、前記リードフレームのリードである、ことを特徴とする請求項1に記載の超小型電子パッケージ。
[請求項3]
前記ワイヤボンドの前記未封止部分は、前記ワイヤボンドの前記端面と、前記封止層によって覆われていない前記端面に隣接する前記縁面の一部と、によって画定されている、ことを特徴とする請求項1に記載の超小型電子パッケージ。
[請求項4]
前記ワイヤボンドの前記未封止部分の少なくともいくつかに接触する酸化保護層をさらに備えている、ことを特徴とする請求項3に記載の超小型電子パッケージ。
[請求項5]
前記ワイヤボンドの少なくとも1つの前記端面に隣接する少なくとも一部は、前記封止層の表面と実質的に直交している、ことを特徴とする請求項1に記載の超小型電子パッケージ。
[請求項6]
前記導電要素は、第1の導電要素であり、
前記超小型電子パッケージは、前記ワイヤボンドの前記未封止部分に電気的に接続された複数の第2の導電要素をさらに備えており、
前記第2の導電要素は、前記第1の導電要素と接触していない、ことを特徴とする請求項1に記載の超小型電子パッケージ。
[請求項7]
前記第2の導電要素は、前記第1のワイヤボンドの少なくともいくつかの前記端面に接合された複数のスタッドバンプを備えている、ことを特徴とする請求項6に記載の超小型電子パッケージ。
[請求項8]
前記ワイヤボンドの少なくとも1つは、その前記基部と前記未封止部分との間で実質的に直線に沿って延在しており、前記実質的な直線は、前記基板の前記第1の表面に対して90°未満の角度をなしている、ことを特徴とする請求項1に記載の超小型電子パッケージ。
[請求項9]
前記ワイヤボンドの少なくとも1つの前記縁面は、前記端面に隣接する第1の部分と、前記端面から前記第1の部分によって分離された第2の部分とを有しており、
前記第1の部分は、前記第2の部分が延在する方向から離れる方向に延在している、ことを特徴とする請求項1に記載の超小型電子パッケージ。
[請求項10]
超小型電子パッケージにおいて、
第1の領域および第2の領域を有する基板であって、第1の表面および前記第1の表面から遠く離れた第2の表面を有している、基板と、
前記第1の領域内において前記第1の表面の上に重なる少なくとも1つの超小型電子素子と、
前記第2の領域内において前記基板の前記第1の表面および前記第2の表面の少なくとも1つに露出した導電要素であって、前記導電要素の少なくともいくつかは、前記少なくとも1つの超小型電子素子に電気的に接続されている、導電要素と、
前記導電要素のそれぞれに接合された基部と、前記基板から遠く離れてかつ前記基部から遠く離れた端面とを有する複数のワイヤボンドであって、各ワイヤボンドは、その前記基部と前記端面との間に延在する縁面を画定しており、第1の前記ワイヤボンドは、第1の信号電位を送るように構成されており、第2の前記ワイヤボンドは、前記第1の信号電位と異なる第2の信号電位を同時に送るように構成されている、複数のワイヤボンドと、
前記第1または第2の表面の少なくとも1つから延在する誘電体封止層であって、前記封止層は、前記ワイヤボンドが前記封止層によって互いに分離されるように、前記ワイヤボンド間の空間を充填しており、前記封止層は、前記基板の少なくとも前記第2の領域の上に重なっており、前記ワイヤボンドの未封止部分は、少なくとも前記封止層によって覆われていない前記ワイヤボンドの前記端面に隣接する前記縁面の一部によって画定されている、誘電体封止層と、
を備えている、ことを特徴とする超小型電子パッケージ。
[請求項11]
前記未封止部分の少なくとも1つは、前記封止層によって覆われていない前記端面の少なくとも一部によってさらに画定されている、ことを特徴とする請求項10に記載の超小型電子パッケージ。
[請求項12]
前記封止層によって覆われていない前記縁面の前記一部は、前記封止層の前記表面と実質的に平行の方向に延在する最長寸法を有している、ことを特徴とする請求項10に記載の超小型電子パッケージ。
[請求項13]
前記封止層によって覆われず、前記封止層の前記表面と実質的に平行に延在する前記縁面の前記一部の長さは、前記ワイヤボンドの断面幅よりも大きくなっている、ことを特徴とする請求項12に記載の超小型電子パッケージ。
[請求項14]
前記封止層は、前記ワイヤボンドを形成した後に、誘電体材料を前記第1の表面上に堆積させ、前記堆積した誘電体材料を硬化させることによって、前記基板上に形成された一体化層である、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項15]
前記一体化封止層は、前記誘電体材料を含んでいる、ことを特徴とする請求項11に記載の超小型電子パッケージ。
[請求項16]
前記基板の前記第1の表面は、第1および第2の横方向に延在しており、
各横方向は、前記第1および第2の表面間において前記基板の厚みの方向を横断しており、
前記ワイヤボンドの少なくとも1つの前記未封止部分は、前記少なくとも1つのワイヤボンドが接合された前記導電要素から前記横方向の少なくとも1つにおいて変位している、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項17]
前記ワイヤボンドの少なくとも1つは、その前記基部と前記端面との間に実質的に湾曲した部分を備えている、ことを特徴とする請求項16に記載の超小型電子パッケージ。
[請求項18]
前記少なくとも1つのワイヤボンドの前記未封止部分は、前記超小型電子素子の主面の上に重なっている、ことを特徴とする請求項16に記載の超小型電子パッケージ。
[請求項19]
前記ワイヤボンドの少なくとも1つの前記未封止部分に接合された半田ボールをさらに備えている、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項20]
前記封止層は、少なくとも1つの表面を備えており、前記ワイヤボンドの前記未封止部分は、前記少なくとも1つの表面で覆われていない、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項21]
前記少なくとも1つの表面は、前記基板の前記第1の表面と実質的に平行の主面を含んでおり、
前記ワイヤボンドの少なくとも1つの前記未封止部分は、前記主面において前記封止層によって覆われていない、ことを特徴とする請求項20に記載の超小型電子パッケージ。
[請求項22]
少なくとも1つのワイヤボンドの前記未封止部分は、前記主面と実質的に同一平面をなしている、ことを特徴とする請求項21に記載の超小型電子パッケージ。
[請求項23]
少なくとも1つのワイヤボンドの前記未封止部分は、前記主面の上方に延在している、ことを特徴とする請求項21に記載の超小型電子パッケージ。
[請求項24]
前記少なくとも1つの表面は、前記基板の前記第1の表面から第1の距離を隔てた主面と、前記基板の前記第1の表面から前記第1の距離よりも短い第2の距離を隔てた凹面とを備えており、
前記ワイヤボンドの少なくとも1つの前記未封止部分は、前記凹面において前記封止層によって覆われていない、ことを特徴とする請求項20に記載の超小型電子パッケージ。
[請求項25]
前記少なくとも1つの表面は、前記基板の第1の表面対して大きな角度で離れる方に延在する側面を含んでおり、
少なくとも1つのワイヤボンドの未封止部分は、前記側面において前記封止層によって覆われていない、ことを特徴とする請求項20に記載の超小型電子パッケージ。
[請求項26]
前記封止層は、前記封止層の表面から前記基板に向かって延在するように形成された空洞を有しており、
前記ワイヤボンドの1つの前記未封止部分は、前記空洞内に配置されている、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項27]
前記ワイヤボンドは、銅、金、アルミニウム、および半田からなる群から選択された少なくとも一種の材料から本質的になっている、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項28]
前記ワイヤボンドの少なくとも1つは、その長さに沿って長軸を画定しており、
各ワイヤボンドは、前記長軸に沿って延在する第1の材料の内層と、前記長軸から遠く離れ、このようなワイヤボンドの長さ方向に延在する長さを有する第2の材料の外層と、を備えている、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項29]
前記第1の材料は、銅、金、ニッケル、およびアルミニウムの一種であり、
前記第2の材料は、銅、金、ニッケル、アルミニウム、および半田の一種である、ことを特徴とする請求項28に記載の超小型電子パッケージ。
[請求項30]
前記複数のワイヤボンドは、第1のワイヤボンドであり、
前記超小型電子パッケージは、前記超小型電子素子上の接点に接合された基部と前記接点から遠く離れた端面とを有する少なくとも1つの第2のワイヤボンドをさらに備えており、
前記少なくとも1つの第2のワイヤボンドは、前記基部と前記端面との間に延在する縁面を画定しており、
前記少なくとも1つの第2のワイヤボンドの未封止部分は、第2のワイヤボンドの前記端面または前記封止層によって覆われていない第2のワイヤボンドの前記縁面の少なくとも一部によって画定されている、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項31]
前記少なくとも1つの超小型電子素子は、第1の超小型電子素子であり、
前記超小型電子パッケージは、前記第1の超小型電子素子の上に少なくとも部分的に重なる少なくとも1つの第2の超小型電子素子をさらに備えており、
前記ワイヤボンドは、第1のワイヤボンドであり、
前記超小型電子パッケージは、前記超小型型電子素子上の接点に接合された基部と、前記接点から遠く離れた端面とを有する少なくとも1つの第2のワイヤボンドを有しており、
前記少なくとも1つの第2のワイヤボンドは、前記基部と前記端面との間に延在する縁面を画定しており、
前記第2のワイヤボンドの未封止部分は、このような第2のワイヤボンドの前記端面の一部または前記封止層によって覆われていないこのような第2のワイヤボンドの前記縁面の少なくとも1つによって画定されている、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項32]
前記封止層の前記表面に沿って延在する再分配層をさらに備えており、
前記再分配層は、前記封止層の主面に隣接する第1の面を有する再分配基板を備えており、
前記再分配層は、
前記第1の表面から遠く離れた第2の表面と、
前記再分配基板の前記第1の表面上に露出し、前記ワイヤボンドのそれぞれの未封止部分と真っ直ぐに並んで機械的に接続された第1の導電パッドと、
前記基板の前記第2の表面に露出し、前記第1の導電パッドに電気的に接続された第2の導電パッドと、をさらに備えている、ことを特徴とする請求項1または10に記載の超小型電子パッケージ。
[請求項33]
超小型電子アセンブリにおいて、
請求項1または10に記載の第1の超小型電子パッケージと、
第1の表面および第2の表面を有する基板と、前記第1の表面に実装された第2の超小型電子素子と、前記第2の表面に露出し、前記第2の超小型電子素子に電気的に接続された接触パッドと、を備える第2の超小型電子パッケージと、
を備えており、
前記第2の超小型電子パッケージは、前記第2の超小型電子パッケージの前記第2の表面が前記誘電体封止層の前記表面の少なくとも一部の上に重なるように、かつ前記接触パッドの少なくともいくつかが前記ワイヤボンドの前記未封止部分の少なくともいくつかに電気的かつ機械的に接続されるように、前記第1の超小型電子パッケージに実装されている、ことを特徴とする超小型電子アセンブリ。
[請求項34]
超小型電子パッケージにおいて、
第1の領域および第2の領域を有する基板であって、第1の表面および前記第1の表面から遠く離れた第2の表面を有し、横方向に延在している、基板と、
前記第1の領域内において前記第1の表面の上に重なる超小型電子素子であって、前記基板から遠く離れた主面を有している、超小型電子素子と、
前記第2の領域内において前記基板の前記第1の表面に露出した導電要素であって、前記導電要素の少なくともいくつかは、前記超小型電子素子に電気的に接続されている、導電要素と、
前記第1の導電要素のそれぞれに接合された基部と、前記基板から遠く離れてかつ前記基部から遠く離れた端面とを有するワイヤボンドであって、各ワイヤボンドは、その前記基部と前記端面との間に延在する縁面を画定しており、第1のワイヤボンドは、第1の信号電位を送るように構成されており、第2のワイヤボンドは、前記第1の信号電位と異なる第2の信号電位を同時に送るように構成されている、ワイヤボンドと、
前記第1または第2の表面の少なくとも1つから延在する誘電体封止層であって、前記封止層は、前記ワイヤボンドが前記誘電体層によって互いに分離されるように、前記ワイヤボンド間の空間を充填しており、前記封止層は、前記基板の少なくとも前記第2の領域の上に重なっており、前記ワイヤボンドの未封止部分は、少なくとも前記封止層によって覆われていない前記ワイヤボンドの前記端面の一部によって画定されている、誘電体封止層と、
を備えており、
少なくとも1つのワイヤボンドの前記未封止部分は、前記未封止部分が前記超小型電子素子の前記主面の上に重なるように、前記少なくとも1つのワイヤボンドが接続された前記導電要素から前記第1の表面に沿って少なくとも1つの横方向に変位している、ことを特徴とする超小型電子アセンブリ。
[請求項35]
前記導電要素は、第1の所定の形態の第1のアレイに配置されており、
前記ワイヤボンドの前記未封止部分は、前記第1の所定の形態と異なる第2の所定の形態の第2のアレイに配置されている、ことを特徴とする請求項34に記載の超小型電子アセンブリ。
[請求項36]
前記第1の所定の形態は、第1のピッチによって特徴付けられており、
前記第2の所定の形態は、前記第1のピッチよりも細い第2のピッチによって特徴付けられている、ことを特徴とする請求項35に記載の超小型電子パッケージ。
[請求項37]
絶縁層が、前記超小型電子素子の少なくとも表面を覆って延在しており、
前記絶縁層は、前記超小型電子素子の前記表面と、前記超小型電子素子の前記主面の上に重なる未封止部分を有する前記少なくとも1つのワイヤボンドと、の間に配置されている、ことを特徴とする請求項34に記載の超小型電子パッケージ。
[請求項38]
前記ワイヤボンドのそれぞれの複数の前記未封止部分は、前記超小型電子素子の前記主面の上に重なっている、ことを特徴とする請求項34に記載の超小型電子パッケージ。
[請求項39]
超小型電子アセンブリにおいて、
請求項34に記載の第1の超小型電子パッケージと、
第1の表面および第2の表面を有する基板と、前記第1の表面に取り付けられた超小型電子素子と、前記第2の表面に露出し、前記超小型電子素子に電気的に接続された接触パッドと、を備える第2の超小型電子パッケージと、
を備えており、
前記第2の超小型電子パッケージは、前記第2のパッケージの前記第2の表面が前記誘電体層の前記表面の少なくとも一部の上に重なるように、かつ前記接触パッドの少なくともいくつかが前記ワイヤボンドの前記未封止部分の少なくともいくつかに電気的かつ機械的に接続されるように、前記第1の超小型電子パッケージに取り付けられている、ことを特徴とする超小型電子アセンブリ。
[請求項40]
前記第1の超小型電子パッケージの前記導電要素は、第1の所定の形態の第1のアレイに配置されており、
前記第2の超小型電子パッケージの前記接触パッドは、前記第1の所定の形態と異なる第2の所定の形態の第2のアレイに配置されている、ことを特徴とする請求項39に記載の超小型電子アセンブリ。
[請求項41]
前記第1の超小型電子パッケージの前記ワイヤボンドの前記未封止部分の少なくともいくつかは、前記第2の所定の形態に対応する第3のアレイに配置されている、ことを特徴とする請求項39に記載の超小型電子アセンブリ。
[請求項42]
前記第1の所定の形態は、第1のピッチによって特徴付けられており、
前記第2の形態は、前記第1のピッチよりも細い第2のピッチによって特徴付けられている、ことを特徴とする請求項39に記載の超小型電子アセンブリ。
[請求項43]
超小型電子アセンブリにおいて、
第1の超小型電子パッケージであって、
第1の領域および第2の領域を有する基板であって、第1の表面および前記第1の表面から遠く離れた第2の表面を有している、基板と、
前記第1の領域内において前記第1の表面の上に重なる少なくとも1つの超小型電子素子と、
前記第2の領域内において前記基板の前記第1の表面および前記第2の表面の少なくとも1つに露出した導電要素であって、前記導電要素の少なくともいくつかは、前記少なくとも1つの超小型電子素子に電気的に接続されている、導電要素と、
前記導電要素のそれぞれに接合された基部と前記基部から遠く離れた端面とを有するワイヤボンドであって、各ワイヤボンドは、その前記基部と前記端面との間に延在する端面を画定しており、前記基板から遠く離れた少なくとも一部を有している、ワイヤボンドと、
前記第1または第2の表面の少なくとも1つから延在する誘電体封止層であって、前記封止層は、前記ワイヤボンドが前記封止層によって互いに分離されるように前記ワイヤボンド間の空間を充填しており、前記誘電体封止層は、前記基板の少なくとも前記第2の領域の上に重なっており、前記ワイヤボンドの未封止部分は、前記前記封止層によって覆われていない前記ワイヤボンドの前記端面および前記縁面の1つの少なくとも一部によって画定されている、誘電体封止層と、
を備えている、第1の超小型電子パッケージと、
第2の超小型電子素子と、前記第2の超小型電子素子に電気的に接続されており、前記第2の超小型電子パッケージの表面に露出した接触パッドとを備える第2の超小型電子パッケージであって、前記第2の超小型電子パッケージは、前記接触パッドの少なくともいくつかが前記ワイヤボンドの前記未封止部分の少なくともいくつかに電気的かつ機械的に接続されるように、前記第1の超小型電子パッケージに実装されている、第2の超小型電子パッケージと、
を備えている、ことを特徴とする超小型電子アセンブリ。
[請求項44]
前記第2の超小型電子パッケージは、第1の表面および第2の表面を有する基板を備えており、
前記第2の超小型電子素子は、前記第1の表面に実装されており、
前記第2の超小型電子パッケージの前記第2の表面は、前記誘電体封止層の前記表面の少なくとも一部と向き合っている、ことを特徴とする請求項43に記載の超小型電子アセンブリ。
[請求項45]
前記ワイヤボンドの前記端面は、前記基板から遠く離れており、
前記ワイヤボンドの前記未封止部分は、少なくとも前記ワイヤボンドの前記端面によって画定されている、ことを特徴とする請求項43に記載の超小型電子アセンブリ。
[請求項46]
前記ワイヤボンドの前記端面は、前記基板から遠く離れており、
前記ワイヤボンドの前記未封止部分は、少なくとも前記ワイヤボンドの前記端面に隣接する前記縁面によって画定されている、ことを特徴とする請求項43に記載の超小型電子アセンブリ。
[請求項47]
前記ワイヤボンドの前記端面は、前記基板の特徴部に接合されており、
前記縁面は、前記基部と前記端面との間に配置されて前記基板から遠く離れた頂部を画定しており、
前記ワイヤボンドの前記未封止部分は、前記頂部に隣接する前記縁面の領域によって画定されている、ことを特徴とする請求項43に記載の超小型電子アセンブリ。
[請求項48]
超小型電子アセンブリにおいて、
第1の領域および第2の領域を有する基板であって、第1の表面および前記第1の表面から遠く離れた第2の表面を有している、基板と、
前記第1の領域内において前記第1の表面の上に重なる少なくとも1つの超小型電子素子と、
前記第2の領域内において前記基板の前記第1の表面に露出した導電要素であって、前記導電要素の少なくともいくつかが、前記少なくとも1つの超小型電子素子に電気的に接続されている、導電要素と、
複数のボンド要素であって、各々が、第1の基部と、第2の基部と、前記基部間に延在する縁面と,を有しており、前記第1の基部は、前記導電要素の1つに接合されており、前記縁面は、接触パッドから前記基板から遠く離れた前記縁面の頂部に延在する第1の部分を備えており、前記縁面は、前記頂部から前記第2の基部に延在する第2の部分をさらに備えており、前記第2の基部は、前記基板の特徴部に接合されている、複数のボンド要素と、
前記第1または第2の表面の少なくとも1つから延在する誘電体封止層であって、前記封止層は、前記ボンド要素が前記封止層によって互いに分離されるように、前記ボンド要素の前記第1および第2の部分間の空間および前記複数のボンド要素間の空間を充填しており、前記封止層は、少なくとも前記基板の前記第2の領域の上に重なっており、前記ボンド要素の未封止部分は、前記封止層によって覆われていない前記頂部の周りの前記ボンド要素の前記縁面の少なくとも一部によって画定されている、誘電体封止層と、
を備えている、ことを特徴とする超小型電子パッケージ。
[請求項49]
前記ボンド要素は、ワイヤボンドである、ことを特徴とする請求項48に記載の超小型電子パッケージ。
[請求項50]
前記基板の前記第2の基部が接合される前記基板の前記特徴部は、前記第1の基部が接続される前記導電要素である、ことを特徴とする請求項49に記載の超小型電子パッケージ。
[請求項51]
前記基板の前記第2の基部が接合される前記基板の前記特徴部は、前記第1の基部が接合される前記導電要素と異なる各導電要素である、ことを特徴とする請求項49に記載の超小型電子パッケージ。
[請求項52]
前記第2の基部が接合される前記導電要素は、前記超小型電子要素に電気的に接続されていない、ことを特徴とする請求項51に記載の超小型電子パッケージ。
[請求項53]
前記ボンド要素は、ボンドリボンである、ことを特徴とする請求項48に記載の超小型電子素子。
[請求項54]
前記第1の基部の一部は、前記各接触パッドの一部に沿って延在しており、
前記第2の基部が接合される前記特徴部は、前記各接触パッドの一部に沿って延在する前記第1の基部の長さ部分である、ことを特徴とする請求項53に記載の超小型電子素子。
[請求項55]
前記基板の前記第1の表面は、前記第1および第2の横方向に延在しており、
各横方向は、前記第1および第2の表面間において前記基板の厚みの方向を横断しており、
前記ワイヤボンドの少なくとも1つの前記未封止部分は、前記少なくとも1つのワイヤボンドが接合された前記導電要素から前記横方向の少なくとも1つにおいて変位している、ことを特徴とする請求項48に記載の超小型電子パッケージ。
[請求項56]
前記少なくとも1つのワイヤボンドの前記未封止部分は、前記超小型電子素子の主面の上に重なっている、ことを特徴とする請求項55に記載の超小型電子パッケージ。
[請求項57]
超小型電子パッケージを製造する方法において、
誘電体封止層を処理中ユニット上に形成するステップであって、前記処理中ユニットは、第1の表面およびそこから遠く離れた第2の表面を有する基板と、前記基板の前記第1の表面に実装された超小型電子素子と、前記第1の表面に露出した複数の導電要素であって、前記導電要素の少なくともいくつかは、前記超小型電子素子に電気的に接続されている、複数の導電要素と、前記導電要素に接合された基部および前記基部から遠く離れた端面を有するワイヤボンであって、各ワイヤボンドは、前記基部と前記端面との間に延在する縁面を画定しており、前記ワイヤボンドの第1のものは、第1の信号電位を送るように構成されており、前記ワイヤボンドの第2のものは、前記第1の信号電子と異なる第2の信号電位を同時に送るように構成されている、ワイヤボンドと、を備えている、ステップを含んでおり、
前記封止層は、前記第1の表面および前記ワイヤボンドの一部を少なくとも部分的に覆うように形成されており、前記ワイヤボンドの未封止部分は、前記封止層によって覆われていない前記端面または前記縁面の少なくとも1つの一部によって画定されている、ことを特徴とする方法。
[請求項58]
前記基板は、リードフレームであり、前記導電要素は、前記リードフレームのリードである、ことを特徴とする請求項57に記載の超小型電子素子。
[請求項59]
前記封止層を形成する前記ステップは、誘電体材料塊を前記第1の表面および前記ワイヤボンドの実質的に全てを覆って堆積させ、その前記未封止部分を画定するために、前記誘電体材料塊の部分を除去し、前記ワイヤボンドの一部を露出させることを含んでいる、ことを特徴とする請求項58に記載の方法。
[請求項60]
前記ワイヤボンドの少なくとも1つは、前記導電要素の少なくとも2つの各々に接合されたループをなすように延ばされており、
前記誘電体材料塊は、前記第1の表面および前記少なくとも1つのワイヤボンドループを少なくとも部分的に覆うように堆積されており、
前記誘電体材料塊の一部を除去する前記ステップは、前記少なくとも1つのワイヤボンドループを前記封止層によって覆われていないそれぞれの自由端を有する第1および第2のワイヤボンドに切断し、その未封止部分を形成するように、前記少なくとも1つのワイヤボンドループの一部を除去することをさらに含んでいる、ことを特徴とする請求項59に記載の方法。
[請求項61]
ワイヤの第1の端を前記導電要素に接合し、前記ワイヤを前記第1の表面から離れる方向に引き出し、
前記ワイヤを前記第1の表面に沿って少なくとも横方向に引き出し、
前記ワイヤを前記第2の導電要素の方に引き出し、かつ前記ワイヤを前記第2の導電要素に接合することを含むステップによって、前記処理中ユニットの前記ループを形成することをさらに含んでいる、ことを特徴とする請求項60に記載の方法。
[請求項62]
誘電体材料塊を前記基板の前記第1の表面から離れた位置から、前記ワイヤボンドの前記少なくとも1つが前記誘電体材料塊を貫通するように、前記ワイヤボンドの上に押圧し、前記基板の前記第1の表面に接触させることによって、前記封止層が前記処理中ユニット上に形成されるようになっている、ことを特徴とする、請求項57に記載の方法。
[請求項63]
前記ワイヤボンドは、金、銅、アルミニウム、または半田から本質的になるワイヤから作製されている、ことを特徴とする請求項57に記載の方法。
[請求項64]
前記第1のワイヤボンドは、アルミニウムを含んでおり、前記ワイヤボンドは、ウエジボンディングによって、前記導電要素に接合されるようになっている、ことを特徴とする請求項57に記載の方法。
[請求項65]
前記基板の前記第1の表面は、横方向に延在しており、
前記ワイヤボンドの少なくとも1つの前記未封止部分は、前記ワイヤボンドの前記端面が前記少なくとも1つのワイヤボンドが接合された前記導電要素から前記横方向の少なくとも1つにおいて変位するように、形成されている、ことを特徴とする請求項57に記載の方法。
[請求項66]
前記処理中ユニットは、前記ワイヤボンドの少なくとも1つが前記導電要素と前記少なくとも1つのワイヤボンドの前記端面との間に位置する実質的に湾曲した部分を備えるように、前記ワイヤボンドを形成するステップを含むことを特徴とする請求項57に記載の方法。
[請求項67]
前記基板は、第1の領域および第2の領域を備えており、
前記超小型電子素子は、前記第1の領域の上に重なっており、前記基板から遠く離れた主面を有しており、
前記第1の導電要素は、前記第1の領域内に配置されており、
前記処理中ユニットは、前記ワイヤボンドの少なくとも1つの少なくとも一部が前記超小型電子素子の前記主面を覆って延在するように、
前記ワイヤボンドを形成するステップを含むことを特徴とする請求項57に記載の方法。
[請求項68]
前記封止層を形成する前記ステップは、前記封止層の主面から前記基板の方に延在する少なくとも1つの空洞を形成することを含んでおり、
前記少なくとも1つの空洞は、前記ワイヤボンドの1つの前記未封止部分を包囲している、ことを特徴とする請求項57に記載の方法。
[請求項69]
前記少なくとも1つの空洞は、前記基板上に誘電体封止材料を堆積させた後、前記封止材料の湿式エッチング、乾式エッチング、またはレーザーエッチングの少なくとも1つによって形成されるようになっている、ことを特徴とする請求項68に記載の方法。
[請求項70]
前記少なくとも1つの空洞は、前記基板および前記少なくとも1つのワイヤボンド上に誘電体封止材料を堆積した後、前記ワイヤボンドの少なくとも1つの所定位置から犠牲材料の塊の少なくとも一部を除去することによって、形成されるようになっている、ことを特徴とする請求項68に記載の方法。
[請求項71]
前記封止層を形成する前記ステップは、前記犠牲材料の塊の一部が前記封止層の主面上に露出し、
前記犠牲材料の塊の前記露出部が、前記ワイヤボンドの前記自由端の近くの部分を包囲し、前記封止層の一部を前記自由端の近くの部分から離間する、ように行われるようになっている、ことを特徴とする請求項70に記載の方法。
[請求項72]
前記ワイヤボンドの少なくとも1つは、その長さに沿って長軸を画定しており、
前記犠牲材料の塊の第2の部分は、前記基部に隣接する箇所から前記少なくとも1つのワイヤボンドの前記長軸に沿って延在しており、前記犠牲材料の塊の少なくとも一部を除去する前記ステップの後に残るようになっている、ことを特徴とする請求項70に記載の方法。
[請求項73]
前記ワイヤボンドは、その長さに沿って長軸を画定しており、
前記ワイヤボンドは、前記長軸に沿って延在する第1の材料の内層と、前記長軸から遠く離れて前記ワイヤボンドの前記長さに沿って延在する第2の材料の外層と、を備えている、ことを特徴とする請求項57に記載の方法。
[請求項74]
前記第1の材料は、銅であり、前記第2の材料は、半田である、ことを特徴とする請求項73に記載の方法。
[請求項75]
前記封止層を形成する前記ステップの後、前記ワイヤボンドの前記内層の前記縁面の一部を露出させるために、前記第2の材料の一部が除去され、前記誘電体層の表面から延在する空洞を形成するようになっている、ことを特徴とする請求項73に記載の方法。
[請求項76]
前記ワイヤボンドの少なくとも1つの前記未封止部分上にスタッドバンプを形成することをさらに含んでいる、ことを特徴とする請求項57に記載の方法。
[請求項77]
前記ワイヤボンドの少なくとも1つの前記未封止部分上に半田ボールを堆積させることをさらに含んでいる、ことを特徴とする請求項57に記載の方法。
[請求項78]
超小型電子アセンブリを製造する方法において、請求項42の前記ステップによって作製された第1の超小型電子パッケージを第2の超小型電子パッケージに接合するステップを含んでおり、
前記第2の超小型電子パッケージは、第1の表面を有する基板および前記基板の前記第1の表面に露出した複数の接点を備えており、
前記第1の超小型電子パッケージを前記第2の超小型電子パッケージに接合する前記ステップは、前記第1の超小型電子パッケージの前記ワイヤボンドの前記未封止部分を前記第2の超小型電子パッケージの前記接点に電気的かつ機械的に接続することを含んでいる、ことを特徴とする方法。
[請求項79]
超小型電子パッケージを製造する方法において、
誘電体材料塊を処理中ユニットを覆って配置するステップであって、前記処理中ユニットは、第1の表面およびそこから遠く離れた第2の表面を有する基板と、前記第1の表面に露出した複数の薄い導電要素と、前記薄い導電要素のそれぞれに接合された基部と、前記基板から遠く離れてかつ前記基部から遠く離れた端面と、を有するワイヤボンドであって、各ワイヤボンドは、その前記基部と前記端面との間に延在する縁面を画定しており、第1の前記ワイヤボンドは、第1の信号電位を送るように構成されており、第2のワイヤボンドは、前記第1の信号電位と異なる第2の信号電位を同時に送るように構成されている、ワイヤボンドと、を備えている、ステップと、
前記ワイヤボンドが前記誘電体材料塊を貫通するように、前記誘電体材料塊を前記ワイヤボンドの上に押圧し、前記基板の前記第1の表面に接触させることによって、封止層を前記処理中ユニット上に形成するステップであって、前記封止層は、前記ワイヤボンドが前記封止層によって互いに分離されるように、前記ワイヤボンド間の空間を充填し、前記封止層は、前記基板の少なくとも前記第2の領域の上に重なり、前記第1のワイヤボンドの未封止部分は、前記第1のワイヤボンドの一部が前記封止層によって覆われないように、前記ワイヤボンドが前記封止層の一部を貫通することによって形成されるようになっている、ステップと、
を含んでいる、ことを特徴とする方法。
[請求項80]
超小型電子パッケージを製造する方法において、
誘電体封止層を処理中ユニット上に形成するステップであって、前記処理中ユニットは、第1の表面およびそこから遠く離れた第2の表面を有する基板と、前記第1の表面に露出した複数の薄い導電要素と、前記薄い導電要素の少なくとも2つのそれぞれに第1の基部および第2の基部において接合されたワイヤループであって、前記封止層は、前記第1の表面および前記少なくとも1つのワイヤループを少なくとも部分的に覆うように形成されている、ワイヤループと、を備えている、ステップと、
前記ワイヤループの各々を、前記第1および第2の基部のそれぞれに対応すると共に前記基板から遠く離れてかつ前記基部から遠く離れた端面を有する個別のワイヤボンドに分断するように、前記封止層の一部および前記ワイヤループの一部を除去するステップであって、各ワイヤボンドは、その前記基部と前記端面との間に延在する縁面を画定しており、前記封止層は、前記ワイヤボンドが前記封止層によって分離されるように、前記ワイヤボンド間の空間を充填しており、前記ワイヤボンドは、前記封止層によって少なくとも部分的に覆われていない前記ワイヤボンドの自由端によって形成された未封止部分を有しており、前記ワイヤボンドの第1のものは、第1の信号電位を送るように構成されており、前記ワイヤボンドの第2のものは、前記第1の信号電子と異なる第2の信号電位を同時に送るように構成されている、ステップと、
を含んでいる、ことを特徴とする方法。
[請求項81]
請求項1,10のいずれか1つに記載の超小型電子パッケージと、前記超小型電子アセンブリに電気的に接続された1つまたは複数の他の電子コンポーネントとを備えるシステム。
[請求項82]
ハウジングをさらに備えており、前記超小型電子アセンブリおよび前記他の電子コンポーネントは、前記ハウジングに実装されている、ことを特徴とする請求項81に記載のシステム。
Claims (23)
- 超小型電子パッケージにおいて、
第1の領域および第2の領域を有する基板であって、横方向に延びている第1の表面および前記第1の表面から遠く離れた第2の表面を有している、基板と、
前記第1の領域内において前記第1の表面の上に重なる少なくとも1つの超小型電子素子と、
前記第2の領域内において前記基板の前記第1の表面に露出した第1の導電要素であって、前記導電要素の少なくともいくつかは、前記少なくとも1つの超小型電子素子に電気的に接続されている、第1の導電要素と、
前記第1の導電要素のそれぞれに接合された基部と、前記基板から遠く離れてかつ前記基部から遠く離れた端面とを有する複数のワイヤボンドであって、各ワイヤボンドは、その前記基部と前記端面との間に延在する縁面を画定しており、第1のワイヤボンドは、第1の信号電位を送るように構成されており、第2のワイヤボンドは、前記第1の信号電位と異なる第2の信号電位を同時に送るように構成されている、複数のワイヤボンドと、
前記第1の表面から延在する誘電体封止層であって、前記封止層は、前記ワイヤボンドが前記封止層によって互いに分離されるように前記ワイヤボンド間の空間を充填しており、前記封止層は、前記基板の少なくとも前記第2の領域の上に重なっており、前記ワイヤボンドの未封止部分は、少なくとも前記封止層によって覆われていない前記ワイヤボンドの前記端面の一部によって画定されている、誘電体封止層と、
前記ワイヤボンドの前記未封止部分に電気的に接続されている第2の導電要素であって、前記第1の導電要素と接触しない第2の導電要素と、
を備え、
前記ワイヤボンドの少なくとも1つの前記未封止部分は、前記超小型電子素子の主面の上に重なり、前記少なくとも1つのワイヤボンドが接合された前記第1の導電要素から、前記横方向の少なくとも1つにおいて変位しており、
前記第1の導電要素は、第1の所定の形態の第1のアレイ内に配置され、前記ワイヤーボンドの前記未封止部分は、前記第1の所定の形態とは異なる第2の所定の形態の第2のアレイ内に配置され、
前記第1の所定の形態は、前記少なくとも1つの横方向の第1方向における第1ピッチによって特徴付けられ、前記第2の所定の形態は、前記第1方向における前記第1ピッチよりも細い第2のピッチによって特徴付けられており、
前記封止層の前記表面に沿って延在する再分配層をさらに備えており、
前記再分配層は、前記封止層の主面に隣接する第1の面を有する再分配基板を備えており、
前記再分配層は、
前記第1の表面から遠く離れた第2の表面と、
前記再分配基板の前記第1の表面上に露出し、前記ワイヤボンドのそれぞれの未封止部分と真っ直ぐに並んで機械的に接続された第1の導電パッドと、
前記基板の前記第2の表面に露出し、前記第1の導電パッドに電気的に接続された第2の導電パッドと、をさらに備えていることを特徴とする超小型電子パッケージ。 - 前記ワイヤボンドの少なくとも1つの前記端面に隣接する少なくとも一部は、前記封止層の表面と直交している、ことを特徴とする請求項1に記載の超小型電子パッケージ。
- 前記第2の導電要素は、前記第1のワイヤボンドの少なくともいくつかの前記端面に接合された複数のスタッドバンプを備えている、ことを特徴とする請求項1に記載の超小型電子パッケージ。
- 前記ワイヤボンドの少なくとも1つは、その前記基部と前記未封止部分との間で実質的に直線に沿って延在しており、前記実質的な直線は、前記基板の前記第1の表面に対して90°未満の角度をなしている、ことを特徴とする請求項1に記載の超小型電子パッケージ。
- 超小型電子パッケージにおいて、
第1の領域および第2の領域を有する基板であって、横方向に延びている第1の表面および前記第1の表面から遠く離れた第2の表面を有している、基板と、
前記第1の領域内において前記第1の表面の上に重なる少なくとも1つの超小型電子素子と、
前記第2の領域内において前記基板の前記第1の表面に露出した導電要素であって、前記導電要素の少なくともいくつかは、前記少なくとも1つの超小型電子素子に電気的に接続されている、導電要素と、
前記導電要素のそれぞれに接合された基部と、前記基板から遠く離れてかつ前記基部から遠く離れた端面とを有する複数のワイヤボンドであって、各ワイヤボンドは、その前記基部と前記端面との間に延在する縁面を画定しており、第1の前記ワイヤボンドは、第1の信号電位を送るように構成されており、第2の前記ワイヤボンドは、前記第1の信号電位と異なる第2の信号電位を同時に送るように構成されている、複数のワイヤボンドと、
前記第1の表面から延在する誘電体封止層であって、前記封止層は、前記ワイヤボンドが前記封止層によって互いに分離されるように、前記ワイヤボンド間の空間を充填しており、前記封止層は、前記基板の少なくとも前記第2の領域の上に重なっており、前記ワイヤボンドの未封止部分は、少なくとも前記封止層によって覆われていない前記ワイヤボンドの前記端面に隣接する前記縁面の一部によって画定されており、前記封止層によって覆われていない前記縁面の前記一部の最長寸法は、前記封止層の表面と平行な方向に延在している、誘電体封止層と、
を備え、
前記ワイヤボンドの少なくとも1つの前記未封止部分は、前記超小型電子素子の主面の上に重なり、前記少なくとも1つのワイヤボンドが接合された前記導電要素から、前記横方向の少なくとも1つにおいて変位しており、
前記導電要素は、第1の所定の形態の第1のアレイ内に配置され、前記ワイヤーボンドの前記未封止部分は、前記第1の所定の形態とは異なる第2の所定の形態の第2のアレイ内に配置され、
前記第1の所定の形態は、前記少なくとも1つの横方向の第1方向における第1ピッチによって特徴付けられ、前記第2の所定の形態は、前記第1方向における前記第1ピッチよりも細い第2のピッチによって特徴付けられていることを特徴とする超小型電子パッケージ。 - 前記未封止部分の少なくとも1つは、前記封止層によって覆われていない前記端面の少なくとも一部によって更に画定されている、ことを特徴とする請求項5に記載の超小型電子パッケージ。
- 前記封止層によって覆われず、前記封止層の前記表面と平行に延在する前記縁面の前記一部の長さは、前記ワイヤボンドの断面幅よりも大きくなっている、ことを特徴とする請求項5に記載の超小型電子パッケージ。
- 前記ワイヤボンドの少なくとも1つは、その長さに沿って長軸を画定しており、
各ワイヤボンドは、前記長軸に沿って延在する第1の材料の内層と、前記長軸から遠く離れ、このようなワイヤボンドの長さ方向に延在する長さを有する第2の材料の外層と、を備えている、ことを特徴とする請求項1または5に記載の超小型電子パッケージ。 - 前記封止層の前記表面に沿って延在する再分配層をさらに備えており、
前記再分配層は、前記封止層の主面に隣接する第1の面を有する再分配基板を備えており、
前記再分配層は、
前記第1の表面から遠く離れた第2の表面と、
前記再分配基板の前記第1の表面上に露出し、前記ワイヤボンドのそれぞれの未封止部分と真っ直ぐに並んで機械的に接続された第1の導電パッドと、
前記基板の前記第2の表面に露出し、前記第1の導電パッドに電気的に接続された第2の導電パッドと、をさらに備えている、ことを特徴とする請求項5に記載の超小型電子パッケージ。 - 前記封止層は、前記封止層の表面から前記基板に向かって延在するように形成された空洞を有しており、
少なくとも1つの前記ワイヤボンドの前記未封止部分は、前記空洞内に配置されており、
前記未封止部分の先端に堆積されている半田ボールは、前記空洞内に配置されていることを特徴とする、ことを特徴とする請求項1または5に記載の超小型電子パッケージ。 - 超小型電子パッケージを製造する方法において、
誘電体封止層を処理中ユニット上に形成するステップを含み、
前記処理中ユニットは、第1の表面およびそこから遠く離れた第2の表面を有する基板であって、前記第1の表面が横方向に延びている、基板と、前記基板の前記第1の表面に実装された超小型電子素子と、前記第1の表面に露出した複数の導電要素であって、前記導電要素の少なくともいくつかは、前記超小型電子素子に電気的に接続されている、複数の導電要素と、前記導電要素に接合された基部および前記基部から遠く離れた端面を有するワイヤボンであって、各ワイヤボンドは、前記基部と前記端面との間に延在する縁面を画定しており、前記ワイヤボンドの第1のものは、第1の信号電位を送るように構成されており、前記ワイヤボンドの第2のものは、前記第1の信号電子と異なる第2の信号電位を同時に送るように構成されている、ワイヤボンドと、を備え、
前記封止層は、前記第1の表面および前記ワイヤボンドの一部を少なくとも部分的に覆うように形成されており、前記ワイヤボンドの未封止部分は、前記封止層によって覆われていない前記端面または前記縁面の少なくとも1つの一部によって画定され、前記端面が形成された前記ワイヤボンドの少なくとも1つの前記未封止部分は、前記超小型電子素子の主面の上に重なり、前記少なくとも1つのワイヤボンドが接合された前記導電要素から、前記第1の表面に沿って、前記横方向の少なくとも1つにおいて変位しており、
前記導電要素は、第1の所定の形態の第1のアレイ内に配置され、前記ワイヤーボンドの前記未封止部分は、前記第1の所定の形態とは異なる第2の所定の形態の第2のアレイ内に配置され、
前記第1の所定の形態は、前記少なくとも1つの横方向の第1方向における第1ピッチによって特徴付けられ、前記第2の所定の形態は、前記第1方向における前記第1ピッチよりも細い第2のピッチによって特徴付けられており、
誘電体材料塊を前記基板の前記第1の表面から離れた位置から、前記ワイヤボンドの前記少なくとも1つが前記誘電体材料塊を貫通するように、前記ワイヤボンドの上に押圧し、前記基板の前記第1の表面に接触させることによって、前記封止層が前記処理中ユニット上に形成されるようになっていることを特徴とする、方法。 - 前記基板は、リードフレームであり、前記導電要素は、前記リードフレームのリードである、ことを特徴とする請求項11に記載の方法。
- 前記封止層を形成する前記ステップは、誘電体材料塊を前記第1の表面および前記ワイヤボンドの実質的に全てを覆って堆積させ、その前記未封止部分を画定するために、前記誘電体材料塊の部分を除去し、前記ワイヤボンドの一部を露出させることを含んでいる、
ことを特徴とする請求項11に記載の方法。 - 前記ワイヤボンドの少なくとも1つは、前記導電要素の少なくとも2つの各々に接合されたループをなすように延ばされており、
前記誘電体材料塊は、前記第1の表面および前記少なくとも1つのワイヤボンドループを少なくとも部分的に覆うように堆積されており、
前記誘電体材料塊の一部を除去する前記ステップは、前記少なくとも1つのワイヤボンドループを前記封止層によって覆われていないそれぞれの自由端を有する第1および第2のワイヤボンドに切断し、その未封止部分を形成するように、前記少なくとも1つのワイヤボンドループの一部を除去することをさらに含んでいる、ことを特徴とする請求項13に記載の方法。 - 前記処理中ユニットは、前記ワイヤボンドの少なくとも1つが前記導電要素と前記少なくとも1つのワイヤボンドの前記端面との間に位置する実質的に湾曲した部分を備えるように、前記ワイヤボンドを形成するステップを含むことを特徴とする請求項11に記載の方法。
- 前記基板は、第1の領域および第2の領域を備えており、
前記超小型電子素子は、前記第1の領域の上に重なっており、前記基板から遠く離れた主面を有しており、
前記導電要素は、前記第1の領域内に配置されており、
前記処理中ユニットは、前記ワイヤボンドの少なくとも1つの少なくとも一部が前記超小型電子素子の前記主面を覆って延在するように、
前記ワイヤボンドを形成するステップを含むことを特徴とする請求項11に記載の方法。 - 前記封止層を形成する前記ステップは、前記封止層の主面から前記基板の方に延在する少なくとも1つの空洞を形成することを含んでおり、
前記少なくとも1つの空洞は、前記ワイヤボンドの1つの前記未封止部分を包囲している、ことを特徴とする請求項11に記載の方法。 - 前記ワイヤボンドは、その長さに沿って長軸を画定しており、
前記ワイヤボンドは、前記長軸に沿って延在する第1の材料の内層と、前記長軸から遠く離れて前記ワイヤボンドの前記長さに沿って延在する第2の材料の外層と、を備えている、ことを特徴とする請求項11に記載の方法。 - 前記ワイヤボンドの少なくとも1つの前記未封止部分上にスタッドバンプを形成することをさらに含んでいる、ことを特徴とする請求項11に記載の方法。
- 前記ワイヤボンドの少なくとも1つの前記未封止部分上に半田ボールを堆積させることをさらに含んでいる、ことを特徴とする請求項11に記載の方法。
- 超小型電子アセンブリを製造する方法において、請求項11の前記ステップによって作製された第1の超小型電子パッケージを第2の超小型電子パッケージに接合するステップを含んでおり、
前記第2の超小型電子パッケージは、第1の表面を有する基板および前記基板の前記第1の表面に露出した複数の接点を備えており、
前記第1の超小型電子パッケージを前記第2の超小型電子パッケージに接合する前記ステップは、前記第1の超小型電子パッケージの前記ワイヤボンドの前記未封止部分を前記第2の超小型電子パッケージの前記接点に電気的かつ機械的に接続することを含んでいる、ことを特徴とする方法。 - 超小型電子パッケージを製造する方法において、
誘電体材料塊を処理中ユニットを覆って配置するステップであって、前記処理中ユニットは、第1の表面およびそこから遠く離れた第2の表面を有する基板と、前記第1の表面に露出した複数の薄い導電要素と、前記薄い導電要素のそれぞれに接合された基部と、前記基板から遠く離れてかつ前記基部から遠く離れた端面と、を有するワイヤボンドであって、各ワイヤボンドは、その前記基部と前記端面との間に延在する縁面を画定しており、第1の前記ワイヤボンドは、第1の信号電位を送るように構成されており、第2のワイヤボンドは、前記第1の信号電位と異なる第2の信号電位を同時に送るように構成されている、ワイヤボンドと、を備えている、ステップと、
前記ワイヤボンドが前記誘電体材料塊を貫通するように、前記誘電体材料塊を前記ワイヤボンドの上に押圧し、前記基板の前記第1の表面に接触させることによって、封止層を前記処理中ユニット上に形成するステップであって、前記封止層は、前記ワイヤボンドが前記封止層によって互いに分離されるように、前記ワイヤボンド間の空間を充填し、前記封止層は、前記基板の少なくとも前記第2の表面の上に重なり、前記第1のワイヤボンドの未封止部分は、前記第1のワイヤボンドの一部が前記封止層によって覆われないように、前記ワイヤボンドが前記封止層の一部を貫通することによって形成されるようになって、前記端面が形成された前記ワイヤボンドの少なくとも1つの前記未封止部分は、超小型電子素子の主面の上に重なり、前記少なくとも1つのワイヤボンドが接合された前記導電要素から、前記第1の表面に沿って、横方向の少なくとも1つにおいて変位している、ステップと、
を含んでおり、
前記導電要素は、第1の所定の形態の第1のアレイ内に配置され、前記ワイヤーボンドの前記未封止部分は、前記第1の所定の形態とは異なる第2の所定の形態の第2のアレイ内に配置され、
前記第1の所定の形態は、前記少なくとも1つの横方向の第1方向における第1ピッチによって特徴付けられ、前記第2の所定の形態は、前記第1方向における前記第1ピッチよりも細い第2のピッチによって特徴付けられていることを特徴とする、方法。 - 前記封止層は、前記封止層の表面から前記基板に向かって延在するように形成された空洞を有しており、
少なくとも1つの前記ワイヤボンドの前記未封止部分は、前記空洞内に配置されており、
前記未封止部分の先端に堆積されている半田ボールは、前記空洞内に配置されていることを特徴とする、ことを特徴とする請求項11又は22に記載の方法。
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US20170287733A1 (en) | 2017-10-05 |
US20210050322A1 (en) | 2021-02-18 |
US9224717B2 (en) | 2015-12-29 |
US10062661B2 (en) | 2018-08-28 |
US10833044B2 (en) | 2020-11-10 |
TWI467732B (zh) | 2015-01-01 |
US11424211B2 (en) | 2022-08-23 |
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